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1. 发明授权

US08266482B2 Operating parameter control for integrated circuit signal paths 有权
标题翻译：集成电路信号路径的工作参数控制
公开(公告)号：US08266482B2
公开(公告)日：2012-09-11
申请号：US12087007
申请日：2006-01-31
申请人： Andrew David Tune , Alistair Crone Bruce , Simon Crossley , Robin Hotchkiss
发明人： Andrew David Tune , Alistair Crone Bruce , Simon Crossley , Robin Hotchkiss
IPC分类号： G06F11/00
CPC分类号： H04L1/0001 , H04L1/0009 , H04L1/0033
摘要： An integrated circuit includes a signal source and a signal destination linked by a signal path. Error correction codes (e.g. Hamming codes) are applied to the signals to be transmitted. Errors detected in the signal transmission are used to control an operating parameter of the signal path, such as signal voltage level, body bias voltage, clock frequency and/or temperature. The control applied is closed-loop feedback control seeking to maintain a finite non-zero predetermined error rate. The technique can also be used between a memory accessing integrated circuit and a separate memory integrated circuit. Furthermore, the technique can be used to provide fixed, but differing operating parameters for signal lines within a signal path. Control signals which may be timing critical are passed with appropriate operating parameters, such as a high signal voltage level, where as other signals, such as address and data signals, are passed with a different appropriate operating parameter, such as a low signal voltage level.
摘要翻译：集成电路包括信号源和由信号路径链接的信号目的地。错误校正码（例如汉明码）被应用于要发送的信号。在信号传输中检测到的错误用于控制信号路径的工作参数，例如信号电压电平，体偏置电压，时钟频率和/或温度。所施加的控制是闭环反馈控制，寻求维持有限的非零预定误差率。该技术还可以用于存储器访问集成电路和单独的存储器集成电路之间。此外，该技术可用于为信号路径内的信号线提供固定但不同的操作参数。可能具有时序关键性的控制信号通过适当的操作参数（例如高信号电压电平）传递，其中随着诸如地址和数据信号的其它信号通过不同的适当的操作参数，例如低信号电压电平。

2. 发明授权

US08619554B2 Interconnecting initiator devices and recipient devices 有权
标题翻译：互连发起者设备和收件人设备
公开(公告)号：US08619554B2
公开(公告)日：2013-12-31
申请号：US11498985
申请日：2006-08-04
申请人： Andrew David Tune , Robin Hotchkiss
发明人： Andrew David Tune , Robin Hotchkiss
IPC分类号： G01R31/08 , H04L12/56
CPC分类号： H04L45/28 , G06F15/16 , G06F15/17375 , H04L69/14
摘要： An interconnect block for a data processing apparatus, said interconnect block being operable to provide data routes via which one or more initiator devices may access one or more recipient devices, said interconnect block comprising: a first and a second portion; said first portion comprising at least one initiator port for communicating with one of said initiator devices, and at least one recipient port for communicating with one of said recipient devices; said second portion comprising at least two recipient ports for communicating with at least two recipient devices, said second portion being connected to said first portion via at least two parallel connecting routes, said at least two recipient ports being connectable to said at least two parallel connecting routes; wherein in response to a request received from one of said initiator devices at said first portion to perform a transaction accessing one of said at least two recipients in communication with said second portion, said interconnect block is operable to provide a data route between said initiator device and said recipient device via said at least two parallel connecting routes and to maintain said data route for the duration of said transaction.
摘要翻译：一种用于数据处理设备的互连块，所述互连块可操作以提供一个或多个启动器设备经由其访问一个或多个接收器设备的数据路由，所述互连块包括：第一和第二部分; 所述第一部分包括用于与所述发起者设备之一进行通信的至少一个启动器端口以及用于与所述接收设备之一通信的至少一个接收端口; 所述第二部分包括用于与至少两个接收装置通信的至少两个接收端口，所述第二部分经由至少两个并行连接路径连接到所述第一部分，所述至少两个接收端口可连接到所述至少两个并联连接路线其中响应于从所述第一部分的所述发起者设备之一接收的请求，以执行与所述第二部分通信的所述至少两个接收者之一的事务，所述互连块可操作以提供所述启动器设备之间的数据路由并且经由所述至少两个并行连接路由表示所述接收方设备，并且在所述事务持续期间保持所述数据路由。

3. 发明授权

US07945806B2 Data processing apparatus and method for controlling a transfer of payload data over a communication channel 有权
标题翻译：用于控制通过通信信道传输有效载荷数据的数据处理装置和方法
公开(公告)号：US07945806B2
公开(公告)日：2011-05-17
申请号：US11976606
申请日：2007-10-25
申请人： Andrew David Tune , Robin Hotchkiss
发明人： Andrew David Tune , Robin Hotchkiss
IPC分类号： G06F5/06 , G06F13/00 , G06F13/14
CPC分类号： H04L7/00
摘要： A data processing apparatus has initiator circuitry for initiating a transfer of payload data in a first clock cycle, and recipient circuitry for receiving the payload data in a later clock cycle. A communication channel carries the payload data along with associated transfer control information. Timing of receipt of the payload data by the recipient circuitry is controlled by the transfer control information. Timing easing circuitry located within the communication channel temporarily buffers the transfer control information before outputting it to the recipient circuitry. The timing easing circuitry is responsive to a specified timing easing value to determine a time for which the transfer control information is temporarily buffered. The number of clock cycles that elapses between the first clock cycle and the later clock cycle depends on the specified timing easing value. This enables a multi-cycle path to be provided to transfer the payload data.
摘要翻译：数据处理装置具有用于在第一时钟周期内发起有效载荷数据传送的发起者电路以及用于在稍后的时钟周期中接收有效载荷数据的接收电路。通信信道携带有效载荷数据连同关联的传输控制信息。由接收电路接收有效载荷数据的时间由传送控制信息控制。位于通信信道内的定时缓存电路在将其输出到接收电路之前临时缓冲传输控制信息。定时缓动电路响应于指定的定时宽松值来确定传输控制信息被临时缓冲的时间。在第一个时钟周期和较后一个时钟周期之间经过的时钟周期数取决于指定的时钟周期缓动值。这使得能够提供多循环路径来传送有效载荷数据。

4. 发明申请

US20090287978A1 Operating Parameter Control for Integrated Circuit Signal Paths 有权
标题翻译：集成电路信号路径的工作参数控制
公开(公告)号：US20090287978A1
公开(公告)日：2009-11-19
申请号：US12087007
申请日：2006-01-31
申请人： Andrew David Tune , Alistair Crone Bruce , Simon Crossley , Robin Hotchkiss
发明人： Andrew David Tune , Alistair Crone Bruce , Simon Crossley , Robin Hotchkiss
IPC分类号： H03M13/00 , H04L1/00 , G06F11/08
CPC分类号： H04L1/0001 , H04L1/0009 , H04L1/0033
摘要： An integrated circuit (2) includes a signal source (4, 6) and a signal destination (10, 12) linked by a signal path (8). Error correction codes (e.g. Hamming codes) are applied to the signals to be transmitted. Errors detected in the signal transmission are used to control an operating parameter of the signal path, such as signal voltage level, body bias voltage, clock frequency and/or temperature. The control applied is closed-loop feedback control seeking to maintain a finite non-zero predetermined error rate. The technique can also be used between a memory accessing integrated circuit (54) and a separate memory integrated circuit (56). Furthermore, the technique can be used to provide fixed, but differing operating parameters for signal lines within a signal path. Control signals which may be timing critical are passed with appropriate operating parameters, such as a high signal voltage level, where as other signals, such as address and data signals, are passed with a different appropriate operating parameter, such as a low signal voltage level.
摘要翻译：集成电路（2）包括由信号路径（8）链接的信号源（4,6）和信号目的地（10,12）。错误校正码（例如汉明码）被应用于要发送的信号。在信号传输中检测到的错误用于控制信号路径的工作参数，例如信号电压电平，体偏置电压，时钟频率和/或温度。所施加的控制是闭环反馈控制，寻求维持有限的非零预定误差率。该技术还可以在存储器访问集成电路（54）和单独的存储器集成电路（56）之间使用。此外，该技术可用于为信号路径内的信号线提供固定但不同的操作参数。可能具有时序关键性的控制信号通过适当的操作参数（例如高信号电压电平）传递，其中随着诸如地址和数据信号的其它信号通过不同的适当的操作参数，例如低信号电压电平。

5. 发明申请

US20080294929A1 Data processing apparatus and method for controlling a transfer of payload data over a communication channel 有权
标题翻译：用于控制通过通信信道传输有效载荷数据的数据处理装置和方法
公开(公告)号：US20080294929A1
公开(公告)日：2008-11-27
申请号：US11976606
申请日：2007-10-25
申请人： Andrew David Tune , Robin Hotchkiss
发明人： Andrew David Tune , Robin Hotchkiss
IPC分类号： G06F1/10 , G06F1/08
CPC分类号： H04L7/00
摘要： A data processing apparatus and method are provided for controlling a transfer of payload data over a communication channel. The data processing apparatus has initiator circuitry for initiating a transfer of payload data in a first clock cycle, and recipient circuitry for receiving the payload data the subject of the transfer in a later clock cycle. A communication channel is provided over which the payload data is passed from the initiator circuitry to the recipient circuitry along with associated transfer control information, timing of receipt of the payload data by the recipient circuitry being controlled by the transfer control information. Timing easing circuitry located within the communication channel is then used to temporarily buffer at least the transfer control information generated by the initiator circuitry before outputting that transfer control information to the recipient circuitry. The timing easing circuitry is responsive to a specified timing easing value to determine a time for which the transfer control information is temporarily buffered, whereby the number of clock cycles that elapse between the first clock cycle and the later clock cycle is dependent on the specified timing easing value. This hence enables a multi-cycle path to be provided for the transfer of payload data from the initiator circuitry to the recipient circuitry.
摘要翻译：提供了一种用于控制通过通信信道传输有效载荷数据的数据处理装置和方法。数据处理装置具有用于在第一时钟周期内发起有效载荷数据传送的发起者电路，以及接收电路，用于在稍后的时钟周期中接收有效载荷数据传输的对象。提供通信信道，有效载荷数据从发起者电路传送到接收者电路以及相关联的传输控制信息，接收电路接收有效载荷数据的时间由传输控制信息控制。然后，位于通信信道内的定时缓存电路至少暂时缓冲由发起者电路产生的传输控制信息，然后将该传送控制信息输出给接收者电路。定时缓动电路响应于指定的定时缓动值以确定传输控制信息被临时缓冲的时间，从而在第一时钟周期和较晚的时钟周期之间经过的时钟周期的数目取决于指定的时序放松价值因此，可以提供多周期路径来将有效载荷数据从发起者电路传送到接收电路。

6. 发明申请

US20080086572A1 Interconnecting initiator devices and recipient devices 有权
标题翻译：互连发起者设备和收件人设备
公开(公告)号：US20080086572A1
公开(公告)日：2008-04-10
申请号：US11498985
申请日：2006-08-04
申请人： Andrew David Tune , Robin Hotchkiss
发明人： Andrew David Tune , Robin Hotchkiss
IPC分类号： G06F15/173
CPC分类号： H04L45/28 , G06F15/16 , G06F15/17375 , H04L69/14
摘要： An interconnect block for a data processing apparatus, said interconnect block being operable to provide data routes via which one or more initiator devices may access one or more recipient devices, said interconnect block comprising: a first and a second portion; said first portion comprising at least one initiator port for communicating with one of said initiator devices, and at least one recipient port for communicating with one of said recipient devices; said second portion comprising at least two recipient ports for communicating with at least two recipient devices, said second portion being connected to said first portion via at least two parallel connecting routes, said at least two recipient ports being connectable to said at least two parallel connecting routes; wherein in response to a request received from one of said initiator devices at said first portion to perform a transaction accessing one of said at least two recipients in communication with said second portion, said interconnect block is operable to provide a data route between said initiator device and said recipient device via said at least two parallel connecting routes and to maintain said data route for the duration of said transaction.
摘要翻译：一种用于数据处理设备的互连块，所述互连块可操作以提供一个或多个启动器设备经由其访问一个或多个接收器设备的数据路由，所述互连块包括：第一和第二部分; 所述第一部分包括用于与所述发起者设备之一进行通信的至少一个启动器端口以及用于与所述接收设备之一通信的至少一个接收端口; 所述第二部分包括用于与至少两个接收装置通信的至少两个接收端口，所述第二部分经由至少两个并行连接路径连接到所述第一部分，所述至少两个接收端口可连接到所述至少两个并联连接路线其中响应于从所述第一部分的所述发起者设备之一接收的请求，以执行与所述第二部分通信的所述至少两个接收者之一的事务，所述互连块可操作以提供所述启动器设备之间的数据路由并且经由所述至少两个并行连接路由表示所述接收方设备，并且在所述事务持续期间保持所述数据路由。

7. 发明授权

US08151126B2 Controlling power consumption in a data processing apparatus 有权
标题翻译：控制数据处理装置的功耗
公开(公告)号：US08151126B2
公开(公告)日：2012-04-03
申请号：US12308888
申请日：2006-06-29
申请人： Alistair Crone Bruce , Robin Hotchkiss , Louisa Jayne McElwee
发明人： Alistair Crone Bruce , Robin Hotchkiss , Louisa Jayne McElwee
IPC分类号： G06F1/26
CPC分类号： G06F1/3203 , G06F1/32 , G06F1/3253 , G06F1/3287 , Y02D10/151 , Y02D10/171 , Y02D50/20
摘要： A data processing apparatus, bus logic and method are provided for controlling power consumption within a data processing apparatus. The data processing apparatus has a plurality of logic elements, at least one of the logic elements being an initiator logic element for initiating transfers, and at least one of the logic elements being a recipient logic element for receiving transfers. A communication path is provided between an initiator logic element and a recipient logic element to enable payload data the subject of a transfer to be passed from the initiator logic element to the recipient logic element. The communication path has at least one buffer circuit provided therein for propagating at least the payload data along the communication path. Further, a power control circuit is associated with the at least one buffer circuit, which is responsive to a control signal indicating whether the payload data on the communication path is valid. If the control signal indicates that the payload data is not valid, the power control circuit causes the associated at least one buffer circuit to enter a power saving state. The control signal is derived from at least one pre-existing signal associated with the transfer. This has been found to provide a particularly efficient and flexible technique for reducing leakage current in buffer circuits within the data processing apparatus.
摘要翻译：提供数据处理装置，总线逻辑和方法来控制数据处理装置内的功耗。所述数据处理装置具有多个逻辑元件，所述逻辑元件中的至少一个是用于启动传输的启动器逻辑元件，并且所述逻辑元件中的至少一个是用于接收传输的接收者逻辑元件。在启动器逻辑元件和接收者逻辑元件之间提供通信路径，以使传输对象的负载数据能够从启动器逻辑元件传递到接收者逻辑元件。通信路径具有至少一个缓冲电路，用于至少沿着通信路径传播有效载荷数据。此外，功率控制电路与至少一个缓冲电路相关联，该缓冲电路响应于指示通信路径上的有效载荷数据是否有效的控制信号。如果控制信号指示有效载荷数据无效，则功率控制电路使相关联的至少一个缓冲电路进入省电状态。控制信号是从与传送相关联的至少一个预先存在的信号导出的。已经发现，这提供了一种用于减少数据处理装置内的缓冲器电路中的泄漏电流的特别有效和灵活的技术。

8. 发明申请

US20090300382A1 Controlling Power Consumption in a Data Processing Apparatus 有权
标题翻译：控制数据处理设备的功耗
公开(公告)号：US20090300382A1
公开(公告)日：2009-12-03
申请号：US12308888
申请日：2006-06-29
申请人： Alistair Crone Bruce , Robin Hotchkiss , Louisa Jayne McElwee
发明人： Alistair Crone Bruce , Robin Hotchkiss , Louisa Jayne McElwee
IPC分类号： G06F1/32
CPC分类号： G06F1/3203 , G06F1/32 , G06F1/3253 , G06F1/3287 , Y02D10/151 , Y02D10/171 , Y02D50/20
摘要： A data processing apparatus, bus logic and method are provided for controlling power consumption within a data processing apparatus. The data processing apparatus has a plurality of logic elements, at least one of the logic elements being an initiator logic element for initiating transfers, and at least one of the logic elements being a recipient logic element for receiving transfers. A communication path is provided between an initiator logic element and a recipient logic element to enable payload data the subject of a transfer to be passed from the initiator logic element to the recipient logic element. The communication path has at least one buffer circuit provided therein for propagating at least the payload data along the communication path. Further, a power control circuit is associated with the at least one buffer circuit, which is responsive to a control signal indicating whether the payload data on the communication path is valid. If the control signal indicates that the payload data is not valid, the power control circuit causes the associated at least one buffer circuit to enter a power saving state. The control signal is derived from at least one pre-existing signal associated with the transfer. This has been found to provide a particularly efficient and flexible technique for reducing leakage current in buffer circuits within the data processing apparatus.
摘要翻译：提供数据处理装置，总线逻辑和方法来控制数据处理装置内的功耗。所述数据处理装置具有多个逻辑元件，所述逻辑元件中的至少一个是用于启动传输的启动器逻辑元件，并且所述逻辑元件中的至少一个是用于接收传输的接收者逻辑元件。在启动器逻辑元件和接收者逻辑元件之间提供通信路径，以使传输对象的负载数据能够从启动器逻辑元件传递到接收者逻辑元件。通信路径具有至少一个缓冲电路，用于至少沿着通信路径传播有效载荷数据。此外，功率控制电路与至少一个缓冲电路相关联，该缓冲电路响应于指示通信路径上的有效载荷数据是否有效的控制信号。如果控制信号指示有效载荷数据无效，则功率控制电路使相关联的至少一个缓冲电路进入省电状态。控制信号是从与传送相关联的至少一个预先存在的信号导出的。已经发现，这提供了一种用于减少数据处理装置内的缓冲器电路中的泄漏电流的特别有效和灵活的技术。

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