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1. 发明申请

US20070298599A1 Method for fabricating multiple FETs of different types 有权
标题翻译：制造不同类型多个FET的方法
公开(公告)号：US20070298599A1
公开(公告)日：2007-12-27
申请号：US11804875
申请日：2007-05-21
申请人： Se-Myeong Jang , Makoto Yoshida , Jae-Rok Kahng , Chul Lee , Keun-Nam Kim , Hyun-Ju Sung , Hui-Jung Kim , Kyoung-Ho Jung
发明人： Se-Myeong Jang , Makoto Yoshida , Jae-Rok Kahng , Chul Lee , Keun-Nam Kim , Hyun-Ju Sung , Hui-Jung Kim , Kyoung-Ho Jung
IPC分类号： H01L21/8232
CPC分类号： H01L21/823412
摘要： For fabricating multiple field effect transistors (FETs), a first conductive layer is deposited over first and second active regions of a semiconductor substrate. The first conductive layer is patterned over the second active region to form mold structures. Mask structures are formed between the mold structures. The second active region is patterned using the mask structures or using spacers formed at sidewalls of the mold structures to form multiple fins of a field effect transistor of a fin type. The first conductive layer is patterned over the first active region to form a gate of another field effect transistor of a different type.
摘要翻译：为了制造多个场效应晶体管（FET），第一导电层沉积在半导体衬底的第一和第二有源区上。在第二有源区上形成第一导电层以形成模具结构。在模具结构之间形成掩模结构。使用掩模结构或使用形成在模具结构的侧壁处的间隔来形成第二有源区，以形成翅片型场效应晶体管的多个鳍。在第一有源区上图案化第一导电层以形成不同类型的另一场效应晶体管的栅极。

2. 发明授权

US06458653B1 Method for forming lower electrode of cylinder-shaped capacitor preventing twin bit failure 失效
标题翻译：用于形成圆柱形电容器的下电极的方法，其防止双位故障
公开(公告)号：US06458653B1
公开(公告)日：2002-10-01
申请号：US10040866
申请日：2001-12-27
申请人： Se-Myeong Jang
发明人： Se-Myeong Jang
IPC分类号： H01L218242
CPC分类号： H01L28/91 , H01L21/76804
摘要： A method for forming a lower electrode of a cylinder-shaped capacitor is provided to prevent etch skew and twin bit failure. The method includes sequentially forming a buffer layer and an etch stopper on a semiconductor substrate including a conductive region, forming a sacrificial dielectric layer on the etch stopper, forming a first opening within the sacrificial dielectric layer by etching a portion of the sacrificial dielectric layer using the etch stopper, depositing a slope-improving layer for improving sidewall slope of the first opening, forming a second opening by etching a portion of the slope-improving layer, the etch stopper and the buffer layer under the first opening and exposing the conductive region to which the cylinder-shaped capacitor is electrically connected, depositing a conductive layer for forming cylinder-shaped lower electrodes on a surface of the second opening, and forming the cylinder-shaped lower electrodes separated from each other.
摘要翻译：提供一种用于形成圆柱形电容器的下电极的方法，以防止蚀刻偏斜和双位故障。该方法包括在包括导电区域的半导体衬底上顺序地形成缓冲层和蚀刻停止层，在蚀刻停止层上形成牺牲介电层，通过用牺牲介电层中的一部分蚀刻牺牲介电层的一部分，蚀刻停止器，沉积用于改善第一开口的侧壁倾斜度的斜坡改进层，通过蚀刻斜面改善层的一部分，蚀刻停止层和第一开口下方的缓冲层形成第二开口，并使导电区域所述圆筒形电容器电连接到所述第一开口，在所述第二开口的表面上沉积用于形成圆柱形下电极的导电层，并且形成彼此分离的所述圆筒形下电极。

3. 发明授权

US08497175B2 Method of fabricating FinFET devices 有权
标题翻译： FinFET器件的制造方法
公开(公告)号：US08497175B2
公开(公告)日：2013-07-30
申请号：US12766055
申请日：2010-04-23
申请人： Jae-Rok Kahng , Makoto Yoshida , Se-Myeong Jang
发明人： Jae-Rok Kahng , Makoto Yoshida , Se-Myeong Jang
IPC分类号： H01L21/8234
CPC分类号： H01L29/7851 , H01L29/42384 , H01L29/66795
摘要： A semiconductor device is fabricating using a photoresist mask pattern, and selectively removing portions of a liner nitride layer in a cell region and a peripheral circuit region. A modified FinFET is formed to reduce the influence of signals transmitted by adjacent gate lines in a cell region. A double FinFET and a substantially planar MOSFET are formed in a core region and in a peripheral region, respectively, concurrently with the formation of the modified FinFET.
摘要翻译：使用光致抗蚀剂掩模图案制造半导体器件，并且选择性地去除单元区域和外围电路区域中的衬里氮化物层的部分。形成改进的FinFET以减小由相邻栅极线在单元区域中传输的信号的影响。在形成改进的FinFET的同时，在芯区域和周边区域分别形成双FinFET和基本上平面的MOSFET。

4. 发明授权

US07952140B2 Methods of fabricating semiconductor devices having multiple channel transistors and semiconductor devices fabricated thereby 有权
标题翻译：制造具有多个沟道晶体管和由此制造的半导体器件的半导体器件的方法
公开(公告)号：US07952140B2
公开(公告)日：2011-05-31
申请号：US12705011
申请日：2010-02-12
申请人： Se-Myeong Jang , Makoto Yoshida , Jae-Rok Kahng , Hyun-Ju Sung , Hui-Jung Kim , Chang-Hoon Jeon
发明人： Se-Myeong Jang , Makoto Yoshida , Jae-Rok Kahng , Hyun-Ju Sung , Hui-Jung Kim , Chang-Hoon Jeon
IPC分类号： H01L29/66
CPC分类号： H01L27/105 , H01L21/823412 , H01L21/823437 , H01L21/823481 , H01L27/1052
摘要： In methods of fabricating a semiconductor device having multiple channel transistors and semiconductor devices fabricated thereby, the semiconductor device includes an isolation region disposed within a semiconductor substrate and defining a first region. A plurality of semiconductor pillars self-aligned with the first region and spaced apart from each other are disposed within the first region, and each of the semiconductor pillars has at least one recessed region therein. At least one gate structure may be disposed across the recessed regions, which crosses the semiconductor pillars and extends onto the isolation region.
摘要翻译：在制造具有多个沟道晶体管和由此制造的半导体器件的半导体器件的方法中，半导体器件包括设置在半导体衬底内并限定第一区域的隔离区域。与第一区域自对准并且彼此间隔开的多个半导体柱设置在第一区域内，并且每个半导体柱在其中具有至少一个凹陷区域。至少一个栅极结构可以设置在穿过半导体柱并且延伸到隔离区上的凹陷区域之间。

5. 发明授权

US07700445B2 Method for fabricating multiple FETs of different types 有权
标题翻译：制造不同类型多个FET的方法
公开(公告)号：US07700445B2
公开(公告)日：2010-04-20
申请号：US11804875
申请日：2007-05-21
申请人： Se-Myeong Jang , Makoto Yoshida , Jae-Rok Kahng , Chul Lee , Keun-Nam Kim , Hyun-Ju Sung , Hui-Jung Kim , Kyoung-Ho Jung
发明人： Se-Myeong Jang , Makoto Yoshida , Jae-Rok Kahng , Chul Lee , Keun-Nam Kim , Hyun-Ju Sung , Hui-Jung Kim , Kyoung-Ho Jung
IPC分类号： H01L21/336
CPC分类号： H01L21/823412
摘要： For fabricating multiple field effect transistors (FETs), a first conductive layer is deposited over first and second active regions of a semiconductor substrate. The first conductive layer is patterned over the second active region to form mold structures. Mask structures are formed between the mold structures. The second active region is patterned using the mask structures or using spacers formed at sidewalls of the mold structures to form multiple fins of a field effect transistor of a fin type. The first conductive layer is patterned over the first active region to form a gate of another field effect transistor of a different type.
摘要翻译：为了制造多个场效应晶体管（FET），第一导电层沉积在半导体衬底的第一和第二有源区上。在第二有源区上形成第一导电层以形成模具结构。在模具结构之间形成掩模结构。使用掩模结构或使用形成在模具结构的侧壁处的间隔来形成第二有源区，以形成翅片型场效应晶体管的多个鳍。在第一有源区上图案化第一导电层以形成不同类型的另一场效应晶体管的栅极。

6. 发明授权

US07223649B2 Method of fabricating transistor of DRAM semiconductor device 有权
标题翻译：制造DRAM半导体器件晶体管的方法
公开(公告)号：US07223649B2
公开(公告)日：2007-05-29
申请号：US10922055
申请日：2004-08-18
申请人： Yong-Chul Oh , Wook-Je Kim , Nak-Jin Son , Se-Myeong Jang , Gyo-Young Jin
发明人： Yong-Chul Oh , Wook-Je Kim , Nak-Jin Son , Se-Myeong Jang , Gyo-Young Jin
IPC分类号： H01L21/336 , H01L21/8238 , H01L21/8242
CPC分类号： H01L21/823878 , H01L21/28185 , H01L21/28202 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L27/10873 , H01L27/10894 , H01L29/513 , H01L29/518
摘要： Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a gate insulation layer including a silicon oxide layer and a silicon oxide nitride layer on the semiconductor substrate. Also, the embodiments can include forming a polysilicon layer containing an N-type impurity on the gate insulation layer, and forming a gate electrode by selectively ion-implanting a P-type impurity into the polysilicon layer formed in a PMOS transistor region of the circuit region. The embodiments further include forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and forming a gate stack in a gate region.
摘要翻译：实施例防止或基本上减少P型杂质扩散到具有双栅极的PMOS晶体管中的沟道区域中。一些实施例包括在半导体衬底上形成器件隔离膜，在半导体衬底的有源区中形成沟道杂质区，并在半导体衬底上形成包括氧化硅层和氧化硅氮化物层的栅极绝缘层。此外，实施例可以包括在栅极绝缘层上形成含有N型杂质的多晶硅层，并且通过选择性地将P型杂质离子注入形成在电路的PMOS晶体管区域中的多晶硅层中来形成栅电极地区。实施例还包括在栅电极上形成导电金属层和栅极上绝缘层，以及在栅极区域中形成栅叠层。

7. 发明授权

US09570510B2 Magnetoresistive random access memory devices and methods of manufacturing the same 有权
标题翻译：磁阻随机存取存储器件及其制造方法
公开(公告)号：US09570510B2
公开(公告)日：2017-02-14
申请号：US14724725
申请日：2015-05-28
申请人： Eun-Jung Kim , Se-Myeong Jang , Dae-Ik Kim , Je-Min Park , Yoo-Sang Hwang
发明人： Eun-Jung Kim , Se-Myeong Jang , Dae-Ik Kim , Je-Min Park , Yoo-Sang Hwang
IPC分类号： H01L29/82 , H01L27/22 , H01L29/78 , H01L43/08
CPC分类号： H01L27/228 , H01L29/7827 , H01L43/08
摘要： An MRAM device may include semiconductor structures, a common source region, a drain region, a channel region, gate structures, word line structures, MTJ structures, and bit line structures arranged on a substrate. Each of the semiconductor structures may include a first semiconductor pattern having a substantially linear shape extending in a first direction that is substantially parallel to a top surface of the substrate, and a plurality of second patterns that each extend in a third direction substantially perpendicular to the top surface of the substrate. A common source region and drain region may be formed in each of the semiconductor structures to be spaced apart from each other in the third direction, and the channel region may be arranged between the common source region and the drain region. Gate structures may be formed between adjacent second semiconductor patterns in the second direction. Word line structures may electrically connect gate structures arranged in the first direction to each other. MTJ structures may be electrically connected to corresponding ones of the second semiconductor patterns. Each bit line structure may electrically connect two adjacent MTJ structures in the first direction to each other.
摘要翻译： MRAM器件可以包括布置在衬底上的半导体结构，公共源极区，漏极区，沟道区，栅极结构，字线结构，MTJ结构和位线结构。每个半导体结构可以包括具有基本上线性形状的第一半导体图案，该第一半导体图案沿着基本上平行于基板的顶表面的第一方向延伸，以及多个第二图案，每个第二图案沿基本上垂直于基板的第三方向延伸衬底的顶表面。可以在每个半导体结构中形成公共源极区域和漏极区域，以在第三方向上彼此间隔开，并且沟道区域可以布置在公共源极区域和漏极区域之间。可以在相邻的第二半导体图案之间沿第二方向形成栅极结构。字线结构可以将布置在第一方向上的栅极结构彼此电连接。 MTJ结构可以电连接到相应的第二半导体图案。每个位线结构可以将第一方向上的两个相邻的MTJ结构彼此电连接。

8. 发明授权

US07501668B2 Semiconductor memory devices having contact pads with silicide caps thereon 有权
标题翻译：具有其上具有硅化物帽的接触垫的半导体存储器件
公开(公告)号：US07501668B2
公开(公告)日：2009-03-10
申请号：US11582926
申请日：2006-10-18
申请人： Se-Myeong Jang , Yong-chul Oh , Gyo-young Jin
发明人： Se-Myeong Jang , Yong-chul Oh , Gyo-young Jin
IPC分类号： H01L27/088 , H01L29/78
CPC分类号： H01L27/10855 , H01L21/76885 , H01L21/76889 , H01L21/76897 , H01L23/485 , H01L27/105 , H01L27/10817 , H01L27/10888 , H01L27/10894 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device having a semiconductor substrate includes a gate structure on the semiconductor substrate. Source/drain regions are on opposite sides of the gate structure. A contact pad is on at least one of the source/drain region, and a silicide cap is on a surface of the contact pad opposite the respective source/drain region.
摘要翻译：具有半导体衬底的集成电路器件包括半导体衬底上的栅极结构。源极/漏极区位于栅极结构的相对侧。接触焊盘位于源极/漏极区域中的至少一个上，并且硅化物帽位于与相应源极/漏极区域相对的接触焊盘的表面上。

9. 发明申请

US20070037375A1 Semiconductor memory devices having contact pads with silicide caps thereon 有权
标题翻译：具有其上具有硅化物帽的接触垫的半导体存储器件
公开(公告)号：US20070037375A1
公开(公告)日：2007-02-15
申请号：US11582926
申请日：2006-10-18
申请人： Se-Myeong Jang , Yong-chul Oh , Gyo-young Jin
发明人： Se-Myeong Jang , Yong-chul Oh , Gyo-young Jin
IPC分类号： H01L21/44
CPC分类号： H01L27/10855 , H01L21/76885 , H01L21/76889 , H01L21/76897 , H01L23/485 , H01L27/105 , H01L27/10817 , H01L27/10888 , H01L27/10894 , H01L27/10897 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit device having a semiconductor substrate includes a gate structure on the semiconductor substrate. Source/drain regions are on opposite sides of the gate structure. A contact pad is on at least one of the source/drain region, and a silicide cap is on a surface of the contact pad opposite the respective source/drain region.
摘要翻译：具有半导体衬底的集成电路器件包括半导体衬底上的栅极结构。源极/漏极区位于栅极结构的相对侧。接触焊盘位于源极/漏极区域中的至少一个上，并且硅化物帽位于与相应源极/漏极区域相对的接触焊盘的表面上。

10. 发明申请

US20050042832A1 Method of fabricating transistor of DRAM semiconductor device 有权
标题翻译：制造DRAM半导体器件晶体管的方法
公开(公告)号：US20050042832A1
公开(公告)日：2005-02-24
申请号：US10922055
申请日：2004-08-18
申请人： Yong-Chul Oh , Wook-Je Kim , Nak-Jin Son , Se-Myeong Jang , Gyo-Young Jin
发明人： Yong-Chul Oh , Wook-Je Kim , Nak-Jin Son , Se-Myeong Jang , Gyo-Young Jin
IPC分类号： H01L29/78 , H01L21/28 , H01L21/8238 , H01L21/8242 , H01L29/51 , H01L21/3205 , H01L29/76 , H01L31/062
CPC分类号： H01L21/823878 , H01L21/28185 , H01L21/28202 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L27/10873 , H01L27/10894 , H01L29/513 , H01L29/518
摘要： Embodiments prevent or substantially reduce diffusion of a P-type impurity into a channel region in a PMOS transistor having a dual gate. Some embodiments include forming a device isolation film on a semiconductor substrate, forming a channel impurity region in an active region of the semiconductor substrate, and forming a gate insulation layer including a silicon oxide layer and a silicon oxide nitride layer on the semiconductor substrate. Also, the embodiments can include forming a polysilicon layer containing an N-type impurity on the gate insulation layer, and forming a gate electrode by selectively ion-implanting a P-type impurity into the polysilicon layer formed in a PMOS transistor region of the circuit region. The embodiments further include forming a conductive metal layer and a gate upper insulation layer on the gate electrode, and forming a gate stack in a gate region.
摘要翻译：实施例防止或基本上减少P型杂质扩散到具有双栅极的PMOS晶体管中的沟道区域中。一些实施例包括在半导体衬底上形成器件隔离膜，在半导体衬底的有源区中形成沟道杂质区，并在半导体衬底上形成包括氧化硅层和氧化硅氮化物层的栅极绝缘层。此外，实施例可以包括在栅极绝缘层上形成含有N型杂质的多晶硅层，并且通过选择性地将P型杂质离子注入形成在电路的PMOS晶体管区域中的多晶硅层中来形成栅电极地区。实施例还包括在栅电极上形成导电金属层和栅极上绝缘层，以及在栅极区域中形成栅叠层。

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