专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US5031072A Baseboard for orthogonal chip mount 失效
标题翻译：底板用于正交芯片安装
公开(公告)号：US5031072A
公开(公告)日：1991-07-09
申请号：US472698
申请日：1990-01-31
申请人： Satwinder S. Malhi , Kenneth E. Bean
发明人： Satwinder S. Malhi , Kenneth E. Bean
IPC分类号： H01L23/13 , H01L23/14 , H01L23/538 , H01L25/065
CPC分类号： H01L23/13 , H01L23/147 , H01L23/538 , H01L25/0657 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06589 , H01L2924/0002
摘要： A baseboard for orthogonal mounting of integrated circuit chips thereto is described. Plural channels (14) are anisotropically etched in a silicon baseboard (10). A corresponding plurality of integrated circuit chips (12) are inserted into the channels (14). A number of baseboard contact pads (18) are formed adjacent each channel (14), and are solder bonded to corresponding chip conductor pads (16). Interconnect conductors (20, 28) provide connection of each baseboard pad (18) either to other chips (12) or to connector pads (22) located adjacent an edge (26) of the baseboard chip mount (10). A coating (30) of silicon carbide over the surface of the baseboard chip mount (10) improves the thermal efficiency of the assembly.
摘要翻译：描述了用于将集成电路芯片正交安装的基板。在硅基板（10）中各向异性地蚀刻多个通道（14）。相应的多个集成电路芯片（12）插入通道（14）中。在每个通道（14）附近形成有多个基板接触焊盘（18），并焊接到相应的芯片导体焊盘（16）上。互连导体（20,28）提供每个基板焊盘（18）与其它芯片（12）或邻近基板芯片安装架（10）的边缘（26）定位的连接器焊盘（22）的连接。在基板芯片安装件（10）的表面上的碳化硅涂层（30）提高了组件的热效率。

2. 发明授权

US4922378A Baseboard for orthogonal chip mount 失效
标题翻译：底板用于正交芯片安装
公开(公告)号：US4922378A
公开(公告)日：1990-05-01
申请号：US893770
申请日：1986-08-01
申请人： Satwinder S. Malhi , Kenneth E. Bean
发明人： Satwinder S. Malhi , Kenneth E. Bean
IPC分类号： H01L23/13 , H01L23/14 , H01L23/538 , H01L25/065
CPC分类号： H01L25/0657 , H01L23/13 , H01L23/147 , H01L23/538 , H01L2225/06527 , H01L2225/06551 , H01L2225/06555 , H01L2225/06589 , H01L2924/0002
摘要： A baseboard for orthogonal mounting of integrated circuit chips is described. Plural channels (14) are anisotropically etched in a silicon baseboard (10). A corresponding plurality of integrated circuit chips (12) are inserted into the channels (14). A number of baseboard contact pads (18) are formed adjacent each channel (14), and are solder bonded to corresponding chip conductor pads (16). Interconnect conductors (20, 28) provide connection of each baseboard pad (18) either to other chips (12) or to connector pads (22) located adjacent an edge (26) of the baseboard chip mount (10). A coating (30) of silicon carbide over the surface of the baseboard chip mount (10) improves the thermal efficiency of the assembly.
摘要翻译：描述了用于集成电路芯片的正交安装的基板。在硅基板（10）中各向异性地蚀刻多个通道（14）。相应的多个集成电路芯片（12）插入通道（14）中。在每个通道（14）附近形成有多个基板接触焊盘（18），并焊接到相应的芯片导体焊盘（16）上。互连导体（20,28）提供每个基板焊盘（18）与其它芯片（12）或邻近基板芯片安装架（10）的边缘（26）定位的连接器焊盘（22）的连接。在基板芯片安装件（10）的表面上的碳化硅涂层（30）提高了组件的热效率。

3. 发明授权

US5250445A Discretionary gettering of semiconductor circuits 失效
标题翻译：半导体电路的任意吸气
公开(公告)号：US5250445A
公开(公告)日：1993-10-05
申请号：US824770
申请日：1992-01-17
申请人： Kenneth E. Bean , Satwinder S. Malhi , Walter R. Runyan
发明人： Kenneth E. Bean , Satwinder S. Malhi , Walter R. Runyan
IPC分类号： H01L21/322 , H01L21/205
CPC分类号： H01L21/3221
摘要： A semiconductor wafer (32) is patterned to have gettering areas (36-38) selectively positioned proximate devices (44-46) which require gettering. The areas (36-38) comprise germanium-doped silicon having a germanium concentration of approximately 1.5%-2.0%. The germanium creates a lattice mismatch between the substrate (32) and an epitaxial layer (34) which is sufficient to produce defects capable of gettering contaminants. The gettering areas (36-38) may be formed by selective deposition, selective etching, ion-implantation or selective diffusion techniques.
摘要翻译：将半导体晶片（32）图案化成具有选择性地定位在需要吸杂的器件（44-46）附近的吸气区域（36-38）。区域（36-38）包括锗浓度约为1.5％-2.0％的锗掺杂硅。锗在衬底（32）和外延层（34）之间产生足以产生能够吸收污染物的缺陷的晶格失配。吸气区（36-38）可以通过选择性沉积，选择性蚀刻，离子注入或选择性扩散技术形成。

4. 发明授权

US4791463A Structure for contacting devices in three dimensional circuitry 失效
标题翻译：用于在三维电路中接触设备的结构
公开(公告)号：US4791463A
公开(公告)日：1988-12-13
申请号：US801037
申请日：1985-11-22
申请人： Satwinder S. Malhi
发明人： Satwinder S. Malhi
IPC分类号： H01L21/225 , H01L21/8242 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10864 , H01L21/2257 , H01L27/10841
摘要： The present invention is described in conjunction with the fabrication of a dRAM cell which an important application of the present invention. The described cell provides a one-transistor/one-capacitor dRAM cell structure and array in which the cell transistor is formed on the sidewalls of a substrate trench containing the cell capacitor; the word and bit lines cross over this trench. This stacking of the transistor on top of the capacitor yields a cell with minimal area on the substrate and solves a problem of dense packing of cells. One capacitor plate and the transistor channel and source region are formed in the bulk sidewall of the trench and the transistor gate and the other plate of the capacitor are both formed in polysilicon in the trench but separated from each other by an oxide layer inside the trench. The signal charge is stored on the polysilicon capacitor plate by an electrical connection of the source region with the polysilicon capacitor plate. The described embodiment provides an electrical connection which allows separate connection to the capacitor.
摘要翻译：结合本发明的重要应用的dRAM单元的制造来描述本发明。所描述的单元提供单晶体管/单电容器dRAM单元结构和阵列，其中单元晶体管形成在包含单元电容器的基板沟槽的侧壁上; 字和位线跨过这个沟槽。晶体管在电容器顶部的堆叠产生在衬底上具有最小面积的电池，并解决了电池致密堆积的问题。一个电容器板和晶体管沟道和源极区域形成在沟槽的体侧壁中，并且晶体管栅极和电容器的另一个板都形成在沟槽中的多晶硅中，但是通过沟槽内的氧化物层彼此分离。信号电荷通过源极区域与多晶硅电容器板的电连接而存储在多晶硅电容器板上。所描述的实施例提供允许分离连接到电容器的电连接。

5. 发明授权

US5293053A Elevated CMOS 失效
标题翻译：高架CMOS
公开(公告)号：US5293053A
公开(公告)日：1994-03-08
申请号：US655500
申请日：1991-05-01
申请人： Satwinder S. Malhi , Ravishankar Sundaresan , Shivaling S. Mahant-Shetti
发明人： Satwinder S. Malhi , Ravishankar Sundaresan , Shivaling S. Mahant-Shetti
IPC分类号： H01L21/8238 , H01L21/8234 , H01L27/06 , H01L27/08 , H01L27/088 , H01L27/092 , H01L29/78 , H01L27/02 , H01L27/01 , H01L29/06
CPC分类号： H01L27/0688 , H01L21/823885 , H01L27/092 , H01L29/7827
摘要： A new class of CMOS integrated circuits, wherein the PMOS and NMOS devices are both configured as vertical transistors. One trench can contain a PMOS device, an NMOS device, and a gate which is coupled to control both the PMOS device and the NMOS device. Latchup problems do not arise, and n+ to p+ spacing rules are not required.
摘要翻译：一类新的CMOS集成电路，其中PMOS和NMOS器件均被配置为垂直晶体管。一个沟槽可以包含PMOS器件，NMOS器件和耦合以控制PMOS器件和NMOS器件的栅极。 Latchup问题不会出现，并且不需要n +到p +间隔规则。

6. 发明授权

US4829017A Method for lubricating a high capacity dram cell 失效
标题翻译：润滑高容量电池的方法
公开(公告)号：US4829017A
公开(公告)日：1989-05-09
申请号：US912030
申请日：1986-09-25
申请人： Satwinder S. Malhi
发明人： Satwinder S. Malhi
IPC分类号： H01L27/10 , H01L21/8242 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10864 , H01L27/10841
摘要： A dynamic random access memory cell (14) is disclosed which is characterized by a high capacity storage element and small lateral wafer area. The cell (14) is constructed with a word line (40) overlying a split bit line (48, 50), with an underlying transistor 30, and yet thereunder a high capacitance capacitor (34). The word line (40) includes a member (42) isolated from the bit line (36) and formed therethrough to provide the transistor gate conductor. The transistor gate insulator (44) covers the gate conductor (42), and is encircled by a transistor semiconductor region (46) forming a vertical transistor conduction channel. The split bit line elements (48, 50) are in electrical contact with an underlying transistor drain region (126). The transistor conduction channel (46) is also in contact with an underlying transistor source region forming one plate (52) of the capacitor (34). The capacitor plate (52) is a core which is enclosed annularly by dielectric isolation (54). Another semiconductor capacitor plate (56) encircles the dielectric isolation (54).
摘要翻译：公开了一种动态随机存取存储器单元（14），其特征在于高容量存储元件和小的横向晶片面积。单元（14）由覆盖分割位线（48,50）的字线（40）构成，具有下面的晶体管30，而在高容量电容器（34）之下。字线（40）包括与位线（36）隔离并形成在其中以提供晶体管栅极导体的构件（42）。晶体管栅极绝缘体（44）覆盖栅极导体（42），并被形成垂直晶体管导通沟道的晶体管半导体区域（46）包围。分开的位线元件（48,50）与底层晶体管漏极区（126）电接触。晶体管传导通道（46）也与形成电容器（34）的一个板（52）的底层晶体管源区接触。电容器板（52）是通过电介质隔离（54）环形封闭的芯。另一个半导体电容器板（56）围绕绝缘隔离（54）。

7. 发明授权

US4797373A Method of making dRAM cell with trench capacitor 失效
标题翻译：制造具有沟槽电容器的dRAM单元的方法
公开(公告)号：US4797373A
公开(公告)日：1989-01-10
申请号：US122560
申请日：1987-11-12
申请人： Satwinder S. Malhi , Gordon P. Pollack
发明人： Satwinder S. Malhi , Gordon P. Pollack
IPC分类号： H01L21/225 , H01L21/8242 , H01L27/108 , H01L27/10 , H01L21/302
CPC分类号： H01L27/10864 , H01L21/2257 , H01L27/10841
摘要： A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one storage capacitor with both the transistor and the capacitor formed in a trench in a substrate. The transistor source, channel and drain and one capacitor plate are formed essentially vertically in the bulk substrate sidewalls of the trench, and the gate and other capacitor plate are formed in two regions of material inserted into the trench and isolated from the bulk by an insulating layer. Signal charge is stored on the capacitor material inserted into the trench by an electrical connection of the bulk substrate source to the capacitor material through the insulating layer. In preferred embodiments word lines on the substrate surface connect to the upper of the inserted regions which forms the gate, and bit lines on the substrate surface form the drains. The trenches and cells are formed at the crossings of bit lines and word lines; the bit lines and the word lines form perpendicular sets of parallel lines.
摘要翻译：公开了一种dRAM单元和单元阵列及其制造方法，其中单元包括一个场效应晶体管和一个存储电容器，晶体管和电容器都形成在衬底中的沟槽中。晶体管源极，沟道和漏极以及一个电容器板基本垂直地形成在沟槽的主体衬底侧壁中，并且栅极和其它电容器板形成在插入到沟槽中的两个材料区域中，并且通过绝缘体与本体隔离层。信号电荷通过绝缘层通过体衬底源与电容器材料的电连接而被存储在插入到沟槽中的电容器材料上。在优选实施例中，衬底表面上的字线连接到形成栅极的插入区域的上部，衬底表面上的位线形成漏极。在位线和字线的交叉处形成沟槽和电池; 位线和字线形成垂直的平行线组。

8. 发明授权

US5072276A Elevated CMOS 失效
标题翻译：高架CMOS
公开(公告)号：US5072276A
公开(公告)日：1991-12-10
申请号：US622254
申请日：1990-12-04
申请人： Satwinder S. Malhi , Ravishankar Sundaresan , Shivaling S. Mahant-Shetti
发明人： Satwinder S. Malhi , Ravishankar Sundaresan , Shivaling S. Mahant-Shetti
IPC分类号： H01L27/06 , H01L27/092 , H01L29/78
CPC分类号： H01L27/092 , H01L21/823885 , H01L27/0688 , H01L29/7827
摘要： A new class of CMOS integrated circuits, wherein the PMOS and NMOS devices are both configured as vertical transistors. One trench can contain a PMOS device, an NMOS device, and a gate which is coupled to control both the PMOS device and the NMOS device. Latchup problems do not arise, and n+ to p+ spacing rules are not required.
摘要翻译：一类新的CMOS集成电路，其中PMOS和NMOS器件均被配置为垂直晶体管。一个沟槽可以包含PMOS器件，NMOS器件和耦合以控制PMOS器件和NMOS器件的栅极。 Latchup问题不会出现，并且不需要n +到p +间隔规则。

9. 发明授权

US4890145A dRAM cell and array 失效
标题翻译： dRAM单元格和数组
公开(公告)号：US4890145A
公开(公告)日：1989-12-26
申请号：US316587
申请日：1989-02-27
申请人： Satwinder S. Malhi
发明人： Satwinder S. Malhi
IPC分类号： H01L27/108
CPC分类号： H01L27/10841
摘要： A dRAM cell and array of cells, together with a method of fabrication, are disclosed wherein the cell includes one field effect transistor and one capacitor with both the transistor and the capacitor formed in a trench in a substrate. One capacitor plate and the transistor source are common and are formed in the lower portion of the trench sidewall. The transistor drain is formed in the upper portion of the trench sidewall to connect to a bit line on the substrate surface, and the channel is the vertical portion of the trench sidewall between the source and drain. The transistor gate fills the upper portion of the trench, and a heavily doped other plate of the capacitor fills the lower portion of the trench and makes contact with the substrate through the bottom of the trench.
摘要翻译：公开了一种dRAM单元和单元阵列，其中制造方法，其中该单元包括一个场效应晶体管和一个电容器，两个晶体管和电容器都形成在衬底中的沟槽中。一个电容器板和晶体管源是共同的，并且形成在沟槽侧壁的下部。晶体管漏极形成在沟槽侧壁的上部，以连接到衬底表面上的位线，并且沟道是源极和漏极之间的沟槽侧壁的垂直部分。晶体管栅极填充沟槽的上部，并且电容器的重掺杂的其他板填充沟槽的下部并且通过沟槽的底部与衬底接触。

10. 发明授权

US4754314A Split-level CMOS 失效
标题翻译：分体式CMOS
公开(公告)号：US4754314A
公开(公告)日：1988-06-28
申请号：US9004
申请日：1987-01-28
申请人： David B. Scott , Satwinder S. Malhi
发明人： David B. Scott , Satwinder S. Malhi
IPC分类号： H01L21/822 , H01L27/06 , H01L27/092 , H01L27/02 , H01L29/04 , H01L29/78
CPC分类号： H01L27/0688 , H01L21/8221 , H01L27/0922
摘要： A CMOS device wherein the NMOS devices are bulk devices and the PMOS devices are SOI devices. The PMOS devices are formed with their channel regions in a silicon-on-insulator layer, preferably a laterally recrystallized annealed-polysilicon layer over a silicon dioxide layer.
摘要翻译： CMOS器件，其中NMOS器件是体器件，PMOS器件是SOI器件。 PMOS器件在绝缘体上硅层中形成它们的沟道区，优选在二氧化硅层上形成横向再结晶的退火多晶硅层。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式