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1. 发明申请

US20110053358A1 METHOD FOR MANUFACTURING MICROCRYSTALLINE SEMICONDUCTOR FILM AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：制造微晶半导体膜的方法和制造半导体器件的方法
公开(公告)号：US20110053358A1
公开(公告)日：2011-03-03
申请号：US12860175
申请日：2010-08-20
申请人： Satoshi TORIUMI , Ryota TAJIMA , Takashi OHTSUKI , Tetsuhiro TANAKA , Ryo TOKUMARU , Mitsuhiro ICHIJO , Kazutaka KURIKI , Tomokazu YOKOI , Toshiya ENDO , Shunpei YAMAZAKI
发明人： Satoshi TORIUMI , Ryota TAJIMA , Takashi OHTSUKI , Tetsuhiro TANAKA , Ryo TOKUMARU , Mitsuhiro ICHIJO , Kazutaka KURIKI , Tomokazu YOKOI , Toshiya ENDO , Shunpei YAMAZAKI
IPC分类号： H01L21/20
CPC分类号： H01J37/32541 , C23C16/24 , C23C16/45565 , C23C16/45574 , C23C16/5096 , H01J37/3244 , H01J37/32449 , H01J37/32834 , H01L21/0262 , H01L29/66765 , H01L29/78696
摘要： An object of one embodiment of the present invention is to provide a technique for manufacturing a dense crystalline semiconductor film (e.g., a microcrystalline semiconductor film) without a cavity between crystal grains. A plasma region is formed between a first electrode and a second electrode by supplying high-frequency power of 60 MHz or less to the first electrode under a condition where a pressure of a reactive gas in a reaction chamber of a plasma CVD apparatus is set to 450 Pa to 13332 Pa, and a distance between the first electrode and the second electrode of the plasma CVD apparatus is set to 1 mm to 20 mm; crystalline deposition precursors are formed in a gas phase including the plasma region; a crystal nucleus of 5 nm to 15 nm is formed by depositing the deposition precursors; and a microcrystalline semiconductor film is formed by growing a crystal from the crystal nucleus.
摘要翻译：本发明的一个实施例的目的是提供一种在晶粒之间没有空腔的致密结晶半导体膜（例如，微晶半导体膜）的制造技术。在等离子体CVD装置的反应室中的反应气体的压力设定为：将第一电极和第二电极的反应气体的压力设定为第一电极的状态下，向第一电极供给60MHz以下的高频电力，在第一电极与第二电极之间形成等离子体区域 450Pa〜13332Pa，等离子体CVD装置的第一电极和第二电极之间的距离设定为1mm〜20mm; 在包括等离子体区域的气相中形成结晶沉积前体; 通过沉积沉积前体形成5nm至15nm的晶核; 并且通过从晶核生长晶体形成微晶半导体膜。

2. 发明申请

US20110097877A1 METHOD FOR MANUFACTURING MICROCRYSTALLINE SEMICONDUCTOR AND THIN FILM TRANSISTOR 有权
标题翻译：制造微晶半导体和薄膜晶体管的方法
公开(公告)号：US20110097877A1
公开(公告)日：2011-04-28
申请号：US12908228
申请日：2010-10-20
申请人： Mitsuhiro ICHIJO , Kazutaka KURIKI , Tomokazu YOKOI , Toshiya ENDO
发明人： Mitsuhiro ICHIJO , Kazutaka KURIKI , Tomokazu YOKOI , Toshiya ENDO
IPC分类号： H01L21/205 , C23C16/513
CPC分类号： H01L21/02532 , C23C16/45565 , C23C16/505 , H01L21/02595 , H01L21/0262 , H01L27/1214 , H01L27/127 , H01L29/04 , H01L29/66765 , H01L29/78696
摘要： A technique for manufacturing a microcrystalline semiconductor layer with high mass productivity is provided. In a reaction chamber of a plasma CVD apparatus, an upper electrode and a lower electrode are provided in almost parallel to each other. A hollow portion is formed in the upper electrode, and the upper electrode includes a shower plate having a plurality of holes formed on a surface of the upper electrode which faces the lower electrode. A substrate is provided over the lower electrode. A gas containing a deposition gas and hydrogen is supplied to the reaction chamber from the shower plate through the hollow portion of the upper electrode, and a rare gas is supplied to the reaction chamber from a portion different from the upper electrode. Accordingly, high-frequency power is supplied to the upper electrode to generate plasma, so that a microcrystalline semiconductor layer is formed over the substrate.
摘要翻译：提供了一种以高质量生产率制造微晶半导体层的技术。在等离子体CVD装置的反应室中，上部电极和下部电极彼此平行地设置。在上部电极中形成中空部，上部电极具有形成在上部电极的与下部电极相对的面上形成的多个孔的喷淋板。衬底设置在下电极上。含有沉积气体和氢气的气体从淋浴板通过上部电极的中空部分供应到反应室，并且稀有气体从不同于上部电极的部分供应到反应室。因此，向上部电极提供高频电力以产生等离子体，从而在基板上形成微晶半导体层。

3. 发明申请

US20120100677A1 METHOD FOR MANUFACTURING MICROCRYSTALLINE SEMICONDUCTOR AND THIN FILM TRANSISTOR 有权
标题翻译：制造微晶半导体和薄膜晶体管的方法
公开(公告)号：US20120100677A1
公开(公告)日：2012-04-26
申请号：US13343734
申请日：2012-01-05
申请人： Mitsuhiro ICHIJO , Kazutaka KURIKI , Tomokazu YOKOI , Toshiya ENDO
发明人： Mitsuhiro ICHIJO , Kazutaka KURIKI , Tomokazu YOKOI , Toshiya ENDO
IPC分类号： H01L21/336 , H01L21/205
CPC分类号： H01L21/02532 , C23C16/45565 , C23C16/505 , H01L21/02595 , H01L21/0262 , H01L27/1214 , H01L27/127 , H01L29/04 , H01L29/66765 , H01L29/78696
摘要： A technique for manufacturing a microcrystalline semiconductor layer with high mass productivity is provided. In a reaction chamber of a plasma CVD apparatus, an upper electrode and a lower electrode are provided in almost parallel to each other. A hollow portion is formed in the upper electrode, and the upper electrode includes a shower plate having a plurality of holes formed on a surface of the upper electrode which faces the lower electrode. A substrate is provided over the lower electrode. A gas containing a deposition gas and hydrogen is supplied to the reaction chamber from the shower plate through the hollow portion of the upper electrode, and a rare gas is supplied to the reaction chamber from a portion different from the upper electrode. Accordingly, high-frequency power is supplied to the upper electrode to generate plasma, so that a microcrystalline semiconductor layer is formed over the substrate.
摘要翻译：提供了一种以高质量生产率制造微晶半导体层的技术。在等离子体CVD装置的反应室中，上部电极和下部电极彼此平行地设置。在上部电极中形成中空部，上部电极具有形成在上部电极的与下部电极相对的面上形成的多个孔的喷淋板。衬底设置在下电极上。含有沉积气体和氢气的气体从淋浴板通过上部电极的中空部分供应到反应室，并且稀有气体从不同于上部电极的部分供应到反应室。因此，向上部电极提供高频电力以产生等离子体，从而在基板上形成微晶半导体层。

4. 发明申请

US20100327281A1 THIN FILM TRANSISTOR AND METHOD FOR MANUFACTURING THE SAME 有权
标题翻译：薄膜晶体管及其制造方法
公开(公告)号：US20100327281A1
公开(公告)日：2010-12-30
申请号：US12820201
申请日：2010-06-22
申请人： Miyako NAKAJIMA , Hidekazu MIYAIRI , Toshiyuki ISA , Erika KATO , Mitsuhiro ICHIJO , Kazutaka KURIKI , Tomokazu YOKOI
发明人： Miyako NAKAJIMA , Hidekazu MIYAIRI , Toshiyuki ISA , Erika KATO , Mitsuhiro ICHIJO , Kazutaka KURIKI , Tomokazu YOKOI
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/6675 , H01L29/04 , H01L29/4908 , H01L29/66765 , H01L29/78669 , H01L29/78678 , H01L29/78696
摘要： An object is to provide a thin film transistor with small off current, large on current, and high field-effect mobility. A silicon nitride layer and a silicon oxide layer which is formed by oxidizing the silicon nitride layer are stacked as a gate insulating layer, and crystals grow from an interface of the silicon oxide layer of the gate insulating layer to form a microcrystalline semiconductor layer; thus, an inverted staggered thin film transistor is manufactured. Since crystals grow from the gate insulating layer, the thin film transistor can have a high crystallinity, large on current, and high field-effect mobility. In addition, a buffer layer is provided to reduce off current.
摘要翻译：目的是提供具有小截止电流，大电流和高场效应迁移率的薄膜晶体管。层叠氮化硅层和通过氧化氮化硅层形成的氧化硅层作为栅极绝缘层，从栅极绝缘层的氧化硅层的界面生长晶体，形成微晶半导体层; 因此，制造了反交错的薄膜晶体管。由于晶体从栅极绝缘层生长，所以薄膜晶体管可以具有高结晶度，大电流和高的场效应迁移率。此外，提供缓冲层以减少电流。

5. 发明申请

US20120156556A1 ACTIVE MATERIAL, ELECTRODE INCLUDING THE ACTIVE MATERIAL AND MANUFACTURING METHOD THEREOF, AND SECONDARY BATTERY 有权
标题翻译：活性材料，包括活性材料的电极及其制造方法和二次电池
公开(公告)号：US20120156556A1
公开(公告)日：2012-06-21
申请号：US13307052
申请日：2011-11-30
申请人： Kazutaka KURIKI , Mitsuhiro Ichijo , Toshiya Endo
发明人： Kazutaka KURIKI , Mitsuhiro Ichijo , Toshiya Endo
IPC分类号： H01M10/02 , H01M4/66 , H01M4/58
CPC分类号： H01M4/366 , H01M4/0428 , H01M4/134 , H01M4/1395 , H01M4/386 , H01M4/48 , H01M4/661 , Y02E60/122 , Y02P70/54
摘要： An electrode in which a silicon layer is provided over a current collector, a thin film layer having a thickness within a certain range is provided on a surface of the silicon layer, and the thin film layer contains fluorine, is used for a power storage device. The thickness of the thin film layer containing fluorine is greater than 0 nm and less than or equal to 10 nm, preferably greater than or equal to 4 nm and less than or equal to 9 nm. The fluorine concentration of the thin film layer containing fluorine is preferably as high as possible, and the nitrogen concentration, the oxygen concentration, and the hydrogen concentration thereof are preferably as low as possible.
摘要翻译：在硅层的表面上设置有在集电体上设置硅层的电极，厚度在一定范围内的薄膜层，薄膜层含有氟，用于蓄电装置。含氟的薄膜层的厚度大于0nm且小于或等于10nm，优选大于或等于4nm且小于或等于9nm。含氟的薄膜层的氟浓度优选尽可能高，氮浓度，氧浓度和氢浓度优选尽可能低。

6. 发明申请

US20110305950A1 POWER STORAGE DEVICE 有权
标题翻译：电源存储设备
公开(公告)号：US20110305950A1
公开(公告)日：2011-12-15
申请号：US13153503
申请日：2011-06-06
申请人： Kazutaka KURIKI , Kiyofumi OGINO , Tomokazu YOKOI , Makoto ISHIKAWA , Toshihiko TAKEUCHI
发明人： Kazutaka KURIKI , Kiyofumi OGINO , Tomokazu YOKOI , Makoto ISHIKAWA , Toshihiko TAKEUCHI
IPC分类号： H01M4/64 , H01G9/042 , H01M10/04
CPC分类号： H01G11/26 , H01M4/134 , H01M4/661 , H01M4/667 , H01M10/0525 , H01M2004/025 , Y02E60/122 , Y02E60/13
摘要： An electrode for a power storage device with less deterioration due to charge and discharge and a power storage device using the electrode are provided. In the electrode for a power storage device and the power storage device, a region including a metal element which functions as a catalyst is selectively provided over a current collector, and then, an active material layer is formed. By selectively providing the region including the metal element, a whisker can be effectively generated in the active material layer over the current collector, and the whisker generation region can be controlled. Accordingly, the discharge capacity can be increased and the cycle characteristics can be improved.
摘要翻译：提供了一种用于蓄电装置的放电劣化少的电极和使用该电极的蓄电装置。在蓄电装置用电极和蓄电装置中，在集电体上选择性地设置作为催化剂的金属元素的区域，形成活性物质层。通过选择性地提供包括金属元素的区域，可以在集电体上的有源材料层中有效地产生晶须，并且可以控制晶须产生区域。因此，可以提高放电容量，并且可以提高循环特性。

7. 发明申请

US20090098739A1 METHOD FOR MANUFACTURING SOI SUBSTRATE 有权
标题翻译：制造SOI衬底的方法
公开(公告)号：US20090098739A1
公开(公告)日：2009-04-16
申请号：US12244414
申请日：2008-10-02
申请人： Hideto OHNUMA , Takashi SHINGU , Tetsuya KAKEHATA , Kazutaka KURIKI , Shunpei YAMAZAKI
发明人： Hideto OHNUMA , Takashi SHINGU , Tetsuya KAKEHATA , Kazutaka KURIKI , Shunpei YAMAZAKI
IPC分类号： H01L21/31
CPC分类号： H01L27/1266 , H01L21/2007 , H01L21/76254 , H01L27/1214 , H01L29/66772
摘要： An object of the present invention is to provide a method for manufacturing an SOI substrate provided with a semiconductor layer which can be used practically even where a substrate having a low upper temperature limit such as a glass substrate is used. The manufacturing method compromises the steps of preparing a semiconductor substrate provided with a bonding layer formed on a surface thereof and a separation layer formed at a predetermined depth from the surface thereof, bonding the bonding layer to the base substrate having a distortion point of 700° C. or lower so that the semiconductor substrate and the base substrate face each other, and separating a part of the semiconductor substrate at the separation layer by heat treatment in order to form a single-crystal semiconductor layer over the base substrate. In the manufacturing method, a substrate which shrinks isotropically at least by the heat treatment is used as the base substrate.
摘要翻译：本发明的目的是提供一种制造具有半导体层的SOI衬底的方法，即使在使用诸如玻璃衬底的上限温度低的衬底的情况下也可以使用。制造方法损害了制备其表面上形成有接合层的半导体衬底和从其表面形成在预定深度的分离层的步骤，将接合层粘合到具有700°的变形点的基底 C.或更低，使得半导体衬底和基底基板彼此面对，并且通过热处理在分离层处分离半导体衬底的一部分，以在基底衬底上形成单晶半导体层。在制造方法中，使用至少通过热处理各向同性收缩的基板作为基底。

8. 发明申请

US20110212363A1 POWER STORAGE SYSTEM AND MANUFACTURING METHOD THEREFOR AND SECONDARY BATTERY AND CAPACITOR 审中-公开
标题翻译：电力储存系统及其二次电池和电容器的制造方法
公开(公告)号：US20110212363A1
公开(公告)日：2011-09-01
申请号：US13033877
申请日：2011-02-24
申请人： Shunpei YAMAZAKI , Tamae MORIWAKA , Kazutaka KURIKI , Mikio YUKAWA
发明人： Shunpei YAMAZAKI , Tamae MORIWAKA , Kazutaka KURIKI , Mikio YUKAWA
IPC分类号： H01M10/26 , H01G9/00 , H01M4/48 , H01M4/505 , H01G9/042 , H01M4/26 , B82Y99/00
CPC分类号： H01G11/26 , H01G11/28 , H01G11/32 , H01G11/46 , H01M4/131 , H01M4/134 , H01M4/1395 , H01M4/366 , H01M4/587 , H01M4/62 , H01M10/0525 , H01M10/0561 , H01M2004/021 , Y02E60/13 , Y10T29/417 , Y10T29/49108 , Y10T29/49115
摘要： The present invention relates to a power storage system including a negative electrode which has a crystalline silicon film provided as a negative electrode active material on the surface of a current collector and contains a conductive oxide in a surface layer section of the crystalline silicon film. Alternatively, the present invention relates to a method for manufacturing a power storage system, which includes the step of forming an amorphous silicon film on a current collector, adding a catalytic element for promoting crystallization of the amorphous silicon, onto a surface of the amorphous silicon film, heating the amorphous silicon film with the catalytic element added to crystallize the amorphous silicon film and thereby form a crystalline silicon film, and using the crystalline silicon film as a negative electrode active material layer.
摘要翻译：本发明涉及一种蓄电系统，其包括负极，该负极具有在集电体的表面上设置为负极活性物质的结晶硅膜，并且在结晶硅膜的表层部分中含有导电氧化物。或者，本发明涉及一种用于制造蓄电系统的方法，其包括在集电器上形成非晶硅膜的步骤，将非晶硅的结晶的催化元素添加到非晶硅的表面上加热非晶硅膜，加入催化剂元素使非晶硅膜结晶，从而形成结晶硅膜，并使用结晶硅膜作为负极活性物质层。

9. 发明申请

US20120141866A1 POWER STORAGE DEVICE 有权
标题翻译：电源存储设备
公开(公告)号：US20120141866A1
公开(公告)日：2012-06-07
申请号：US13307045
申请日：2011-11-30
申请人： Kazutaka KURIKI , Nobuhiro Inoue , Kiyofumi Ogino
发明人： Kazutaka KURIKI , Nobuhiro Inoue , Kiyofumi Ogino
IPC分类号： H01M4/66 , H01M10/02 , H01G9/032
CPC分类号： H01M4/366 , H01G11/06 , H01G11/50 , H01G11/68 , H01G11/72 , H01M4/382 , H01M4/386 , H01M4/661 , H01M10/0525 , H01M10/0562 , H01M2004/027 , Y02E60/122 , Y02E60/13 , Y02T10/7022
摘要： A power storage device which has improved performance such as higher discharge capacity and in which deterioration due to peeling or the like of an active material layer is less likely to be caused is provided. In an electrode for the power storage device, phosphorus-doped amorphous silicon is used for the active material layer over a current collector as a material that can be alloyed with lithium, and niobium oxide is deposited over the active material layer as a layer containing niobium. Accordingly, the capacity of the power storage device can be increased and the cycle characteristics and the charge-discharge efficiency can be improved.
摘要翻译：提供了一种具有改善的性能的蓄电装置，例如较高的放电容量，并且由于活性材料层的剥离等而导致的劣化不大可能。在蓄电装置的电极中，作为可与锂合金化的材料，在集电体上使用磷掺杂非晶硅作为活性物质层，在活性物质层上沉积氧化铌作为含有铌的层。因此，能够提高蓄电装置的容量，能够提高循环特性和充放电效率。

10. 发明申请

US20110269301A1 MANUFACTURING METHOD OF SINGLE CRYSTAL SEMICONDUCTOR FILM AND MANUFACTURING METHOD OF ELECTRODE 有权
标题翻译：单晶半导体膜的制造方法及电极的制造方法
公开(公告)号：US20110269301A1
公开(公告)日：2011-11-03
申请号：US13092249
申请日：2011-04-22
申请人： Sho KATO , Kazutaka KURIKI
发明人： Sho KATO , Kazutaka KURIKI
IPC分类号： H01L21/20
CPC分类号： H01L21/76251
摘要： To provide a method of obtaining a single crystal semiconductor film by a method that is simple and low-cost. A single crystal semiconductor film 11 having compression stress is formed over a surface of a single crystal semiconductor substrate 10 by a vapor phase epitaxial growth method, a film having tensile stress (for example, a thermo-setting resin film 12) is formed over a surface of the single crystal semiconductor film 11, and the single crystal semiconductor substrate 10 and the single crystal semiconductor film 11 are separated from each other by a separation step in which force is applied to the single crystal semiconductor film 11, thereby obtaining a single crystal semiconductor film. Note that as the thermo-setting resin film 12, an epoxy resin film can be used, for example.
摘要翻译：提供通过简单且低成本的方法获得单晶半导体膜的方法。通过气相外延生长法在单晶半导体衬底10的表面上形成具有压应力的单晶半导体膜11，在其上形成具有拉伸应力的膜（例如，热固性树脂膜12）通过对单晶半导体膜11施加力的分离工序将单晶半导体膜11的表面，单晶半导体基板10和单晶半导体膜11分离，得到单晶半导体膜。另外，作为热固性树脂膜12，例如可以使用环氧树脂膜。

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