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1. 发明授权

US5239194A Semiconductor device having increased electrostatic breakdown voltage 失效
标题翻译：具有增加静电破坏电压的半导体器件
公开(公告)号：US5239194A
公开(公告)日：1993-08-24
申请号：US661816
申请日：1991-02-28
申请人： Satoshi Ohtani , Masayuki Yoshida , Nobutaka Kitagawa , Tomotaka Saito
发明人： Satoshi Ohtani , Masayuki Yoshida , Nobutaka Kitagawa , Tomotaka Saito
IPC分类号： H01L27/02
CPC分类号： H01L27/0266
摘要： A semiconductor substrate has a plurality of MOS transistors formed therein. Each of the transistors comprises high density diffusion regions having high impurity density and serving as source and drain, low density diffusion regions having low impurity density and extending in contact with the high density diffusion regions, respectively, a channel region formed between the low density diffusion regions, and a gate formed above the substrate and insulated from the channel region. One of the transistors has its drain connected to an input/output terminal. The low density diffusion region of the one has impurity density higher than that of the other. The channel length of the one is greater than that of the other.

2. 发明授权

US5057702A Duty radio control circuit apparatus 失效
标题翻译：负责无线电控制电路的设备
公开(公告)号：US5057702A
公开(公告)日：1991-10-15
申请号：US457875
申请日：1989-12-27
申请人： Nobutaka Kitagawa , Hiroki Muroga , Tomotaka Saito
发明人： Nobutaka Kitagawa , Hiroki Muroga , Tomotaka Saito
IPC分类号： H03K5/04 , H03K5/156
CPC分类号： H03K5/1565
摘要： An integrating circuit integrates an input signal. When an output from the integrating circuit is input to an AC coupling circuit, only an AC component of the output is extracted. The AC component which passes through the AC coupling circuit is waveshaped and coverted into a rectangular wave by a waveshaping circuit. The duty ratio of the waveshaped rectangular wave is detected by a duty ratio detecting circuit. A voltage corresponding to the duty ratio is then generated and fed back to the output of the AC coupling circuit through a feedback circuit. As a result, a DC bias component is applied to the AC component which has passed through the AC coupling circuit. In this case, the voltage generated by the duty ratio detecting circuit is controlled to coincide with the circuit threshold value of the waveshaping circuit, and a rectangular wave having a duty ratio of 50% is output from the waveshaping circuit.

3. 发明授权

US06989980B2 Semiconductor device having a protection circuit 失效
标题翻译：具有保护电路的半导体装置
公开(公告)号：US06989980B2
公开(公告)日：2006-01-24
申请号：US10800999
申请日：2004-03-16
申请人： Nobutaka Kitagawa
发明人： Nobutaka Kitagawa
IPC分类号： H02H3/20 , H02H9/00
CPC分类号： H02H9/046
摘要： A semiconductor device having a protection circuit comprising an NPN type bipolar transistor having a collector and an emitter connected between an external connection terminal of the semiconductor device to be protected and a reference terminal, a PMOS transistor having a drain and source connected between the base and the collector of the NPN type bipolar transistor and configured to supply a base current to the base of the NPN type bipolar transistor, and a control circuit configured to supply the control signal to the gate of the PMOS transistor in response to a voltage emerging on the external connection terminal.
摘要翻译：一种具有保护电路的半导体器件，包括具有集电极和发射极的NPN型双极晶体管，所述集电极和发射极连接在待保护的半导体器件的外部连接端子和参考端子之间，PMOS晶体管的漏极和源极连接在基极和 NPN型双极晶体管的集电极，并且被配置为向NPN型双极晶体管的基极提供基极电流;以及控制电路，被配置为响应于PMOS晶体管的栅极而向PMOS晶体管的栅极提供控制信号外部连接端子。

4. 发明申请

US20050111153A1 Semiconductor integrated circuit having protection elements for preventing MOS transistors from plasma damage 失效
标题翻译：具有用于防止MOS晶体管等离子体损坏的保护元件的半导体集成电路
公开(公告)号：US20050111153A1
公开(公告)日：2005-05-26
申请号：US10982431
申请日：2004-11-04
申请人： Nobutaka Kitagawa
发明人： Nobutaka Kitagawa
IPC分类号： H01L27/04 , H01L21/822 , H01L27/02 , H02H3/20
CPC分类号： H01L27/0266
摘要： A semiconductor integrated circuit having protection elements for protecting a MOSFET of a high accuracy analog circuit from plasma damage generated during a manufacture of the semiconductor integrated circuit is provided. The protection elements operate at a lower voltage of PN junction breakdown voltage so as to prevent transistors from degrading or having dielectric breakdown due to plasma damage. A differential amplifier includes first and second n-channel MOS transistors for constructing a differential input pair. A first protection element comprising a plurality of gate-drain connected MOS transistors coupled as a cascade is provided between the gate of the first n-channel MOS transistor and a first differential input terminal. A second protection element comprising a plurality of gate-drain connected MOS transistors coupled as a cascade is provided between the gate of the second n-channel MOS transistor and a second differential input terminal. Each of the first and second protection elements operates at a lower voltage of PN junction breakdown voltage.
摘要翻译：提供了一种半导体集成电路，其具有用于保护高精度模拟电路的MOSFET免受在半导体集成电路的制造期间产生的等离子体损伤的保护元件。保护元件在PN结击穿电压的较低电压下工作，以防止晶体管由于等离子体损坏而劣化或具有绝缘击穿。差分放大器包括用于构造差分输入对的第一和第二n沟道MOS晶体管。在第一n沟道MOS晶体管的栅极和第一差分输入端子之间设置包括作为级联耦合的多个栅极 - 漏极连接的MOS晶体管的第一保护元件。在第二n沟道MOS晶体管的栅极和第二差分输入端子之间设置包括作为级联耦合的多个栅极 - 漏极连接的MOS晶体管的第二保护元件。第一和第二保护元件中的每一个以PN结击穿电压的较低电压工作。

5. 发明申请

US20050099744A1 Semiconductor integrated circuit 审中-公开
标题翻译：半导体集成电路
公开(公告)号：US20050099744A1
公开(公告)日：2005-05-12
申请号：US10798402
申请日：2004-03-12
申请人： Nobutaka Kitagawa
发明人： Nobutaka Kitagawa
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8234 , H01L27/02 , H01L27/06 , H01L27/088 , H02H9/00
CPC分类号： H01L27/0251
摘要： There is disclosed an inner circuit constituted of a high voltage-proof circuit section and a low voltage-proof circuit section. A usual protective circuit against a surge is directly connected to an external terminal of an IC outside the inner circuit. The high voltage-proof circuit section includes a MOS transistor driven by a power voltage VDD. The low voltage-proof circuit section includes a MOS transistor driven by a power voltage Vdd lower than the power voltage VDD. The protective circuit against the surge is individually connected to the MOS transistor driven by the power voltage Vdd. A capacitor, diode, and the like are used as the protective circuit.
摘要翻译：公开了由耐高压电路部和低电压保护电路部构成的内部电路。防止浪涌的通常的保护电路直接连接到内部电路外部的IC的外部端子。高耐压电路部分包括由电源电压VDD驱动的MOS晶体管。低压保护电路部分包括由比电源电压VDD低的电源电压Vdd驱动的MOS晶体管。针对浪涌的保护电路单独连接到由电源电压Vdd驱动的MOS晶体管。电容器，二极管等用作保护电路。

6. 发明授权

US5731774A Digital-to-analog converter 失效
标题翻译：数模转换器
公开(公告)号：US5731774A
公开(公告)日：1998-03-24
申请号：US704077
申请日：1996-08-28
申请人： Kazuhito Fujii , Nobutaka Kitagawa
发明人： Kazuhito Fujii , Nobutaka Kitagawa
IPC分类号： H03M1/76 , H03K19/20 , H03M1/68 , H03M1/74
CPC分类号： H03M1/682 , H03M1/685 , H03M1/74 , H03M1/765
摘要： A digital-to-analog converter includes a D/A converter circuit section, connection switching control circuit and multi-input operational amplifier circuit. The D/A converter circuit section is supplied with a binary code of upper i bits of an n-bit (1.ltoreq.i
摘要翻译：数模转换器包括D / A转换器电路部分，连接切换控制电路和多输入运算放大器电路。 D / A转换器电路部分提供n位（1

7. 发明授权

US07218150B2 Semiconductor integrated circuit device and differential small-amplitude data transmission apparatus 失效
标题翻译：半导体集成电路器件和差分小振幅数据传输设备
公开(公告)号：US07218150B2
公开(公告)日：2007-05-15
申请号：US10875126
申请日：2004-06-22
申请人： Nobutaka Kitagawa , Isamu Satoh
发明人： Nobutaka Kitagawa , Isamu Satoh
IPC分类号： H03K19/0175 , H03K19/094 , H03K19/082 , H03K17/16 , H03K19/003
CPC分类号： H04L25/0286 , H03K17/163 , H04L25/0272
摘要： An output driving circuit has a first and second differential output nodes connected to a first and second external output terminals, respectively. A capacitance connection circuit is connected between the first and second differential output nodes. The capacitance connection circuit connects a capacitance between the first and second differential output nodes. The capacitance connection circuit then adjusts the value of the capacitance in accordance with a control signal.
摘要翻译：输出驱动电路具有分别连接到第一和第二外部输出端子的第一和第二差分输出节点。电容连接电路连接在第一和第二差分输出节点之间。电容连接电路连接第一和第二差分输出节点之间的电容。然后，电容连接电路根据控制信号调整电容值。

8. 发明授权

US07106562B2 Protection circuit section for semiconductor circuit system 失效
公开(公告)号：US07106562B2
公开(公告)日：2006-09-12
申请号：US10417112
申请日：2003-04-17
申请人： Nobutaka Kitagawa
发明人： Nobutaka Kitagawa
IPC分类号： H02H9/00
CPC分类号： H01L27/0251
摘要： A semiconductor circuit system has first, second, and third external terminals electrically separated from each other. The first external terminal is configured to receive a first power supply voltage in a normal operation. A protection circuit section is provided in the circuit system and includes a rectifier to allow a surge current to pass therethrough. The rectifier has a current passage connected between a specific terminal connected to a protection target and the third external terminal. The protection circuit section further includes a first PMOS transistor configured to trigger the rectifier, based on a surge voltage inputted into the second external terminal. The first PMOS transistor has a current passage connected between the second external terminal and a base of the NPN transistor. The first PMOS transistor has a gate connected to the first external terminal.

9. 发明授权

US6166671A Analog-to-digital converting circuit apparatus and coverting method thereof 失效
标题翻译：模数转换电路装置及其转换方法
公开(公告)号：US6166671A
公开(公告)日：2000-12-26
申请号：US160541
申请日：1998-09-25
申请人： Nobutaka Kitagawa , Yoshikazu Nagashima
发明人： Nobutaka Kitagawa , Yoshikazu Nagashima
IPC分类号： H03M1/38 , H03M1/06 , H03M1/12 , H03M1/66 , H03M1/84 , H03M1/88
CPC分类号： H03M1/0624 , H03M1/12
摘要： The analog-to-digital converting circuit apparatus of the invention is intended to realize both low voltage operation and high speed operation of an analog-to-digital converting circuit without impairing the precision characteristic. In plural boosting circuits, voltages higher than each supply voltage are generated. These plural boosting circuits are controlled as the control timing is sequentially shifted by the controller. The boosted voltages delivered from the plural boosting circuits are accumulated in the capacitor, and supplied into the analog-to-digital converter. In the analog-to-digital converter, at the timing other than the changeover timing of the converting action of the analog-to-digital converter, the plural boosting circuits are changed over sequentially, and the boosted voltages are converted from analog to digital values.
摘要翻译：本发明的模拟 - 数字转换电路装置旨在实现模数转换电路的低电压操作和高速操作，而不损害精度特性。在多个升压电路中，产生高于每个电源电压的电压。当控制器依次移动控制定时时，控制这些多个升压电路。从多个升压电路输出的升压电压累积在电容器中，并被提供给模数转换器。在模数转换器中，在模数转换器的转换动作的转换定时之外的定时，多个升压电路依次改变，升压后的电压从模数转换为数字值。

10. 发明授权

US6147525A Frequency multiplier circuit operable with an external reference clock signal having a frequency in a wide range 失效
标题翻译：频率乘法器电路与具有宽范围频率的外部参考时钟信号可操作
公开(公告)号：US6147525A
公开(公告)日：2000-11-14
申请号：US199821
申请日：1998-11-25
申请人： Hiroshi Mitani , Nobutaka Kitagawa , Kazuhito Fujii
发明人： Hiroshi Mitani , Nobutaka Kitagawa , Kazuhito Fujii
IPC分类号： G06F1/08 , G11C11/407 , G11C11/4076 , H03K5/00 , H03K5/13 , H03L7/081 , H03L7/089 , H03L7/16 , H03B19/00
CPC分类号： H03K5/133 , H03K5/00006 , H03L7/0814 , H03L7/0891 , H03L7/16 , H03K2005/00039 , H03K2005/00058
摘要： A frequency multiplier circuit needs to have a voltage controlled oscillator circuit having a wide oscillation frequency range, or delay cells each having a delay value which can be controlled over a wide range. Depending on the frequency multiplication factor, however, a frequency multiplied clock signal susceptible to influence of noise is generated. In the disclosed frequency multiplier circuit, there are provided a phase comparison input selection circuit for conducting a selection out of output signals of delay cells forming a voltage controlled delay circuit according to a frequency multiplication factor setting signal and an input frequency range setting signal and outputting the selected signal to a phase comparator, and a selected waveform generation circuit for generating a frequency multiplied clock signal CKOUT from the output signals of the delay cells according to the frequency multiplication factor setting signal and the input frequency range setting signal.
摘要翻译：倍频电路需要具有宽振荡频率范围的压控振荡器电路，或者每个具有可在宽范围内被控制的延迟值的延迟单元。然而，根据倍频因子，产生易受噪声影响的倍频时钟信号。在所公开的倍频电路中，提供了一个相位比较输入选择电路，用于根据倍频因子设置信号和输入频率范围设置信号，对构成电压控制延迟电路的延迟单元的输出信号进行选择，并输出所选择的信号到相位比较器，以及选择的波形发生电路，用于根据倍频因子设置信号和输入频率范围设置信号从延迟单元的输出信号产生倍频时钟信号CKOUT。

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