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1. 发明授权

US07281155B1 Semiconductor memory device and method for executing shift redundancy operation 有权
标题翻译：用于执行移位冗余操作的半导体存储器件和方法
公开(公告)号：US07281155B1
公开(公告)日：2007-10-09
申请号：US09359767
申请日：1999-07-22
申请人： Satoshi Eto , Masato Matsumiya , Toshimi Ikeda , Yuki Ishii , Akira Kikutake , Kuninori Kawabata
发明人： Satoshi Eto , Masato Matsumiya , Toshimi Ikeda , Yuki Ishii , Akira Kikutake , Kuninori Kawabata
IPC分类号： H02H3/05
CPC分类号： G11C29/78
摘要： A semiconductor memory device having a shift redundancy function includes a switch circuit for changeably connecting a plurality of decode signal lines decoding an address signal to a plurality of selecting lines and redundancy selecting lines, and executes a switch operation for shifting at least one of a plurality of decode lines in the direction of a first redundancy selecting line positioned at one of the ends among a plurality of selecting lines or a second switch operation for shifting at least one of the decode lines in the direction of a second redundancy selecting line positioned at the other end among the selecting lines or both of the first and second operations when any fault occurs in a plurality of selecting lines. The semiconductor memory device preferably includes two or more first redundancy selecting lines positioned at one of the ends of a plurality of selecting lines, two or more second redundancy selecting lines positioned at the other end, and first and second switch units disposed in two stages. When any fault selecting line occurs, the first switch unit executes a first switch operation for shifting at least one of the decode signal lines in the direction of the first redundancy selecting line or a second switch operation for shifting the same in the direction of the second redundancy selecting line, or the second switch unit executes a third switch operation for shifting at least one decode signal line in the direction of the first redundancy selecting line or a fourth switch operation for shifting it in the direction of the second redundancy selecting line.
摘要翻译：具有移位冗余功能的半导体存储器件包括用于将解码地址信号的多条解码信号线与多条选择线和冗余选择线可变地连接的开关电路，并且执行用于移位多个选择线和冗余选择线中的至少一个的切换操作在位于多个选择线中的一端的第一冗余选择线的方向上的解码线的第二切换操作或用于沿着位于所述多个选择线的第二冗余选择线的方向移位至少一条解码线的第二切换操作在多个选择线中发生任何故障时，选择线中的另一端或第一和第二操作两者。半导体存储器件优选地包括位于多个选择线的一端的两个或更多个第一冗余选择线，以及位于另一端的两个或更多个第二冗余选择线以及分两个阶段布置的第一和第二开关单元。当发生任何故障选择线时，第一开关单元执行第一开关操作，用于沿第一冗余选择线的方向移位至少一个解码信号线，或者执行第二开关操作，以使其在第二冗余选择线的方向上移位冗余选择线或者第二开关单元执行用于在第一冗余选择线的方向上移位至少一个解码信号线的第三开关操作或者用于在第二冗余选择线的方向上移位的第四开关操作。

2. 发明授权

US07184296B2 Memory device 失效
标题翻译：内存设备
公开(公告)号：US07184296B2
公开(公告)日：2007-02-27
申请号：US11069940
申请日：2005-03-03
申请人： Atsushi Hatakeyama , Toshimi Ikeda , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
发明人： Atsushi Hatakeyama , Toshimi Ikeda , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
IPC分类号： G11C11/00
CPC分类号： G11C16/28
摘要： A memory device has a data line (DATA-BUS) for connection to a memory cell, a reference line (Reference-BUS) for reference, a precharge circuit (101), a load circuit (102), and an amplifier circuit (103). The precharge circuit is connected to the data line and the reference line and configured to precharge the data line and the reference line. The load circuit is connected to the data line and the reference line and configured to apply a first constant current to the data line and apply a second constant current which is smaller than the first constant current to the reference line. The amplification circuit is connected to the data line and the reference line and configured to amplify a differential voltage between the data line and the reference line.
摘要翻译：存储器件具有用于连接到存储单元的数据线（DATA-BUS），用于参考的参考线（Reference-BUS），预充电电路（101），负载电路（102）和放大器电路（103））。预充电电路连接到数据线和参考线，并配置为对数据线和参考线进行预充电。负载电路连接到数据线和参考线，并配置为向数据线施加第一恒定电流，并将比第一恒定电流小的第二恒定电流施加到参考线。放大电路连接到数据线和参考线，并被配置为放大数据线与参考线之间的差分电压。

3. 发明授权

US07307885B2 Multi-value nonvolatile semiconductor memory device equipped with reference cell and load balancing circuit 有权
标题翻译：配有参考电池和负载平衡电路的多值非易失性半导体存储器件
公开(公告)号：US07307885B2
公开(公告)日：2007-12-11
申请号：US11063999
申请日：2005-02-24
申请人： Toshimi Ikeda , Atsushi Hatakeyama , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
发明人： Toshimi Ikeda , Atsushi Hatakeyama , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
IPC分类号： G11C16/28
CPC分类号： G11C16/28 , G11C7/14 , G11C2207/002
摘要： A nonvolatile semiconductor memory device includes a plurality of memory cells holding memory cell information, a plurality of bit lines connected to the plurality of memory cells, the plurality of bit lines including a first bit line conected to a selected one of the plurality of memory cells and a plurality of second bit lines connected to non-selected memory cells, a plurality of reference cells supplying different reference currents respectively, and a read-out circuit, wherein, when reading the memory cell information, the read-out circuit is coupled to the first bit line connected to the selected memory cell and coupled to one of the plurality of reference cells through one of the plurality of second bit lines connected to the non-selected memory cells.
摘要翻译：非易失性半导体存储器件包括保持存储单元信息的多个存储器单元，连接到多个存储器单元的多个位线，多个位线包括与多个存储器单元中选择的一个存储单元相连的第一位线以及连接到未选择的存储器单元的多个第二位线，分别提供不同参考电流的多个参考单元和读出电路，其中当读取存储单元信息时，读出电路耦合到所述第一位线连接到所选择的存储器单元，并且通过连接到所述未选择的存储器单元的所述多个第二位线之一耦合到所述多个参考单元中的一个。

4. 发明申请

US20050185465A1 Memory device 审中-公开
标题翻译：内存设备
公开(公告)号：US20050185465A1
公开(公告)日：2005-08-25
申请号：US11110700
申请日：2005-04-21
申请人： Nobutaka Taniguchi , Atsushi Hatakeyama , Toshimi Ikeda , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
发明人： Nobutaka Taniguchi , Atsushi Hatakeyama , Toshimi Ikeda , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
IPC分类号： G11C8/12 , G11C11/34 , G11C16/26
CPC分类号： G11C16/26 , G11C8/12
摘要： A memory device includes plural banks (BNKA, BNKB, BNKC, and BNKD), and each of the banks includes a plural memory cells storing data and plural bit lines reading data from the plural memory cells. Bit line lengths of all of the plural banks are equal.
摘要翻译：存储器件包括多个存储体（BNKA，BNKB，BNKC和BNKD），并且每个存储体包括存储数据的多个存储单元和从多个存储单元读取数据的多个位线。所有多个组的位线长度相等。

5. 发明申请

US20050141306A1 Memory device 失效
标题翻译：内存设备
公开(公告)号：US20050141306A1
公开(公告)日：2005-06-30
申请号：US11069940
申请日：2005-03-03
申请人： Atsushi Hatakeyama , Toshimi Ikeda , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
发明人： Atsushi Hatakeyama , Toshimi Ikeda , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
IPC分类号： G11C5/06 , G11C16/06 , G11C16/28
CPC分类号： G11C16/28
摘要： A memory device has a data line (DATA-BUS) for connection to a memory cell, a reference line (Reference-BUS) for reference, a precharge circuit (101), a load circuit (102), and an amplifier circuit (103). The precharge circuit is connected to the data line and the reference line and configured to precharge the data line and the reference line. The load circuit is connected to the data line and the reference line and configured to apply a first constant current to the data line and apply a second constant current which is smaller than the first constant current to the reference line. The amplification circuit is connected to the data line and the reference line and configured to amplify a differential voltage between the data line and the reference line.
摘要翻译：存储器件具有用于连接到存储单元的数据线（DATA-BUS），用于参考的参考线（Reference-BUS），预充电电路（101），负载电路（102）和放大器电路（103））。预充电电路连接到数据线和参考线，并配置为对数据线和参考线进行预充电。负载电路连接到数据线和参考线，并配置为向数据线施加第一恒定电流，并将比第一恒定电流小的第二恒定电流施加到参考线。放大电路连接到数据线和参考线，并被配置为放大数据线与参考线之间的差分电压。

6. 发明授权

US06522003B1 Semiconductor device and method of manufacturing the same 失效
标题翻译：半导体装置及其制造方法
公开(公告)号：US06522003B1
公开(公告)日：2003-02-18
申请号：US09472833
申请日：1999-12-28
申请人： Takayoshi Minami , Osamu Tsuboi , Toshimi Ikeda , Masato Matsumiya , Kuninori Kawabata
发明人： Takayoshi Minami , Osamu Tsuboi , Toshimi Ikeda , Masato Matsumiya , Kuninori Kawabata
IPC分类号： H01L2348
CPC分类号： G03F7/70633 , G03F9/7084 , H01L23/522 , H01L23/544 , H01L27/10882 , H01L27/10897 , H01L2223/54426 , H01L2223/54453 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device characterized by comprising a first insulating film formed on the semiconductor substrate, a first wiring or mark formed on the first insulating film, an electrically isolated pattern formed under the first insulating film and below the first wiring or mark, a hole formed in the first insulating film to connect the first wiring or mark and the electrically isolated pattern, and a second insulating film for covering the first wiring or mark.
摘要翻译：一种半导体器件，其特征在于，包括形成在所述半导体衬底上的第一绝缘膜，形成在所述第一绝缘膜上的第一布线或标记，形成在所述第一绝缘膜下方且在所述第一布线或标记下方的电隔离图案，用于连接第一布线或标记和电隔离图案的第一绝缘膜，以及用于覆盖第一布线或标记的第二绝缘膜。

7. 发明申请

US20050162955A1 Nonvolatile semiconductor memory device 有权
标题翻译：非易失性半导体存储器件
公开(公告)号：US20050162955A1
公开(公告)日：2005-07-28
申请号：US11063999
申请日：2005-02-24
申请人： Toshimi Ikeda , Atsushi Hatakeyama , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
发明人： Toshimi Ikeda , Atsushi Hatakeyama , Nobutaka Taniguchi , Akira Kikutake , Kuninori Kawabata , Atsushi Takeuchi
IPC分类号： G11C7/14 , G11C16/26 , G11C16/28 , G11C7/02 , G11C8/00
CPC分类号： G11C16/28 , G11C7/14 , G11C2207/002
摘要： A nonvolatile semiconductor memory device comprises a memory cell array in which memory cells each holding memory cell information are arrayed, reference cells which supply different reference currents respectively, and a read-out circuit. When reading the memory cell information from a selected one of the memory cells, the read-out circuit is brought into conduction to a first global bit line which is connected to a bit line of the selected memory cell, and brought into conduction to one of a plurality of second global bit lines respectively which are provided near the first global bit line and connected to bit lines of non-selected memory cells but not connected to the bit line of the selected memory cell, so that the memory cell information is determined by comparing a read-out current from the selected memory cell with each of the reference currents from the reference cells.
摘要翻译：非易失性半导体存储器件包括其中排列存储单元信息的存储器单元的存储单元阵列，分别提供不同参考电流的参考单元和读出电路。当从所选存储单元中读出存储单元信息时，读出电路被导通到连接到所选存储单元的位线的第一全局位线，并导通到多个第二全局位线分别设置在第一全局位线附近并连接到未选择的存储器单元的位线，但未连接到所选存储单元的位线，使得存储器单元信息由将来自所选存储器单元的读出电流与来自参考单元的每个参考电流进行比较。

8. 发明授权

US6052301A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US6052301A
公开(公告)日：2000-04-18
申请号：US272296
申请日：1999-03-19
申请人： Toshimi Ikeda , Kuninori Kawabata , Masato Takita
发明人： Toshimi Ikeda , Kuninori Kawabata , Masato Takita
IPC分类号： H01L27/10 , G11C7/18 , G11C8/14 , H01L21/8242 , H01L27/108 , G11C5/06
CPC分类号： H01L27/108 , G11C7/18 , G11C8/14
摘要： According to the present invention, the main word lines arranged in a row direction have a linear pattern shape, and in the region where sub word decoder circuits are formed, the pattern of the main word lines has a shape whereby the pattern branches and splits into a plurality of lines and then reconverges, in the direction of the row. In the region where the line splits, relatively small island-shaped patterns of the conducting layer are located, forming nodes which have a difference electric potential from the main word lines. The main word lines are constituted by a first metal conducting layer, similarly to the prior art. In other words, small island-shaped metal layer patterns, which are electrically different from the main word lines are formed inside the conducting metal layer pattern constituting the main word lines, similarly to island formed in the middle of a river, for example.
摘要翻译：根据本发明，排列在行方向上的主字线具有线状图案形状，在形成子字译码器电路的区域中，主字线的图形具有图案分支并分成多行，然后在行的方向上重新转换。在分割线的区域中，导电层的相对较小的岛状图形被定位，形成与主字线具有差电位的节点。与现有技术类似，主字线由第一金属导电层构成。换句话说，与构成主字线的导电金属层图案的内部形成有与主字线电性不同的小岛状金属层图案，与形成在河道中部的岛类似。

9. 发明授权

US06452860B2 Semiconductor memory device having segment type word line structure 有权
标题翻译：具有段型字线结构的半导体存储器件
公开(公告)号：US06452860B2
公开(公告)日：2002-09-17
申请号：US09871646
申请日：2001-06-04
申请人： Masaharu Wada , Kenji Tsuchida , Tsuneo Inaba , Atsushi Takeuchi , Toshimi Ikeda , Kuninori Kawabata
发明人： Masaharu Wada , Kenji Tsuchida , Tsuneo Inaba , Atsushi Takeuchi , Toshimi Ikeda , Kuninori Kawabata
IPC分类号： G11C800
CPC分类号： G11C5/063
摘要： A semiconductor memory device has a segment type word line structure and comprises a plurality of main word lines and a plurality of sub word lines which are arranged at different levels. The semiconductor memory device is provided with a memory cell array divided into a plurality of cell array blocks. A plurality of sub row decoder areas, each for selecting one of the sub word lines, are defined between the cell array blocks. A plurality of first metal wiring lines formed by use of the same wiring layer as the main word lines are provided. The first metal wiring lines pass across the sub row decoder areas and the cell array blocks.
摘要翻译：半导体存储器件具有段类型的字线结构，并且包括多个主字线和排列在不同电平的多个子字线。半导体存储器件设置有分成多个单元阵列块的存储单元阵列。在单元阵列块之间定义多个用于选择一个子字线的子行解码器区域。提供了通过使用与主字线相同的布线层形成的多个第一金属布线。第一金属布线穿过子行解码器区域和单元阵列块。

10. 发明授权

US07064589B2 Semiconductor device using two types of power supplies supplying different potentials 有权
标题翻译：使用提供不同电位的两种电源的半导体器件
公开(公告)号：US07064589B2
公开(公告)日：2006-06-20
申请号：US11075736
申请日：2005-03-10
申请人： Toshimi Ikeda , Kuninori Kawabata , Shuzo Otsuka
发明人： Toshimi Ikeda , Kuninori Kawabata , Shuzo Otsuka
IPC分类号： H03K3/00 , G11C11/34 , G11C16/04 , G11C5/14
CPC分类号： G11C8/08 , G11C11/4085
摘要： A semiconductor device which is driven by a first potential, a second potential lower than the first potential, and a third potential lower than the second potential includes a first Pch transistor and a first Nch transistor connected in series between the first potential and the third potential, a second Pch transistor having a drain node thereof connected to a gate node of the first Nch transistor, and a second Nch transistor having a source node thereof connected to a source node of the second Pch transistor, wherein the drain node and gate node of the second Nch transistor are fixed to the second potential and the first potential, respectively.
摘要翻译：由第一电位，低于第一电位的第二电位和低于第二电位的第三电位驱动的半导体器件包括串联连接在第一电位和第三电位之间的第一Pch晶体管和第一N沟道晶体管，具有连接到第一N沟晶体管的栅极节点的漏极节点的第二Pch晶体管和其源极节点连接到第二Pch晶体管的源极节点的第二N沟道晶体管，其中漏极节点和栅极节点第二Nch晶体管分别被固定到第二电位和第一电位。

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