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1. 发明授权

US07064589B2 Semiconductor device using two types of power supplies supplying different potentials 有权
标题翻译：使用提供不同电位的两种电源的半导体器件
公开(公告)号：US07064589B2
公开(公告)日：2006-06-20
申请号：US11075736
申请日：2005-03-10
申请人： Toshimi Ikeda , Kuninori Kawabata , Shuzo Otsuka
发明人： Toshimi Ikeda , Kuninori Kawabata , Shuzo Otsuka
IPC分类号： H03K3/00 , G11C11/34 , G11C16/04 , G11C5/14
CPC分类号： G11C8/08 , G11C11/4085
摘要： A semiconductor device which is driven by a first potential, a second potential lower than the first potential, and a third potential lower than the second potential includes a first Pch transistor and a first Nch transistor connected in series between the first potential and the third potential, a second Pch transistor having a drain node thereof connected to a gate node of the first Nch transistor, and a second Nch transistor having a source node thereof connected to a source node of the second Pch transistor, wherein the drain node and gate node of the second Nch transistor are fixed to the second potential and the first potential, respectively.
摘要翻译：由第一电位，低于第一电位的第二电位和低于第二电位的第三电位驱动的半导体器件包括串联连接在第一电位和第三电位之间的第一Pch晶体管和第一N沟道晶体管，具有连接到第一N沟晶体管的栅极节点的漏极节点的第二Pch晶体管和其源极节点连接到第二Pch晶体管的源极节点的第二N沟道晶体管，其中漏极节点和栅极节点第二Nch晶体管分别被固定到第二电位和第一电位。

2. 发明申请

US20050152207A1 Semiconductor device using two types of power supplies supplying different potentials 有权
标题翻译：使用提供不同电位的两种电源的半导体器件
公开(公告)号：US20050152207A1
公开(公告)日：2005-07-14
申请号：US11075736
申请日：2005-03-10
申请人： Toshimi Ikeda , Kuninori Kawabata , Shuzo Otsuka
发明人： Toshimi Ikeda , Kuninori Kawabata , Shuzo Otsuka
IPC分类号： G11C8/08 , G11C11/407 , G11C11/408 , G11C8/00
CPC分类号： G11C8/08 , G11C11/4085
摘要： A semiconductor device which is driven by a first potential, a second potential lower than the first potential, and a third potential lower than the second potential includes a first Pch transistor and a first Nch transistor connected in series between the first potential and the third potential, a second Pch transistor having a drain node thereof connected to a gate node of the first Nch transistor, and a second Nch transistor having a source node thereof connected to a source node of the second Pch transistor, wherein the drain node and gate node of the second Nch transistor are fixed to the second potential and the first potential, respectively.
摘要翻译：由第一电位，低于第一电位的第二电位和低于第二电位的第三电位驱动的半导体器件包括串联连接在第一电位和第三电位之间的第一Pch晶体管和第一N沟道晶体管，具有连接到第一N沟晶体管的栅极节点的漏极节点的第二Pch晶体管和其源极节点连接到第二Pch晶体管的源极节点的第二N沟道晶体管，其中漏极节点和栅极节点第二Nch晶体管分别被固定到第二电位和第一电位。

3. 发明申请

US20060236206A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060236206A1
公开(公告)日：2006-10-19
申请号：US11270533
申请日：2005-11-10
申请人： Shuzo Otsuka , Kuninori Kawabata , Toshikazu Nakamura , Akira Kikutake
发明人： Shuzo Otsuka , Kuninori Kawabata , Toshikazu Nakamura , Akira Kikutake
IPC分类号： G11C29/00
CPC分类号： G06F11/1032 , G11C7/1006 , G11C7/1027
摘要： In a semiconductor memory device having an error-correction function: one or both of a portion of a set of data bits and a set of parity bits based on the set of data bits are held, where the set of data bits and the set of parity bits constitute a code for error correction and are written in memory cells in the leading write cycle in a burst write operation. The set of parity bits written in memory cells in the leading write cycle is updated in the final write cycle on the basis of the portion of the set of data bits and/or the set of parity bits, and another set of data bits required to be written in the final write cycle in the memory cells at the address at which the above portion is written in the leading write cycle.
摘要翻译：在具有纠错功能的半导体存储器件中，保持一组数据位的一部分和基于该数据位组的一组奇偶校验位，其中数据位集合和奇偶校验位构成用于纠错的代码，并且在突发写入操作中以前导写入周期写入存储器单元。基于数据位组和/或奇偶校验位集合的部分，在最终写入周期中更新写入存储器单元中的前导写周期中的奇偶校验位集合，以及另一组数据位在上一部分写入前导写周期的地址处的存储单元中写入最终写周期。

4. 发明授权

US07327627B2 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US07327627B2
公开(公告)日：2008-02-05
申请号：US11452379
申请日：2006-06-14
申请人： Kuninori Kawabata , Shuzo Otsuka
发明人： Kuninori Kawabata , Shuzo Otsuka
IPC分类号： G11C7/00
CPC分类号： G11C11/40622 , G11C8/18 , G11C11/406
摘要： Out of memory blocks arranged in one direction, the memory blocks arranged at both ends are included in a partial area. Since part of control circuits operating the memory blocks arranged at the both ends are not shared by the other memory blocks, switching circuits connecting these control circuits to the memory blocks are constantly settable to an ON state. Since ON/OFF control of the switching circuits is not necessary, power consumption required for accessing the memory blocks arranged at the both ends is smaller than that required for accessing the other memory blocks. Therefore, including the memory blocks arranged at the both ends in a partial area makes it possible to reduce power consumption during a partial refresh mode (standby current).
摘要翻译：在一个方向上布置的存储器块不足，布置在两端的存储块被包括在部分区域中。由于设置在两端的存储块的一部分控制电路不被其他存储块共享，所以将这些控制电路连接到存储块的开关电路始终可设定为导通状态。由于不需要开关电路的ON / OFF控制，所以访问布置在两端的存储块所需的功耗小于访问其他存储块所需的功耗。因此，包括布置在部分区域的两端的存储块使得可以在部分刷新模式（待机电流）期间减少功耗。

5. 发明申请

US20060285405A1 Semiconductor memory and operation method for same 失效
公开(公告)号：US20060285405A1
公开(公告)日：2006-12-21
申请号：US11508927
申请日：2006-08-24
申请人： Kuninori Kawabata , Shuzo Otsuka
发明人： Kuninori Kawabata , Shuzo Otsuka
IPC分类号： G11C7/00
CPC分类号： G11C11/40615 , G11C7/12 , G11C11/406 , G11C11/4094 , G11C2211/4067
摘要： A bit line resetting signal is supplied to the gate of an nMOS transistor (or a precharge circuit) which connects a bit line with a precharge voltage line. The high-level voltage of the bit line resetting signal is retained at a first voltage during the precharge operation after a refresh operation, and is retained at a second voltage higher than the first voltage during the precharge operation after an access operation. In the precharge operation after the refresh operation, therefore, the second voltage is not used so that the current consumption of the generating circuit of the second voltage is reduced. Thus, it is possible to reduce the current consumption (or the standby current) during the standby period for which the internal refresh requests continuously occur.

6. 发明授权

US07827463B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07827463B2
公开(公告)日：2010-11-02
申请号：US11270533
申请日：2005-11-10
申请人： Shuzo Otsuka , Kuninori Kawabata , Toshikazu Nakamura , Akira Kikutake
发明人： Shuzo Otsuka , Kuninori Kawabata , Toshikazu Nakamura , Akira Kikutake
IPC分类号： H03M13/00
CPC分类号： G06F11/1032 , G11C7/1006 , G11C7/1027
摘要： In a semiconductor memory device having an error-correction function: one or both of a portion of a set of data bits and a set of parity bits based on the set of data bits are held, where the set of data bits and the set of parity bits constitute a code for error correction and are written in memory cells in the leading write cycle in a burst write operation. The set of parity bits written in memory cells in the leading write cycle is updated in the final write cycle on the basis of the portion of the set of data bits and/or the set of parity bits, and another set of data bits required to be written in the final write cycle in the memory cells at the address at which the above portion is written in the leading write cycle.
摘要翻译：在具有纠错功能的半导体存储器件中，保持一组数据位的一部分和基于该数据位组的一组奇偶校验位，其中数据位集合和奇偶校验位构成用于纠错的代码，并且在突发写入操作中以前导写入周期写入存储器单元。基于数据位组和/或奇偶校验位集合的部分，在最终写入周期中更新写入存储器单元中的前导写周期中的奇偶校验位集合，以及另一组数据位在上一部分写入前导写周期的地址处的存储单元中写入最终写周期。

7. 发明申请

US20060239106A1 Semiconductor memory 有权
标题翻译：半导体存储器
公开(公告)号：US20060239106A1
公开(公告)日：2006-10-26
申请号：US11452379
申请日：2006-06-14
申请人： Kuninori Kawabata , Shuzo Otsuka
发明人： Kuninori Kawabata , Shuzo Otsuka
IPC分类号： G11C8/00
CPC分类号： G11C11/40622 , G11C8/18 , G11C11/406
摘要： Out of memory blocks arranged in one direction, the memory blocks arranged at both ends are included in a partial area. Since part of control circuits operating the memory blocks arranged at the both ends are not shared by the other memory blocks, switching circuits connecting these control circuits to the memory blocks are constantly settable to an ON state. Since ON/OFF control of the switching circuits is not necessary, power consumption required for accessing the memory blocks arranged at the both ends is smaller than that required for accessing the other memory blocks. Therefore, including the memory blocks arranged at the both ends in a partial area makes it possible to reduce power consumption during a partial refresh mode (standby current).
摘要翻译：在一个方向上布置的存储器块不足，布置在两端的存储块被包括在部分区域中。由于设置在两端的存储块的一部分控制电路不被其他存储块共享，所以将这些控制电路连接到存储块的开关电路始终可设定为导通状态。由于不需要开关电路的ON / OFF控制，所以访问布置在两端的存储块所需的功耗小于访问其他存储块所需的功耗。因此，包括布置在部分区域的两端的存储块使得可以在部分刷新模式（待机电流）期间减少功耗。

8. 发明授权

US07548468B2 Semiconductor memory and operation method for same 失效
标题翻译：半导体存储器及其操作方法相同
公开(公告)号：US07548468B2
公开(公告)日：2009-06-16
申请号：US11508927
申请日：2006-08-24
申请人： Kuninori Kawabata , Shuzo Otsuka
发明人： Kuninori Kawabata , Shuzo Otsuka
IPC分类号： G11C7/00
CPC分类号： G11C11/40615 , G11C7/12 , G11C11/406 , G11C11/4094 , G11C2211/4067
摘要： A bit line resetting signal is supplied to the gate of an nMOS transistor (or a precharge circuit) which connects a bit line with a precharge voltage line. The high-level voltage of the bit line resetting signal is retained at a first voltage during the precharge operation after a refresh operation, and is retained at a second voltage higher than the first voltage during the precharge operation after an access operation. In the precharge operation after the refresh operation, therefore, the second voltage is not used so that the current consumption of the generating circuit of the second voltage is reduced. Thus, it is possible to reduce the current consumption (or the standby current) during the standby period for which the internal refresh requests continuously occur.
摘要翻译：位线复位信号被提供给连接位线与预充电电压线的nMOS晶体管（或预充电电路）的栅极。在刷新操作之后的预充电操作期间，位线复位信号的高电平电压保持在第一电压，并且在访问操作之后的预充电操作期间被保持在高于第一电压的第二电压。因此，在刷新操作之后的预充电操作中，不使用第二电压，使得第二电压的发电电路的电流消耗减小。因此，可以在不断发生内部刷新请求的待机期间减少电流消耗（或待机电流）。

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