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1. 发明授权

US06222792B1 Phase control circuit, semiconductor device and semiconductor memory 有权
公开(公告)号：US06222792B1
公开(公告)日：2001-04-24
申请号：US09666598
申请日：2000-09-20
申请人： Satoru Hanzawa , Takeshi Sakata , Osamu Nagashima
发明人： Satoru Hanzawa , Takeshi Sakata , Osamu Nagashima
IPC分类号： G11C800
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/22 , G11C7/222
摘要： A phase control circuit comprises a plurality of fixed delay circuits (200-0 through 200-5) which assign different predetermined delay times to a first clock signal (BDA1) respectively, a detection circuit (201) which receives clock signals outputted from the plurality of fixed delay circuits and a second clock signal (PCLK) different in phase from the first clock signal therein and generates detected signals (202) represented in a plurality of bits each corresponding to the difference in phase between the first clock signal and the second clock signal, and a variable delay circuit (200-6) which gives a delay in the phase difference corresponding to each of the detected signals to a third clock signal (BDA2).

2. 发明授权

US06335901B1 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06335901B1
公开(公告)日：2002-01-01
申请号：US09531467
申请日：2000-03-20
申请人： Sadayuki Morita , Takeshi Sakata , Satoru Hanzawa , Takahiro Sonoda , Haruko Tadokoro , Hiroshi Ichikawa , Osamu Nagashima
发明人： Sadayuki Morita , Takeshi Sakata , Satoru Hanzawa , Takahiro Sonoda , Haruko Tadokoro , Hiroshi Ichikawa , Osamu Nagashima
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/1045 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： An SDRAM has its operation mode selected to be the SDR mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the DDR mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock signal.
摘要翻译：响应于外部端子（OPT）的第一状态，SDRAM将其操作模式选择为SDR模式，从而释放已经从存储器读出的数据，以响应于由时钟产生的时钟信号再生电路具有响应于外部端子（OPT）的第二状态而比较电路的输入和输出的相位或选择为DDR模式的功能，从而释放从响应于与外部时钟信号同步的由时钟信号发生电路产生的时钟信号，存储器垫。

3. 发明授权

US06205086B1 Phase control circuit, semiconductor device and semiconductor memory 有权
标题翻译：相位控制电路，半导体器件和半导体存储器
公开(公告)号：US06205086B1
公开(公告)日：2001-03-20
申请号：US09560724
申请日：2000-04-28
申请人： Satoru Hanzawa , Takeshi Sakata , Osamu Nagashima
发明人： Satoru Hanzawa , Takeshi Sakata , Osamu Nagashima
IPC分类号： G11C800
CPC分类号： G11C7/1057 , G11C7/1051 , G11C7/22 , G11C7/222
摘要： A phase control circuit comprises a plurality of fixed delay circuits (200-0 through 200-5) which assign different predetermined delay times to a first clock signal (BDA1) respectively, a detection circuit (201) which receives clock signals outputted from the plurality of fixed delay circuits and a second clock signal (PCLK) different in phase from the first clock signal therein and generates detected signals (202) represented in a plurality of bits each corresponding to the difference in phase between the first clock signal and the second clock signal, and a variable delay circuit (200-6) which gives a delay in the phase difference corresponding to each of the detected signals to a third clock signal (BDA2).
摘要翻译：相位控制电路包括分别向第一时钟信号（BDA1）分配不同的预定延迟时间的多个固定延迟电路（200-0至200-5）;接收从多个时钟信号输出的时钟信号的检测电路（201）的固定延迟电路和与其中的第一时钟信号不同的第二时钟信号（PCLK），并产生以多个位表示的检测信号（202），每个位对应于第一时钟信号和第二时钟之间的相位差信号和可变延迟电路（200-6），其将与每个检测到的信号相对应的相位差延迟到第三时钟信号（BDA2）。

4. 发明授权

US06754133B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06754133B2
公开(公告)日：2004-06-22
申请号：US10231286
申请日：2002-08-30
申请人： Sadayuki Morita , Takeshi Sakata , Satoru Hanzawa , Takahiro Sonoda , Haruko Tadokoro , Hiroshi Ichikawa , Osamu Nagashima
发明人： Sadayuki Morita , Takeshi Sakata , Satoru Hanzawa , Takahiro Sonoda , Haruko Tadokoro , Hiroshi Ichikawa , Osamu Nagashima
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/1045 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： A Synchronous Dynamic Random Access Memory (SDRAM) has its operation mode selected to be the Single Data Rate (SDR) mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the Double Data Rate (DDR) mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock. In the SDR mode, data are transferred via data lines in SDRAM unidirectionally and in the DDR mode, data are transferred via the data lines bidirectionally.
摘要翻译：响应于外部终端（OPT）的第一状态，同步动态随机存取存储器（SDRAM）的操作模式选择为单数据速率（SDR）模式，从而释放从存储器中读出的数据响应于具有比较电路的输入和输出的相位或者被选择为双倍数据速率（DDR）模式的功能的时钟再生电路产生的时钟信号响应于第二状态外部端子（OPT），从而释放已经从存储器垫读出的数据，响应于与外部时钟同步的时钟信号产生电路产生的时钟信号。在SDR模式下，数据通过SDRAM中的数据线单向传输，在DDR模式下，数据通过数据线双向传输。

5. 发明授权

US06549484B2 Semiconductor device 有权
公开(公告)号：US06549484B2
公开(公告)日：2003-04-15
申请号：US09964669
申请日：2001-09-28
申请人： Sadayuki Morita , Takeshi Sakata , Satoru Hanzawa , Takahiro Sonoda , Haruko Tadokoro , Hiroshi Ichikawa , Osamu Nagashima
发明人： Sadayuki Morita , Takeshi Sakata , Satoru Hanzawa , Takahiro Sonoda , Haruko Tadokoro , Hiroshi Ichikawa , Osamu Nagashima
IPC分类号： G11C800
CPC分类号： G11C7/1066 , G11C7/1045 , G11C7/1072 , G11C7/22 , G11C7/222 , G11C11/4076
摘要： An SDRAM has its operation mode selected to be the SDR mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the DDR mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock signal.

6. 发明授权

US07619911B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07619911B2
公开(公告)日：2009-11-17
申请号：US10579911
申请日：2003-11-21
申请人： Satoru Hanzawa , Junji Shigeta , Shinichiro Kimura , Takeshi Sakata , Riichiro Takemura , Kazuhiko Kajigaya
发明人： Satoru Hanzawa , Junji Shigeta , Shinichiro Kimura , Takeshi Sakata , Riichiro Takemura , Kazuhiko Kajigaya
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C15/043
摘要： In a memory array structured of memory cells using a storage circuit STC and a comparator CP, either one electrode of a source electrode or a drain electrode of a transistor, whose gate electrode is connected to a search line, of a plurality of transistors structuring the comparator CP is connected to a match line HMLr precharged to a high voltage. Further, a match detector MDr is arranged on a match line LMLr precharged to a low voltage to discriminate a comparison signal voltage generated at the match line according to the comparison result of data. According to such memory array structure and operation, comparison operation can be performed at low power and at high speed while influence of search-line noise is avoided in a match line pair. Therefore, a low power content addressable memory which allows search operation at high speed can be realized.
摘要翻译：在使用存储电路STC和比较器CP的存储器单元构成的存储器阵列中，将栅电极连接到搜索线的晶体管的源电极或漏电极的一个电极，构成比较器CP连接到预充电到高电压的匹配线HMLr。此外，匹配检测器MDr布置在预充电到低电压的匹配线LMLr上，以根据数据的比较结果来识别在匹配线处产生的比较信号电压。根据这种存储器阵列结构和操作，可以在低功率和高速度下执行比较操作，同时在匹配线对中避免搜索线噪声的影响。因此，可以实现允许高速搜索操作的低功率内容可寻址存储器。

7. 发明授权

US07505296B2 Ternary content addressable memory with block encoding 失效
标题翻译：具有块编码的三元内容可寻址存储器
公开(公告)号：US07505296B2
公开(公告)日：2009-03-17
申请号：US11877310
申请日：2007-10-23
申请人： Satoru Hanzawa , Takeshi Sakata , Kazuhiko Kajigaya
发明人： Satoru Hanzawa , Takeshi Sakata , Kazuhiko Kajigaya
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C15/043
摘要： The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value ‘1’; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.
摘要翻译：有效存储范围指定的IP地址，以减少必要条目的数量，从而提高TCAM的存储容量。本发明的代表性手段是：存储信息（条目）和输入信息（比较信息或搜索关键字）是公共块码，使得任何位必须是逻辑值“1”; 匹配线是分层结构的，并且存储器单元被布置在多个子匹配线和多条搜索线的交叉点处; 此外，子匹配线分别通过子匹配检测器连接到主匹配线，并且主匹配检测器被布置在主匹配线上。

8. 发明申请

US20080089137A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20080089137A1
公开(公告)日：2008-04-17
申请号：US11873254
申请日：2007-10-16
申请人： Satoru HANZAWA , Takeshi Sakata
发明人： Satoru HANZAWA , Takeshi Sakata
IPC分类号： G11C7/10
CPC分类号： G11C29/787 , G11C7/14 , G11C11/1673 , G11C11/1693
摘要： A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.
摘要翻译：虚拟单元包括：多个第一存储单元MC，用于存储多个字线WR0至WR7与多个第一数据线D 0至D 7之间的交点处的“1”或“0” 多个用于存储“1”或“0”的第一虚拟单元MCH，布置在字线WR0至WR7和第一虚拟数据线之间的交点处，以及多个第二虚拟单元MCL，用于存储“0” “，布置在字线WR0至WR7之间的交点处和第二伪数据线DD 1之间。

9. 发明授权

US06946704B2 Semiconductor memory cell and method of forming same 有权
标题翻译：半导体存储单元及其形成方法
公开(公告)号：US06946704B2
公开(公告)日：2005-09-20
申请号：US10808510
申请日：2004-03-25
申请人： Hideyuki Matsuoka , Kiyoo Itoh , Motoyasu Terao , Satoru Hanzawa , Takeshi Sakata
发明人： Hideyuki Matsuoka , Kiyoo Itoh , Motoyasu Terao , Satoru Hanzawa , Takeshi Sakata
IPC分类号： G11C13/00 , H01L27/10 , H01L27/105 , H01L27/24 , H01L45/00 , H01L29/26
CPC分类号： H01L27/2454 , G11C13/0004 , G11C2213/79 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/144
摘要： A semiconductor memory cell and forming method thereof utilizes a vertical select transistor to eliminate the problem of a large cell surface area in memory cells of the related art utilizing phase changes. A memory cell with a smaller surface area than the DRAM device of the related art is achieved by the present invention. Besides low power consumption during read operation, the invention also provides phase change memory having low power consumption even during write operation. Phase change memory also has stable read-out operation.
摘要翻译：半导体存储单元及其形成方法利用垂直选择晶体管来消除利用相位变化的现有技术的存储单元中的大的单元表面积的问题。通过本发明实现了具有比现有技术的DRAM器件更小的表面积的存储单元。除了读取操作中的低功耗之外，本发明还提供即使在写入操作期间具有低功耗的相变存储器。相变存储器也具有稳定的读出操作。

10. 发明授权

US06862232B2 Semiconductor device 失效
标题翻译：半导体器件
公开(公告)号：US06862232B2
公开(公告)日：2005-03-01
申请号：US10726658
申请日：2003-12-04
申请人： Satoru Hanzawa , Takeshi Sakata
发明人： Satoru Hanzawa , Takeshi Sakata
IPC分类号： G11C11/15 , G11C5/00 , G11C7/00 , G11C11/00 , G11C11/16 , G11C11/34 , H01L27/22 , H01L31/0328
CPC分类号： G11C29/787 , G11C7/14 , G11C11/1673 , G11C11/1693
摘要： A dummy cell includes a plurality of first memory cells MC for storing “1” or “0”, arranged at points of intersection between a plurality of word lines WR0 to WR7 and a plurality of first data lines D0 to D7, a plurality of first dummy cells MCH for storing “1” or “0”, arranged at points of intersection between the word lines WR0 to WR7 and a first dummy data line, and a plurality of second dummy cells MCL for storing “0”, arranged at points of intersection between the word lines WR0 to WR7 and a second dummy data line DD1.
摘要翻译：虚拟单元包括多个用于存储“1”或“0”的第一存储单元MC，其布置在多个字线WR0至WR7与多个第一数据线D0至D7之间的交点处，多个第一用于存储“1”或“0”的虚拟单元MCH，布置在字线WR0至WR7和第一虚拟数据线之间的交点处，以及多个第二虚拟单元MCL，用于存储“0” 字线WR0〜WR7与第二伪数据线DD1的交点。

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