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1. 发明授权

US07619911B2 Semiconductor integrated circuit device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US07619911B2
公开(公告)日：2009-11-17
申请号：US10579911
申请日：2003-11-21
申请人： Satoru Hanzawa , Junji Shigeta , Shinichiro Kimura , Takeshi Sakata , Riichiro Takemura , Kazuhiko Kajigaya
发明人： Satoru Hanzawa , Junji Shigeta , Shinichiro Kimura , Takeshi Sakata , Riichiro Takemura , Kazuhiko Kajigaya
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C15/043
摘要： In a memory array structured of memory cells using a storage circuit STC and a comparator CP, either one electrode of a source electrode or a drain electrode of a transistor, whose gate electrode is connected to a search line, of a plurality of transistors structuring the comparator CP is connected to a match line HMLr precharged to a high voltage. Further, a match detector MDr is arranged on a match line LMLr precharged to a low voltage to discriminate a comparison signal voltage generated at the match line according to the comparison result of data. According to such memory array structure and operation, comparison operation can be performed at low power and at high speed while influence of search-line noise is avoided in a match line pair. Therefore, a low power content addressable memory which allows search operation at high speed can be realized.
摘要翻译：在使用存储电路STC和比较器CP的存储器单元构成的存储器阵列中，将栅电极连接到搜索线的晶体管的源电极或漏电极的一个电极，构成比较器CP连接到预充电到高电压的匹配线HMLr。此外，匹配检测器MDr布置在预充电到低电压的匹配线LMLr上，以根据数据的比较结果来识别在匹配线处产生的比较信号电压。根据这种存储器阵列结构和操作，可以在低功率和高速度下执行比较操作，同时在匹配线对中避免搜索线噪声的影响。因此，可以实现允许高速搜索操作的低功率内容可寻址存储器。

2. 发明申请

US20070274144A1 Semiconductor Integrated Circuit Device 失效
标题翻译：半导体集成电路器件
公开(公告)号：US20070274144A1
公开(公告)日：2007-11-29
申请号：US10579911
申请日：2003-11-21
申请人： Satoru Hanzawa , Junji Shigeta , Shinichiro Kimura , Takeshi Sakata , Riichiro Takemura , Kazuhiko Kajigaya
发明人： Satoru Hanzawa , Junji Shigeta , Shinichiro Kimura , Takeshi Sakata , Riichiro Takemura , Kazuhiko Kajigaya
IPC分类号： G11C7/00
CPC分类号： G11C15/04 , G11C15/043
摘要： In a memory array structured of memory cells using a storage circuit STC and a comparator CP, either one electrode of a source electrode or a drain electrode of a transistor, whose gate electrode is connected to a search line, of a plurality of transistors structuring the comparator CP is connected to a match line HMLr precharged to a high voltage. Further, a match detector MDr is arranged on a match line LMLr precharged to a low voltage to discriminate a comparison signal voltage generated at the match line according to the comparison result of data. According to such memory array structure and operation, comparison operation can be performed at low power and at high speed while influence of search-line noise is avoided in a match line pair. Therefore, a low power content addressable memory which allows search operation at high speed can be realized.
摘要翻译：在使用存储电路STC和比较器CP的存储器单元构成的存储器阵列中，将栅电极连接到搜索线的晶体管的源电极或漏电极的一个电极，构成比较器CP连接到预充电到高电压的匹配线HMLr。此外，匹配检测器MDr布置在预充电到低电压的匹配线LMLr上，以根据数据的比较结果来识别在匹配线处产生的比较信号电压。根据这种存储器阵列结构和操作，可以在低功率和高速度下执行比较操作，同时在匹配线对中避免搜索线噪声的影响。因此，可以实现允许高速搜索操作的低功率内容可寻址存储器。

3. 发明授权

US07505299B2 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US07505299B2
公开(公告)日：2009-03-17
申请号：US11976531
申请日：2007-10-25
申请人： Riichiro Takemura , Satoru Akiyama , Satoru Hanzawa , Tomonori Sekiguchi , Kazuhiko Kajigaya
发明人： Riichiro Takemura , Satoru Akiyama , Satoru Hanzawa , Tomonori Sekiguchi , Kazuhiko Kajigaya
IPC分类号： G11C5/06 , G11C11/24 , G11C7/02 , G11C8/00
CPC分类号： G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10814 , H01L27/10873
摘要： A semiconductor memory device that can achieve high-speed operation or that is highly integrated and simultaneously can achieve high-speed operation is provided. Transistors are disposed on both sides of diffusion layer regions to which capacitor for storing information is connected and other diffusion layer region of each transistor is connected to the same bit line. When access to a memory cell is made, two transistors are activated and the information is read. When writing operation to the memory cell is carried out, two transistors are used and electric charges are written to the capacitor.
摘要翻译：提供了可以实现高速操作或高度集成并同时实现高速操作的半导体存储器件。晶体管设置在扩散层区域的两侧，用于存储信息的电容器被连接到，并且每个晶体管的其它扩散层区域连接到相同的位线。当访问存储器单元时，两个晶体管被激活并且读取该信息。当对存储单元进行写操作时，使用两个晶体管，并将电荷写入电容器。

4. 发明申请

US20060158924A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20060158924A1
公开(公告)日：2006-07-20
申请号：US11280170
申请日：2005-11-17
申请人： Tomonori Sekiguchi , Satoru Akiyama , Riichiro Takemura , Satoru Hanzawa , Kazuhiko Kajigaya
发明人： Tomonori Sekiguchi , Satoru Akiyama , Riichiro Takemura , Satoru Hanzawa , Kazuhiko Kajigaya
IPC分类号： G11C11/24
CPC分类号： G11C11/4094 , G11C7/12 , G11C7/18 , G11C11/4074 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/10882
摘要： A write command is inputted from an outside, voltages of bit lines become VDL and VSS, and a voltage in accordance with a threshold voltage (LVT: low threshold voltage, MVT: mid threshold voltage, HVT: high threshold voltage) of a memory cell transistor is written into a storage node of a capacitor via the memory cell transistor. Thereafter, when a plate line connected to a plate side of the capacitor is driven from voltage VPL to voltage VPH and the voltage of the storage node is increased due to coupling, the voltage VDL of the bit line is reduced to the voltage VDP, and the voltage excessively written into the storage node is reduced in accordance with a level of a threshold voltage of the memory cell transistor, thereby reducing a variation in the voltage of the storage node due to a variation in the threshold voltage.
摘要翻译：从外部输入写命令，位线的电压变为VDL和VSS，以及根据存储单元的阈值电压（LVT：低阈值电压，MVT：中间阈值电压，HVT：高阈值电压）的电压晶体管经由存储单元晶体管写入电容器的存储节点。此后，当连接到电容器的板侧的板线从电压VPL驱动到电压VPH并且存储节点的电压由于耦合而增加时，位线的电压VDL被降低到电压VDP，并且根据存储单元晶体管的阈值电压的电平降低过度写入存储节点的电压，从而减小由于阈值电压的变化引起的存储节点的电压的变化。

5. 发明申请

US20050265068A1 Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US20050265068A1
公开(公告)日：2005-12-01
申请号：US11134476
申请日：2005-05-23
申请人： Riichiro Takemura , Satoru Akiyama , Satoru Hanzawa , Tomonori Sekiguchi , Kazuhiko Kajigaya
发明人： Riichiro Takemura , Satoru Akiyama , Satoru Hanzawa , Tomonori Sekiguchi , Kazuhiko Kajigaya
IPC分类号： H01L27/108 , G11C11/24 , G11C11/405 , G11C11/4097 , H01L21/8242 , H01L27/02
CPC分类号： G11C11/405 , G11C11/4097 , H01L27/0207 , H01L27/108 , H01L27/10814 , H01L27/10873
摘要： A semiconductor memory device that can achieve high-speed operation or that is highly integrated and simultaneously can achieve high-speed operation is provided. Transistors are disposed on both sides of diffusion layer regions to which capacitor for storing information is connected and other diffusion layer region of each transistor is connected to the same bit line. When access to a memory cell is made, two transistors are activated and the information is read. When writing operation to the memory cell is carried out, two transistors are used and electric charges are written to the capacitor.
摘要翻译：提供了可以实现高速操作或高度集成并同时实现高速操作的半导体存储器件。晶体管设置在扩散层区域的两侧，用于存储信息的电容器被连接到，并且每个晶体管的其它扩散层区域连接到相同的位线。当访问存储器单元时，两个晶体管被激活并且读取该信息。当对存储单元进行写操作时，使用两个晶体管，并将电荷写入电容器。

6. 发明申请

US20090116309A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20090116309A1
公开(公告)日：2009-05-07
申请号：US12348306
申请日：2009-01-04
申请人： SATORU HANZAWA , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Kazuhiko Kajigaya
发明人： SATORU HANZAWA , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Kazuhiko Kajigaya
IPC分类号： G11C7/00
CPC分类号： G11C7/1027 , G11C7/1012 , G11C7/1048 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C7/22 , G11C11/4076 , G11C11/4091 , G11C11/4093 , G11C11/4094 , G11C11/4096 , G11C29/028 , G11C2207/002
摘要： A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read enable signals RD1, RD2 is provided in each sub-amplifier SAMP. The read enable signals RD1, RD2 are generated at timings corresponding to the number of cycles in burst read operation under control of the timing controller. Current in the current control circuit IC is set to be large by the RD1 in burst read operation cycle just after activation of a memory bank, while current in the current control circuit IC is set to be small by the RD2 in the next and subsequent burst read cycles. Accordingly, expansion of an operation margin or reduction of power consumption can be realized in a semiconductor device including a semiconductor memory such as a DRAM.
摘要翻译：提供了一种列电路，其将从读出放大器阵列SAA读取的信号放大到子放大器SAMP中的本地输入/输出线LIO，以将放大的信号传送到主输入/输出线MIO。在每个子放大器SAMP中提供可以根据读使能信号RD1，RD2设置两种电流之一的电流控制电路IC。在定时控制器的控制下，在脉冲串读取操作中的周期数对应的定时产生读使能信号RD1，RD2。电流控制电路IC中的电流在刚刚激活存储体之后的脉冲串读取操作周期中的RD1被设置为较大，而当前控制电路IC中的电流在下一个和随后的脉冲串中被RD2设置得较小读周期。因此，可以在包括诸如DRAM的半导体存储器的半导体器件中实现操作余量的扩大或功率消耗的降低。

7. 发明授权

US07489588B2 Semiconductor memory device having a main amplifier equipped with a current control circuit in a burst read operation 失效
标题翻译：具有在突发读取操作中配备有电流控制电路的主放大器的半导体存储器件
公开(公告)号：US07489588B2
公开(公告)日：2009-02-10
申请号：US11924353
申请日：2007-10-25
申请人： Satoru Hanzawa , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Kazuhiko Kajigaya
发明人： Satoru Hanzawa , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Kazuhiko Kajigaya
IPC分类号： G11C7/08
CPC分类号： G11C7/1027 , G11C7/1012 , G11C7/1048 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C7/22 , G11C11/4076 , G11C11/4091 , G11C11/4093 , G11C11/4094 , G11C11/4096 , G11C29/028 , G11C2207/002
摘要： A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read enable signals RD1, RD2 is provided in each sub-amplifier SAMP. The read enable signals RD1, RD2 are generated at timings corresponding to the number of cycles in burst read operation under control of the timing controller. Current in the current control circuit IC is set to be large by the RD1 in burst read operation cycle just after activation of a memory bank, while current in the current control circuit IC is set to be small by the RD2 in the next and subsequent burst read cycles. Accordingly, expansion of an operation margin or reduction of power consumption can be realized in a semiconductor device including a semiconductor memory such as a DRAM.
摘要翻译：提供了一种列电路，其将从读出放大器阵列SAA读取的信号放大到子放大器SAMP中的本地输入/输出线LIO，以将放大的信号传送到主输入/输出线MIO。在每个子放大器SAMP中提供可以根据读使能信号RD1，RD2设置两种电流之一的电流控制电路IC。在定时控制器的控制下，在脉冲串读取操作中的周期数对应的定时产生读使能信号RD1，RD2。电流控制电路IC中的电流在刚刚激活存储体之后的脉冲串读取操作周期中的RD1被设置为较大，而当前控制电路IC中的电流在下一个和随后的脉冲串中被RD2设置得较小读周期。因此，可以在包括诸如DRAM的半导体存储器的半导体器件中实现操作余量的扩大或功率消耗的降低。

8. 发明授权

US07304910B1 Semiconductor memory device with sub-amplifiers having a variable current source 有权
标题翻译：具有具有可变电流源的子放大器的半导体存储器件
公开(公告)号：US07304910B1
公开(公告)日：2007-12-04
申请号：US11467793
申请日：2006-08-28
申请人： Satoru Hanzawa , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Kazuhiko Kajigaya
发明人： Satoru Hanzawa , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Kazuhiko Kajigaya
IPC分类号： G11C8/18 , G11C5/14
CPC分类号： G11C7/1027 , G11C7/1012 , G11C7/1048 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C7/22 , G11C11/4076 , G11C11/4091 , G11C11/4093 , G11C11/4094 , G11C11/4096 , G11C29/028 , G11C2207/002
摘要： A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read enable signals RD1, RD2 is provided in each sub-amplifier SAMP. The read enable signals RD1, RD2 are generated at timings corresponding to the number of cycles in burst read operation under control of the timing controller. Current in the current control circuit IC is set to be large by the RD1 in burst read operation cycle just after activation of a memory bank, while current in the current control circuit IC is set to be small by the RD2 in the next and subsequent burst read cycles. Accordingly, expansion of an operation margin or reduction of power consumption can be realized in a semiconductor device including a semiconductor memory such as a DRAM.
摘要翻译：提供了一种列电路，其将从读出放大器阵列SAA读取的信号放大到子放大器SAMP中的本地输入/输出线LIO，以将放大的信号传送到主输入/输出线MIO。在每个子放大器SAMP中设置有能够根据读使能信号RD1，RD2设定两种电流之一的电流控制电路IC。在定时控制器的控制下，在与脉冲串读取操作中的周期数相对应的定时，生成读使能信号RD 1，RD 2。电流控制电路IC中的电流在刚刚激活存储体之后的脉冲串读取操作周期中的RD 1被设置为较大，而当前控制电路IC中的电流被下一个的RD 2设置得较小时，随后的突发读取周期。因此，可以在包括诸如DRAM的半导体存储器的半导体器件中实现操作余量的扩大或功率消耗的降低。

9. 发明授权

US07193884B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US07193884B2
公开(公告)日：2007-03-20
申请号：US11280170
申请日：2005-11-17
申请人： Tomonori Sekiguchi , Satoru Akiyama , Riichiro Takemura , Satoru Hanzawa , Kazuhiko Kajigaya
发明人： Tomonori Sekiguchi , Satoru Akiyama , Riichiro Takemura , Satoru Hanzawa , Kazuhiko Kajigaya
IPC分类号： G11C11/24
CPC分类号： G11C11/4094 , G11C7/12 , G11C7/18 , G11C11/4074 , G11C11/4097 , G11C2211/4013 , H01L27/0207 , H01L27/10882
摘要： A write command is inputted from an outside, voltages of bit lines become VDL and VSS, and a voltage in accordance with a threshold voltage (LVT: low threshold voltage, MVT: mid threshold voltage, HVT: high threshold voltage) of a memory cell transistor is written into a storage node of a capacitor via the memory cell transistor. Thereafter, when a plate line connected to a plate side of the capacitor is driven from voltage VPL to voltage VPH and the voltage of the storage node is increased due to coupling, the voltage VDL of the bit line is reduced to the voltage VDP, and the voltage excessively written into the storage node is reduced in accordance with a level of a threshold voltage of the memory cell transistor, thereby reducing a variation in the voltage of the storage node due to a variation in the threshold voltage.
摘要翻译：从外部输入写命令，位线的电压变为VDL和VSS，以及根据存储单元的阈值电压（LVT：低阈值电压，MVT：中间阈值电压，HVT：高阈值电压）的电压晶体管经由存储单元晶体管写入电容器的存储节点。此后，当连接到电容器的板侧的板线从电压VPL驱动到电压VPH并且存储节点的电压由于耦合而增加时，位线的电压VDL被降低到电压VDP，并且根据存储单元晶体管的阈值电压的电平降低过度写入存储节点的电压，从而减小由于阈值电压的变化引起的存储节点的电压的变化。

10. 发明申请

US20070038919A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20070038919A1
公开(公告)日：2007-02-15
申请号：US11495550
申请日：2006-07-31
申请人： Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Satoru Hanzawa , Kazuhiko Kajigaya
发明人： Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Satoru Hanzawa , Kazuhiko Kajigaya
IPC分类号： G11C29/00
CPC分类号： G06F11/1044 , G11C2029/0409
摘要： A semiconductor memory device capable of achieving a sufficient operating margin without increasing an area penalty even in the case of miniaturization is provided. An error correction system composed of a data bit of 64 bits and a check bit of 9 bits is introduced to a memory array such as DRAM, and an error correction code circuit required therein is disposed near a sense amplifier array. In addition to normal memory arrays composed of such memory arrays, a redundant memory array having a sense amplifier array and an error correction code circuit adjacent thereto is provided in a chip. By this means, the error which occurs in the manufacture can be replaced. Also, the error correction code circuit corrects the error at the time of an activate command and stores the check bit at the time of a pre-charge command.
摘要翻译：提供了即使在小型化的情况下也能够实现足够的操作余量而不增加面积损失的半导体存储器件。将由64位的数据位和9位的校验位构成的纠错系统引入到诸如DRAM的存储器阵列中，并且其中需要的纠错码电路设置在读出放大器阵列附近。除了由这种存储器阵列组成的常规存储器阵列之外，在芯片中提供了具有读出放大器阵列和与其相邻的纠错码电路的冗余存储器阵列。通过这种方式，可以更换制造过程中发生的错误。此外，纠错码电路校正了激活命令时的错误，并且在预充电命令时存储检查位。

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