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1. 发明申请

US20050010714A1 Schmoo runtime reduction and dynamic calibration based on a DLL lock value 有权
标题翻译：基于DLL锁定值的Schmoo运行时间减少和动态校准
公开(公告)号：US20050010714A1
公开(公告)日：2005-01-13
申请号：US10737358
申请日：2003-12-16
申请人： Sathish Kumar , Kenneth Kindsfater , Lionel D'Luna , Lakshmanan Ramakrishnan , Anand Pande
发明人： Sathish Kumar , Kenneth Kindsfater , Lionel D'Luna , Lakshmanan Ramakrishnan , Anand Pande
IPC分类号： G11C7/10 , G11C7/22 , G11C5/00
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C2207/2254
摘要： Methods of setting numerically controlled delay lines using step sizes based on a delay locked loop lock value are presented herein. In one embodiment, a method may comprise, for example, one or more of the following: calculating an offset value for at least one NCDL; and interpolating a new offset value for the at least one NCDL, based on a change in a delay locked loop (DLL) output value from a previous DLL output value to a new DLL output value.
摘要翻译：本文给出了使用基于延迟锁定环锁定值的步长设置数控延迟线的方法。在一个实施例中，方法可以包括例如以下中的一个或多个：计算至少一个NCDL的偏移值; 以及基于从先前的DLL输出值到新的DLL输出值的延迟锁定环（DLL）输出值的变化来内插用于所述至少一个NCDL的新的偏移值。

2. 发明授权

US07191279B2 Schmoo runtime reduction and dynamic calibration based on a DLL lock value 有权
标题翻译：基于DLL锁定值的Schmoo运行时间减少和动态校准
公开(公告)号：US07191279B2
公开(公告)日：2007-03-13
申请号：US10737358
申请日：2003-12-16
申请人： Sathish Kumar , Kenneth Kindsfater , Lionel D'Luna , Lakshmanan Ramakrishnan , Anand Pande
发明人： Sathish Kumar , Kenneth Kindsfater , Lionel D'Luna , Lakshmanan Ramakrishnan , Anand Pande
IPC分类号： G06F12/00
CPC分类号： G11C7/1066 , G11C7/1051 , G11C7/1078 , G11C7/1093 , G11C7/22 , G11C7/222 , G11C2207/2254
摘要： Methods of setting numerically controlled delay lines using step sizes based on a delay locked loop lock value are presented herein. In one embodiment, a method may comprise, for example, one or more of the following: calculating an offset value for at least one NCDL; and interpolating a new offset value for the at least one NCDL, based on a change in a delay locked loop (DLL) output value from a previous DLL output value to a new DLL output value.
摘要翻译：本文给出了使用基于延迟锁定环锁定值的步长设置数控延迟线的方法。在一个实施例中，方法可以包括例如以下中的一个或多个：计算至少一个NCDL的偏移值; 以及基于从先前的DLL输出值到新的DLL输出值的延迟锁定环（DLL）输出值的变化来内插用于所述至少一个NCDL的新的偏移值。

3. 发明申请

US20050091470A1 Calculation of gray codes using exhaustive combinations 审中-公开
标题翻译：使用穷举组合计算灰度代码
公开(公告)号：US20050091470A1
公开(公告)日：2005-04-28
申请号：US10715064
申请日：2003-11-17
申请人： Anand Pande
发明人： Anand Pande
IPC分类号： G06F3/00 , G06F5/10 , G06F5/12 , G06F12/00
CPC分类号： G06F5/10 , G06F5/12 , G06F2205/102 , G06F2205/126
摘要： A system and method for generating a sequence of 2D addresses, the sequence having the property of a Hamming distance of one between consecutive addresses and the circular property, where D is an arbitrary integer. A sequence of length equal to the next power of 2, from 2D, is used to determine the sequence of 2D addresses. The sequence of addresses is used in an asynchronous first-in-first-out (FIFO) data structure, which may include, for example, a FIFO memory having a depth D and a code generator coupled to the FIFO memory. The first code sequence may be generated from a second code sequence by removing one or more pairs of mirrored codes of the second code sequence.
摘要翻译：一种用于产生2D地址序列的系统和方法，所述序列具有连续地址之间的汉明距离的属性与循环属性之间，其中D是任意整数。使用从2D开始等于下一次幂2的序列来确定2D地址的序列。地址序列用于异步先入先出（FIFO）数据结构，其可以包括例如具有深度D的FIFO存储器和耦合到FIFO存储器的代码发生器。可以通过去除第二代码序列的一个或多个镜像代码对，从第二代码序列生成第一代码序列。

4. 发明申请

US20090003730A1 Method And System For Processing Video Data In A Multipixel Memory To Memory Compositor 有权
标题翻译：用于处理多内存存储器内存视频数据的方法和系统
公开(公告)号：US20090003730A1
公开(公告)日：2009-01-01
申请号：US11770230
申请日：2007-06-28
申请人： Anand Pande , Darren Neuman
发明人： Anand Pande , Darren Neuman
IPC分类号： G06K9/32
CPC分类号： G06T3/4007
摘要： A method and system for processing video data using multi-pixel scaling in a memory system are provided. The multi-pixel scaling may include reading pixel data for one or more data streams from the memory system into one or more scalers, wherein each of the plurality of data streams includes a plurality of pixels, scaling the pixel via the one or more scalers and outputting the scaled pixels from the one or more scalers. Pixel data may be sequential or parallel. The plurality of scalers may be in parallel, scaling sequential pixel data with independent phase control, or scaling parallel pixel data in substantially equal phase. Pixel data may be transposed, replicated, distributed and aligned prior to reading by scalers, and may be aligned merged and transposed after scaling. Scaling may include interpolation or sub sampling using pixel phase, position, step size and scaler quantities.
摘要翻译：提供了一种用于在存储器系统中使用多像素缩放来处理视频数据的方法和系统。多像素缩放可以包括将来自存储器系统的一个或多个数据流的像素数据读取为一个或多个缩放器，其中多个数据流中的每一个包括多个像素，经由一个或多个缩放器缩放像素，以及从一个或多个定标器输出经缩放的像素。像素数据可以是顺序的或并行的。多个定标器可以是并行的，用独立的相位控制缩放顺序像素数据，或者以基本上相等的相位缩放并行像素数据。像素数据可以在通过缩放器读取之前被转置，复制，分布和对齐，并且可以在缩放之后被对齐合并和转置。缩放可以包括使用像素相位，位置，步长和缩放量的插值或次采样。

5. 发明授权

US08917955B2 Method and system for processing video data in a multipixel memory to memory compositor 有权
标题翻译：用于处理多内存存储器中的视频数据到存储器合成器的方法和系统
公开(公告)号：US08917955B2
公开(公告)日：2014-12-23
申请号：US13454273
申请日：2012-04-24
申请人： Anand Pande , Darren Neuman
发明人： Anand Pande , Darren Neuman
IPC分类号： G06K9/32 , G06T3/40
CPC分类号： G06T3/4007
摘要： A method and system for processing video data using multi-pixel scaling in a memory system are provided. The multi-pixel scaling may include reading pixel data for one or more data streams from the memory system into one or more scalers, wherein each of the plurality of data streams includes a plurality of pixels, scaling the pixel via the one or more scalers and outputting the scaled pixels from the one or more scalers. Pixel data may be sequential or parallel. The plurality of scalers may be in parallel, scaling sequential pixel data with independent phase control, or scaling parallel pixel data in substantially equal phase. Pixel data may be transposed, replicated, distributed and aligned prior to reading by scalers, and may be aligned merged and transposed after scaling. Scaling may include interpolation or sub sampling using pixel phase, position, step size and scaler quantities.
摘要翻译：提供了一种用于在存储器系统中使用多像素缩放来处理视频数据的方法和系统。多像素缩放可以包括将来自存储器系统的一个或多个数据流的像素数据读取为一个或多个缩放器，其中多个数据流中的每一个包括多个像素，经由一个或多个缩放器缩放像素，以及从一个或多个定标器输出经缩放的像素。像素数据可以是顺序的或并行的。多个定标器可以是并行的，用独立的相位控制缩放顺序像素数据，或者以基本上相等的相位缩放并行像素数据。像素数据可以在通过缩放器读取之前被转置，复制，分布和对齐，并且可以在缩放之后被对齐合并和转置。缩放可以包括使用像素相位，位置，步长和缩放量的插值或次采样。

6. 发明授权

US08195008B2 Method and system for processing video data in a multipixel memory to memory compositor 有权
标题翻译：用于处理多内存存储器中的视频数据到存储器合成器的方法和系统
公开(公告)号：US08195008B2
公开(公告)日：2012-06-05
申请号：US11770230
申请日：2007-06-28
申请人： Anand Pande , Darren Neuman
发明人： Anand Pande , Darren Neuman
IPC分类号： G06K9/32
CPC分类号： G06T3/4007
摘要： A method and system for processing video data using multi-pixel scaling in a memory system are provided. The multi-pixel scaling may include reading pixel data for one or more data streams from the memory system into one or more scalers, wherein each of the plurality of data streams includes a plurality of pixels, scaling the pixel via the one or more scalers and outputting the scaled pixels from the one or more scalers. Pixel data may be sequential or parallel. The plurality of scalers may be in parallel, scaling sequential pixel data with independent phase control, or scaling parallel pixel data in substantially equal phase. Pixel data may be transposed, replicated, distributed and aligned prior to reading by scalers, and may be aligned merged and transposed after scaling. Scaling may include interpolation or sub sampling using pixel phase, position, step size and scaler quantities.
摘要翻译：提供了一种用于在存储器系统中使用多像素缩放来处理视频数据的方法和系统。多像素缩放可以包括将来自存储器系统的一个或多个数据流的像素数据读取为一个或多个缩放器，其中多个数据流中的每一个包括多个像素，经由一个或多个缩放器缩放像素，以及从一个或多个定标器输出经缩放的像素。像素数据可以是顺序的或并行的。多个定标器可以是并行的，用独立的相位控制缩放顺序像素数据，或者以基本上相等的相位缩放并行像素数据。像素数据可以在通过缩放器读取之前被转置，复制，分布和对准，并且可以在缩放之后被对齐合并和转置。缩放可以包括使用像素相位，位置，步长和缩放量的插值或次采样。

7. 发明申请

US20120212673A1 Method and System for Processing Video Data in a Multipixel Memory to Memory Compositor 有权
标题翻译：用于处理多内存存储器到存储器复合器中的视频数据的方法和系统
公开(公告)号：US20120212673A1
公开(公告)日：2012-08-23
申请号：US13454273
申请日：2012-04-24
申请人： Anand Pande , Darren Neuman
发明人： Anand Pande , Darren Neuman
IPC分类号： H04N9/74
CPC分类号： G06T3/4007
摘要： A method and system for processing video data using multi-pixel scaling in a memory system are provided. The multi-pixel scaling may include reading pixel data for one or more data streams from the memory system into one or more scalers, wherein each of the plurality of data streams includes a plurality of pixels, scaling the pixel via the one or more scalers and outputting the scaled pixels from the one or more scalers. Pixel data may be sequential or parallel. The plurality of scalers may be in parallel, scaling sequential pixel data with independent phase control, or scaling parallel pixel data in substantially equal phase. Pixel data may be transposed, replicated, distributed and aligned prior to reading by scalers, and may be aligned merged and transposed after scaling. Scaling may include interpolation or sub sampling using pixel phase, position, step size and scaler quantities.
摘要翻译：提供了一种用于在存储器系统中使用多像素缩放来处理视频数据的方法和系统。多像素缩放可以包括将来自存储器系统的一个或多个数据流的像素数据读取为一个或多个缩放器，其中多个数据流中的每一个包括多个像素，经由一个或多个缩放器缩放像素，以及从一个或多个定标器输出经缩放的像素。像素数据可以是顺序的或并行的。多个定标器可以是并行的，用独立的相位控制缩放顺序像素数据，或者以基本上相等的相位缩放并行像素数据。像素数据可以在通过缩放器读取之前被转置，复制，分布和对齐，并且可以在缩放之后被对齐合并和转置。缩放可以包括使用像素相位，位置，步长和缩放量的插值或次采样。

8. 发明授权

US08098929B2 Method and system for automatic correction of flesh-tones (skin-tones) 有权
标题翻译：肉色自动矫正方法及系统（肤色）
公开(公告)号：US08098929B2
公开(公告)日：2012-01-17
申请号：US12038965
申请日：2008-02-28
申请人： Anand Pande , Darren Neuman
发明人： Anand Pande , Darren Neuman
IPC分类号： G06K9/00
CPC分类号： H04N1/628 , G06T7/11 , G06T7/90 , G06T2207/10024 , H04N1/62
摘要： Flesh-tones corrections may be performed to correct color shifts that may occur in transmitted video frames wherein chroma information corresponding to flesh-tone video pixels may be distorted. A target region may be determined based on a determined flesh-tones region within a spatial representation of chroma in video color space, such as Y′CrCb. The flesh-tones correction may utilize one or more methodologies based on an elliptical shape and/or a triangular shape algorithm(s). A video processing system may be utilized to analyze chroma information of received video pixels and/or to perform flesh-tones corrections by shifting the chroma value of received video pixels towards good flesh-tones regions to compensate for possible distortions. The video processing system may perform conversion calculation and/or shift operations dynamically. The video processing system may also utilize lookup tables (LUTs) to convert received chroma values. The LUTs may be programmable to enable modifying and/or updating of the system.
摘要翻译：可以执行肉色调校正，以校正在发送的视频帧中可能发生的颜色偏移，其中对应于肉色视频像素的色度信息可能失真。可以基于在诸如Y'CrCb的视频颜色空间中的色度的空间表示中的确定的肉色区域来确定目标区域。肉色校正可以利用基于椭圆形状和/或三角形形状算法的一种或多种方法。可以使用视频处理系统来分析接收的视频像素的色度信息和/或通过将接收到的视频像素的色度值移向良好的肉色区域来进行肉色调校正，以补偿可能的失真。视频处理系统可以动态地执行转换计算和/或移位操作。视频处理系统还可以利用查找表（LUT）来转换接收的色度值。 LUT可以是可编程的，以能够修改和/或更新系统。

9. 发明授权

US07668983B2 System for designing data structures 失效
标题翻译：用于设计数据结构的系统
公开(公告)号：US07668983B2
公开(公告)日：2010-02-23
申请号：US10692957
申请日：2003-10-24
申请人： Anand Pande
发明人： Anand Pande
IPC分类号： H03M1/22 , H03M7/14 , H03M7/04 , H03K21/00 , G06F17/00 , G06F3/00 , G06F9/26
CPC分类号： G06F5/10 , G06F5/12 , G06F2205/102 , G06F2205/126
摘要： Systems and methods for designing data structures are provided. In one embodiment, an asynchronous first-in-first-out (FIFO) data structure may include, for example, a FIFO memory having a depth d in which d is an integer and a code generator coupled to the FIFO memory. The code generator may provide, for example, a first code sequence of length 2d. The first code sequence may have a circular property and a Hamming length of one for any two consecutive codes of the first code sequence. The first code sequence may be generated from a second code sequence by removing one or more pairs of mirrored codes of the second code sequence.
摘要翻译：提供了设计数据结构的系统和方法。在一个实施例中，异步先入先出（FIFO）数据结构可以包括例如具有深度d的FIFO存储器，其中d是整数，以及耦合到FIFO存储器的代码产生器。代码生成器可以提供例如长度为2d的第一代码序列。对于第一代码序列的任何两个连续代码，第一代码序列可以具有圆形属性和汉明长度1。可以通过去除第二代码序列的一个或多个镜像代码对，从第二代码序列生成第一代码序列。

10. 发明申请

US20060248277A1 System, method, and apparatus for least recently used determination for caches 审中-公开
标题翻译：用于缓存的最近最少使用的确定的系统，方法和装置
公开(公告)号：US20060248277A1
公开(公告)日：2006-11-02
申请号：US11167722
申请日：2005-06-22
申请人： Anand Pande
发明人： Anand Pande
IPC分类号： G06F13/00
CPC分类号： G06F12/123
摘要： Presented herein are system(s), method(s), and apparatus for maintaining a least recently used list for a cache. In one embodiment, there is presented a circuit for storing a list of a plurality of locations for a cache line. The circuit comprises a multiplexer, a plurality of registers, and a plurality of logic circuits. The multiplexer receives an indicator indicating a cache hit or cache miss for the cache line. The multiplexer provides an output identifying the least recently used location if the indicator indicates a cache miss, and an output identifying an accessed location if the indicator indicates a cache hit. The plurality of registers store identifiers identifying particular ones of the plurality of locations. The plurality of registers comprise a most recently used register and a remaining plurality of registers. The plurality of logic circuits correspond respectively to the remaining plurality of registers and respectively control a corresponding plurality of signals. The plurality of signals enable the remaining plurality of registers to shift. The plurality of logic circuits selectively set at least one of the plurality of signals to allow at least one of the remaining plurality of registers to shift, based on comparisons between the output and the identifiers.
摘要翻译：这里呈现的是用于维护用于高速缓存的最近最少使用的列表的系统，方法和装置。在一个实施例中，提供了一种用于存储用于高速缓存行的多个位置的列表的电路。该电路包括多路复用器，多个寄存器和多个逻辑电路。多路复用器接收指示高速缓存命中或高速缓存未命中的指示符。如果指示符指示高速缓存未命中，则多路复用器提供识别最近最少使用的位置的输出，以及如果指示符指示高速缓存命中则识别访问位置的输出。多个寄存器存储识别多个位置中的特定位置的标识符。多个寄存器包括最近使用的寄存器和剩余的多个寄存器。多个逻辑电路分别对应于剩余的多个寄存器并分别控制对应的多个信号。多个信号使剩余的多个寄存器能够移位。多个逻辑电路基于输出和标识符之间的比较选择性地设置多个信号中的至少一个以允许剩余的多个寄存器中的至少一个移位。

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