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1. 发明授权

US07824949B2 Structure and method for flexible sensor array 有权
标题翻译：柔性传感器阵列的结构和方法
公开(公告)号：US07824949B2
公开(公告)日：2010-11-02
申请号：US11963008
申请日：2007-12-21
申请人： Sanjiv Sambandan , William S. Wong , Rene A. Lujan , Scott J. Limb
发明人： Sanjiv Sambandan , William S. Wong , Rene A. Lujan , Scott J. Limb
IPC分类号： H01L21/00
CPC分类号： H01L27/14658 , H01L27/14692
摘要： A method of forming a sensor array. The method includes depositing a source/drain contact layer; depositing a semiconductor layer on the source/drain contact layer; and patterning the source/drain contact layer and the semiconductor layer substantially simultaneously, wherein the patterned semiconductor layer forms part of a sensor of the sensor array.
摘要翻译：一种形成传感器阵列的方法。该方法包括沉积源极/漏极接触层; 在源极/漏极接触层上沉积半导体层; 并且基本上同时构图源极/漏极接触层和半导体层，其中图案化的半导体层形成传感器阵列的传感器的一部分。

2. 发明申请

US20100181604A1 STRUCTURE AND METHOD FOR FLEXIBLE SENSOR ARRAY 有权
标题翻译：柔性传感器阵列的结构和方法
公开(公告)号：US20100181604A1
公开(公告)日：2010-07-22
申请号：US12692379
申请日：2010-01-22
申请人： Sanjiv Sambandan , William S. Wong , Rene A. Lujan , Scott J. Limb
发明人： Sanjiv Sambandan , William S. Wong , Rene A. Lujan , Scott J. Limb
IPC分类号： H01L27/146
CPC分类号： H01L27/14658 , H01L27/14692
摘要： A method of forming a sensor array. The method includes depositing a source/drain contact layer; depositing a semiconductor layer on the source/drain contact layer; and patterning the source/drain contact layer and the semiconductor layer substantially simultaneously, wherein the patterned semiconductor layer forms part of a sensor of the sensor array.
摘要翻译：一种形成传感器阵列的方法。该方法包括沉积源极/漏极接触层; 在源极/漏极接触层上沉积半导体层; 并且基本上同时构图源极/漏极接触层和半导体层，其中图案化的半导体层形成传感器阵列的传感器的一部分。

3. 发明授权

US08193601B2 Structure and method for flexible sensor array 有权
标题翻译：柔性传感器阵列的结构和方法
公开(公告)号：US08193601B2
公开(公告)日：2012-06-05
申请号：US12692379
申请日：2010-01-22
申请人： Sanjiv Sambandan , William S. Wong , Rene A. Lujan , Scott J. Limb
发明人： Sanjiv Sambandan , William S. Wong , Rene A. Lujan , Scott J. Limb
IPC分类号： H01L31/102
CPC分类号： H01L27/14658 , H01L27/14692
摘要： A method of forming a sensor array. The method includes depositing a source/drain contact layer; depositing a semiconductor layer on the source/drain contact layer; and patterning the source/drain contact layer and the semiconductor layer substantially simultaneously, wherein the patterned semiconductor layer forms part of a sensor of the sensor array.
摘要翻译：一种形成传感器阵列的方法。该方法包括沉积源/漏接触层; 在源极/漏极接触层上沉积半导体层; 并且基本上同时构图源极/漏极接触层和半导体层，其中图案化的半导体层形成传感器阵列的传感器的一部分。

4. 发明申请

US20090159940A1 STRUCTURE AND METHOD FOR FLEXIBLE SENSOR ARRAY 有权
标题翻译：柔性传感器阵列的结构和方法
公开(公告)号：US20090159940A1
公开(公告)日：2009-06-25
申请号：US11963008
申请日：2007-12-21
申请人： Sanjiv Sambandan , William S. Wong , Rene A. Lujan , Scott J. Limb
发明人： Sanjiv Sambandan , William S. Wong , Rene A. Lujan , Scott J. Limb
IPC分类号： H01L27/146 , H01L31/18
CPC分类号： H01L27/14658 , H01L27/14692
摘要： A method of forming a sensor array. The method includes depositing a source/drain contact layer; depositing a semiconductor layer on the source/drain contact layer; and patterning the source/drain contact layer and the semiconductor layer substantially simultaneously, wherein the patterned semiconductor layer forms part of a sensor of the sensor array.
摘要翻译：一种形成传感器阵列的方法。该方法包括沉积源极/漏极接触层; 在源极/漏极接触层上沉积半导体层; 并且基本上同时构图源极/漏极接触层和半导体层，其中图案化的半导体层形成传感器阵列的传感器的一部分。

5. 发明申请

US20100252927A1 Pattern-Print Thin-Film Transistors with Top Gate Geometry 有权
标题翻译：带顶栅几何图案印刷薄膜晶体管
公开(公告)号：US20100252927A1
公开(公告)日：2010-10-07
申请号：US12817127
申请日：2010-06-16
申请人： William S. Wong , Rene A. Lujan , Eugene M. Chow
发明人： William S. Wong , Rene A. Lujan , Eugene M. Chow
IPC分类号： H01L29/45
CPC分类号： H01L29/41733 , H01L27/124 , H01L27/1285 , H01L27/1288 , H01L27/1292 , H01L29/42384 , H01L29/4908 , H01L29/66757
摘要： A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.
摘要翻译：公开了一种自对准薄膜顶栅晶体管及其制造方法。通过数字光刻在金属层上形成第一印刷图案掩模，例如通过使用液滴喷射器用相变材料进行印刷。然后使用第一印刷图案化掩模蚀刻金属层以形成源极和漏极。在其上形成半导体层和绝缘层。然后将一层感光材料沉积并暴露通过基底，源极和漏极用作曝光的掩模。在感光材料的显影之后，沉积栅极金属层。然后再次通过数字光刻法在器件上形成第二印刷图案掩模。蚀刻和去除感光材料离开自对准顶栅电极。

6. 发明授权

US08411075B2 Large area electronic sheet and pixel circuits with disordered semiconductors for sensor actuator interface 有权
标题翻译：用于传感器执行器接口的大面积电子薄片和具有无序半导体的像素电路
公开(公告)号：US08411075B2
公开(公告)日：2013-04-02
申请号：US12206690
申请日：2008-09-08
申请人： Sanjiv Sambandan , William S. Wong , Robert A. Street
发明人： Sanjiv Sambandan , William S. Wong , Robert A. Street
IPC分类号： G06F3/038 , G06G5/00
CPC分类号： G06F3/038
摘要： A pixel circuit including a first transistor; a second transistor, the first transistor and the second transistor serially coupled between a first power supply terminal and a second power supply terminal; and a first capacitor coupled between a gate of the first transistor and a gate of the second transistor, and an electronic sheet including the same.
摘要翻译：一种像素电路，包括第一晶体管; 第二晶体管，第一晶体管和第二晶体管，串联耦合在第一电源端子和第二电源端子之间; 以及耦合在所述第一晶体管的栅极和所述第二晶体管的栅极之间的第一电容器以及包括所述第一晶体管的电子薄片。

7. 发明申请

US20100073530A1 Method and Apparatus for Using Thin-Film Transistors and MIS Capacitors as Light-Sensing Elements in Charge Mapping Arrays 有权
标题翻译：使用薄膜晶体管和MIS电容器作为电荷映射阵列中的光敏元件的方法和装置
公开(公告)号：US20100073530A1
公开(公告)日：2010-03-25
申请号：US12235534
申请日：2008-09-22
申请人： Tse Nga Ng , Sanjiv Sambandan , William S. Wong
发明人： Tse Nga Ng , Sanjiv Sambandan , William S. Wong
IPC分类号： H04N5/335
CPC分类号： H01L27/14647 , H04N5/374
摘要： A method and apparatus for using TFT transistors or MIS capacitors as light-sensing elements in charge mapping arrays. A bias stress may be applied to a plurality of pixels in a charge map array. As a result, charge carriers may be trapped in each of the plurality of pixels responsive to the bias stress, which may be observed as a value shift such as a threshold voltage VT shift. Light may then be transmitted toward the plurality of pixels in the charge map array causing some of the pixels to absorb the light. The trapped charge carriers are released in the pixels that absorbed the light and not released in the pixels that did not absorb the light. The value shift in each of the pixels can be compared to determine which of the pixels absorbed the light.
摘要翻译：一种用于在电荷映射阵列中使用TFT晶体管或MIS电容器作为光感测元件的方法和装置。可以对电荷映射阵列中的多个像素施加偏压应力。结果，响应于偏压应力，电荷载流子可以被捕获在多个像素的每一个中，这可以被观察为诸如阈值电压VT偏移的值偏移。然后，光可以被传送到电荷映射阵列中的多个像素，导致一些像素吸收光。捕获的电荷载体在吸收光的像素中被释放，并且在不吸收光的像素中释放。可以比较每个像素中的值偏移，以确定吸收光的哪个像素。

8. 发明申请

US20100067280A1 CHARGE MAPPING MEMORY ARRAY FORMED OF MATERIALS WITH MUTABLE ELECTRICAL CHARACTERISTICS 有权
公开(公告)号：US20100067280A1
公开(公告)日：2010-03-18
申请号：US12622308
申请日：2009-11-19
申请人： William S. Wong , Sanjiv Sambandan , Tse Nga Ng , Robert A. Street
发明人： William S. Wong , Sanjiv Sambandan , Tse Nga Ng , Robert A. Street
IPC分类号： G11C5/06
CPC分类号： G11C13/003 , B82Y10/00 , G11C11/22 , G11C13/0014 , G11C13/0016 , G11C2213/53 , G11C2213/74 , G11C2213/79 , G11C2213/80
摘要： A memory cell array including a data line; a capacitor; and a transistor coupled between the data line and the capacitor. At least one of the capacitor and the transistor includes a material with a mutable electrical characteristic.A memory cell array including a first transistor coupled between a first node, a second node, and a third node; and a second transistor coupled between the second node and a fourth node. The first transistor includes a material with a mutable electrical characteristic.

9. 发明授权

US07344928B2 Patterned-print thin-film transistors with top gate geometry 有权
标题翻译：具有顶栅几何形状的图案印刷薄膜晶体管
公开(公告)号：US07344928B2
公开(公告)日：2008-03-18
申请号：US11193847
申请日：2005-07-28
申请人： William S. Wong , Rene A. Lujan , Eugene M. Chow
发明人： William S. Wong , Rene A. Lujan , Eugene M. Chow
IPC分类号： H01L21/84
CPC分类号： H01L29/41733 , H01L27/124 , H01L27/1285 , H01L27/1288 , H01L27/1292 , H01L29/42384 , H01L29/4908 , H01L29/66757
摘要： A self-aligned, thin-film, top-gate transistor and method of manufacturing same are disclosed. A first print-patterned mask is formed over a metal layer by digital lithography, for example by printing with a phase change material using a droplet ejector. The metal layer is then etched using the first print-patterned mask to form source and drain electrodes. A semiconductive layer and an insulative layer are formed thereover. A layer of photosensitive material is then deposited and exposed through the substrate, with the source and drain electrodes acting as masks for the exposure. Following development of the photosensitive material, a gate metal layer is deposited. A second print-patterned mask is then formed over the device, again by digital lithography. Etching and removal of the photosensitive material leaves the self-aligned top-gate electrode.
摘要翻译：公开了一种自对准薄膜顶栅晶体管及其制造方法。通过数字光刻在金属层上形成第一印刷图案掩模，例如通过使用液滴喷射器用相变材料进行印刷。然后使用第一印刷图案化掩模蚀刻金属层以形成源极和漏极。在其上形成半导体层和绝缘层。然后将一层感光材料沉积并暴露通过基底，源极和漏极用作曝光的掩模。在感光材料的显影之后，沉积栅极金属层。然后再次通过数字光刻法在器件上形成第二印刷图案掩模。蚀刻和去除感光材料离开自对准顶栅电极。

10. 发明授权

US07459400B2 Patterned structures fabricated by printing mask over lift-off pattern 有权
标题翻译：通过在剥离模式上印刷掩模制造的图案化结构
公开(公告)号：US07459400B2
公开(公告)日：2008-12-02
申请号：US11184304
申请日：2005-07-18
申请人： Ana C. Arias , Rene A. Lujan , William S. Wong
发明人： Ana C. Arias , Rene A. Lujan , William S. Wong
IPC分类号： H01L21/311
CPC分类号： H01L21/027 , H01L21/0272 , H01L27/1292 , H01L29/66765 , H01L51/0016
摘要： A patterned integrated circuit structure defining a gap or via is fabricated solely by digital printing and bulk processing. A sacrificial lift-off pattern is printed or otherwise formed over a substrate, and then covered by a blanket layer. A mask is then formed, e.g., by printing a wax pattern that covers a region of the blanket layer corresponding to the desired patterned structure, and overlaps the lift-off pattern. Exposed portions of the blanket layer are then removed, e.g., by wet etching. The printed mask and the lift-off pattern are then removed using a lift-off process that also removes any remaining portions of the blanket layer formed over the lift-off pattern. A thin-film transistor includes patterned source/drain structures that are self-aligned to an underlying gate structure by forming a photoresist lift-off pattern that is exposed and developed by a back-exposure process using the gate structure as a mask.
摘要翻译：限定间隙或通孔的图案化集成电路结构仅通过数字印刷和批量处理来制造。牺牲剥离图案印刷或以其它方式形成在衬底上，然后被覆盖层覆盖。然后形成掩模，例如通过印刷覆盖对应于所需图案化结构的橡皮布层的区域并与剥离图案重叠的蜡图案。然后例如通过湿蚀刻除去覆盖层的暴露部分。然后使用剥离过程去除印刷的掩模和剥离图案，剥离过程也去除在剥离图案上形成的覆盖层的任何剩余部分。薄膜晶体管包括通过形成通过使用栅极结构作为掩模的背景曝光工艺曝光和显影的光致抗蚀剂剥离图案而与底层栅极结构自对准的图案化源极/漏极结构。

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