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1. 发明授权

US06576482B1 One step deposition process for the top electrode and hardmask in a ferroelectric memory cell 有权
标题翻译：在铁电存储器单元中的顶部电极和硬掩模的一步沉积工艺
公开(公告)号：US06576482B1
公开(公告)日：2003-06-10
申请号：US10140481
申请日：2002-05-07
申请人： Sanjeev Aggarwal , Scott R. Summerfelt , Stevan G. Hunter
发明人： Sanjeev Aggarwal , Scott R. Summerfelt , Stevan G. Hunter
IPC分类号： H01L2100
CPC分类号： H01L28/75 , H01L21/28568 , H01L21/3143 , H01L28/55
摘要： One aspect of the invention relates to a one-step process for forming a transition metal aluminum oxynitride layer over a transition metal aluminum nitride layer. The transition metal aluminum nitride layer is sputter deposited using a transition metal/aluminum target in an atmosphere containing nitrogen. Subsequently, the oxygen content of the atmosphere is increased, whereby the transition metal aluminum oxynitride layer can be deposited without interrupting the process or otherwise reconditioning the target. Another aspect of the invention relates to depositing a transition metal aluminum nitride layer over a transition metal aluminum oxynitride layer by reducing the oxygen content of the atmosphere. The invention provides a one-step process for depositing a hard mask layer and upper diffusion barrier layer for the capacitor stack of a FeRAM. A top electrode, such as an Ir/IrO electrode, can be deposited as part of the one-step process.
摘要翻译：本发明的一个方面涉及在过渡金属氮化铝层上形成过渡金属铝氧氮化物层的一步法。使用过渡金属/铝靶在含氮的气氛中溅射沉积过渡金属氮化铝层。随后，气氛的氧含量增加，从而可以沉积过渡金属铝氮氧化物层，而不会中断该工艺或以其他方式修复靶。本发明的另一方面涉及通过降低大气中的氧含量在过渡金属铝氮氧化物层上沉积过渡金属氮化铝层。本发明提供了一种用于沉积FeRAM的电容器堆叠的硬掩模层和上扩散阻挡层的一步法。作为一步法的一部分，可以沉积上电极，例如Ir / IrO电极。

2. 发明授权

US06528386B1 Protection of tungsten alignment mark for FeRAM processing 有权
标题翻译：保护钨对准标记用于FeRAM处理
公开(公告)号：US06528386B1
公开(公告)日：2003-03-04
申请号：US10097919
申请日：2002-03-13
申请人： Scott R. Summerfelt , Luigi Colombo , Stephen R. Gilbert , Theodore S. Moise, IV , Sanjeev Aggarwal
发明人： Scott R. Summerfelt , Luigi Colombo , Stephen R. Gilbert , Theodore S. Moise, IV , Sanjeev Aggarwal
IPC分类号： H01L2176
CPC分类号： H01L27/11502 , H01L27/11507
摘要： A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the patterning of a top electrode layer and a dielectric layer to form a capacitor stack structure having sidewalls associated therewith. Prior to patterning the bottom electrode layer, a protective film is formed on the sidewalls of the capacitor stack structure in order to protect the dielectric material from conductive contaminants associated with a subsequent patterning of the bottom electrode layer.
摘要翻译：公开了一种制造铁电电容器的方法。该方法包括图案化顶部电极层和电介质层以形成具有与其相关联的侧壁的电容器堆叠结构。在图形化底部电极层之前，在电容器堆叠结构的侧壁上形成保护膜，以保护电介质材料免受与随后的底部电极层的图案化有关的导电污染物的影响。

3. 发明授权

US06596547B2 Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other processing 有权
标题翻译：通过金属有机化学气相沉积或其他处理防止PZT形成期间IrOx的还原的方法
公开(公告)号：US06596547B2
公开(公告)日：2003-07-22
申请号：US10036805
申请日：2001-12-21
申请人： Sanjeev Aggarwal , Stephen R. Gilbert , Scott R. Summerfelt
发明人： Sanjeev Aggarwal , Stephen R. Gilbert , Scott R. Summerfelt
IPC分类号： H01L2100
CPC分类号： H01L28/75 , C23C14/0084 , C23C14/08 , H01L28/55
摘要： A method of fabricating a ferroelectric capacitor is disclosed. The method comprises decreasing a reduction in a bottom electrode material during formation of the ferroelectric dielectric portion of the capacitor. The method comprises forming an oxygen doped iridium layer and forming a ferroelectric dielectric layer thereover. During the formation of the ferroelectric, the oxygen doped iridium layer converts to an iridium oxide layer.
摘要翻译：公开了一种制造铁电电容器的方法。该方法包括在形成电容器的铁电介质部分期间降低底部电极材料的减少。该方法包括形成氧掺杂铱层并在其上形成铁电介质层。在形成铁电体期间，掺杂氧的铱层转化为氧化铱层。

4. 发明授权

US06872669B1 PZT (111) texture through Ir texture improvement 有权
标题翻译： PZT（111）纹理通过Ir纹理改进
公开(公告)号：US06872669B1
公开(公告)日：2005-03-29
申请号：US10742190
申请日：2003-12-19
申请人： Scott R. Summerfelt , Sanjeev Aggarwal
发明人： Scott R. Summerfelt , Sanjeev Aggarwal
IPC分类号： H01L21/02 , H01L21/302 , H01L21/314 , H01L21/316 , H01L21/321 , H01L21/3213
CPC分类号： H01L28/55 , H01L21/3145 , H01L21/31691 , H01L21/3212 , H01L21/32131 , H01L28/65 , H01L28/75
摘要： The present invention is directed to a method of forming a ferroelectric capacitor having a (111) PZT texture. The method includes forming a smooth bottom electrode diffusion barrier layer that facilitates a preferential (111) texture in the subsequently formed bottom electrode layer. The (111) bottom electrode layer texture than facilitates a high quality (111) texture in the overlying PZT layer, thereby improving bit-to-bit polarization charge uniformity for various capacitors as the ferroelectric capacitor sizes continue to shrink.
摘要翻译：本发明涉及形成具有（111）PZT纹理的铁电电容器的方法。该方法包括形成平滑的底部电极扩散阻挡层，其有利于随后形成的底部电极层中的优先（111）纹理。（111）底电极层结构有利于上覆PZT层中的高质量（111）纹理，从而提高了随着铁电电容器尺寸的不断缩小，各种电容器的位对齐极化电荷均匀性。

5. 发明授权

US06686236B2 Methods of preventing reduction of IrOx during PZT formation by metalorganic chemical vapor deposition or other processing 有权
标题翻译：通过金属有机化学气相沉积或其他处理防止PZT形成期间IrOx的还原的方法
公开(公告)号：US06686236B2
公开(公告)日：2004-02-03
申请号：US10036827
申请日：2001-12-21
申请人： Sanjeev Aggarwal , Stephen R. Gilbert , Scott R. Summerfelt
发明人： Sanjeev Aggarwal , Stephen R. Gilbert , Scott R. Summerfelt
IPC分类号： H01L218242
CPC分类号： H01L21/02197 , C23C14/08 , H01L21/02271 , H01L21/31691 , H01L28/55 , H01L28/56 , H01L28/60 , H01L28/75
摘要： A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the decreases a reduction in a bottom electrode material during formation of the ferroelectric dielectric portion of the capacitor. In the above manner, a fatigue resistance of the ferroelectric capacitor is increased substantially.
摘要翻译：公开了一种制造铁电电容器的方法。该方法包括在形成电容器的铁电介质部分期间降低底部电极材料的减少。以上述方式，铁电电容器的耐疲劳性大幅度提高。

6. 发明授权

US06635498B2 Method of patterning a FeRAM capacitor with a sidewall during bottom electrode etch 有权
标题翻译：在底部电极蚀刻期间用侧壁构图FeRAM电容器的方法
公开(公告)号：US06635498B2
公开(公告)日：2003-10-21
申请号：US10222718
申请日：2002-08-16
申请人： Scott R. Summerfelt , Guoqiang Xing , Luigi Colombo , Sanjeev Aggarwal , Theodore S. Moise, IV
发明人： Scott R. Summerfelt , Guoqiang Xing , Luigi Colombo , Sanjeev Aggarwal , Theodore S. Moise, IV
IPC分类号： H01L2100
CPC分类号： H01L27/11502 , H01L21/31122 , H01L21/32136 , H01L27/11507 , H01L28/55 , H01L28/60
摘要： A method of fabricating a ferroelectric capacitor is disclosed. The method comprises the patterning of a top electrode layer and a dielectric layer to form a capacitor stack structure having sidewalls associated therewith. Prior to patterning the bottom electrode layer, a protective film is formed on the sidewalls of the capacitor stack structure in order to protect the dielectric material from conductive contaminants associated with a subsequent patterning of the bottom electrode layer.
摘要翻译：公开了一种制造铁电电容器的方法。该方法包括图案化顶部电极层和电介质层以形成具有与其相关联的侧壁的电容器堆叠结构。在图形化底部电极层之前，在电容器堆叠结构的侧壁上形成保护膜，以保护电介质材料免受与随后的底部电极层的图案化有关的导电污染物的影响。

7. 发明授权

US06984857B2 Hydrogen barrier for protecting ferroelectric capacitors in a semiconductor device and methods for fabricating the same 有权
标题翻译：用于保护半导体器件中的铁电电容器的氢屏障及其制造方法
公开(公告)号：US06984857B2
公开(公告)日：2006-01-10
申请号：US10620516
申请日：2003-07-16
申请人： K. R. Udayakumar , Martin G. Albrecht , Theodore S. Moise, IV , Scott R. Summerfelt , Sanjeev Aggarwal , Jeff L. Large
发明人： K. R. Udayakumar , Martin G. Albrecht , Theodore S. Moise, IV , Scott R. Summerfelt , Sanjeev Aggarwal , Jeff L. Large
IPC分类号： H01L29/76
CPC分类号： H01L28/57 , H01L23/564 , H01L2924/0002 , H01L2924/00
摘要： Semiconductor devices and fabrication methods are presented, in which a hydrogen barrier is provided above a ferroelectric capacitor to prevent degradation of the ferroelectric material during back-end manufacturing processes employing hydrogen. The hydrogen barrier comprises silicon rich silicon oxide or amorphous silicon, which can be used in combination with an aluminum oxide layer to inhibit diffusion of process-related hydrogen into the ferroelectric capacitor layer.
摘要翻译：提出了半导体器件和制造方法，其中在铁电电容器上方设置氢气阻挡层，以防止在使用氢的后端制造工艺期间铁电材料的劣化。氢势垒包括富硅氧化物或非晶硅，其可以与氧化铝层组合使用以抑制工艺相关氢扩散到铁电电容器层中。

8. 发明授权

US06876021B2 Use of amorphous aluminum oxide on a capacitor sidewall for use as a hydrogen barrier 有权
标题翻译：在电容器侧壁上使用无定形氧化铝作为氢气屏障
公开(公告)号：US06876021B2
公开(公告)日：2005-04-05
申请号：US10303560
申请日：2002-11-25
申请人： J. Scott Martin , Scott R. Summerfelt , Theodore S. Moise , Kelly J. Taylor , Luigi Colombo , Sanjeev Aggarwal , Sirisha Kuchimanchi , K. R. Udayakumar , Lindsey Hall
发明人： J. Scott Martin , Scott R. Summerfelt , Theodore S. Moise , Kelly J. Taylor , Luigi Colombo , Sanjeev Aggarwal , Sirisha Kuchimanchi , K. R. Udayakumar , Lindsey Hall
IPC分类号： H01L21/02 , H01L21/8246 , H01L27/115 , H01L31/119
CPC分类号： H01L27/11502 , H01L27/11507 , H01L28/55
摘要： The present invention forms sidewall diffusion barrier layer(s) that mitigate hydrogen contamination of ferroelectric capacitors. Sidewall diffusion barrier layer(s) of the present invention are formed via a physical vapor deposition process at a low temperature. By so doing, the sidewall diffusion barrier layer(s) are substantially amorphous and provide superior protection against hydrogen diffusion than conventional and/or crystalline sidewall diffusion barrier layers.
摘要翻译：本发明形成减轻铁电电容器的氢污染的侧壁扩散阻挡层。本发明的侧壁扩散阻挡层通过物理气相沉积工艺在低温下形成。通过这样做，侧壁扩散阻挡层基本上是无定形的，并提供优于常规和/或结晶侧壁扩散阻挡层的氢气扩散保护。

9. 发明授权

US06828161B2 Method of forming an FeRAM having a multi-layer hard mask and patterning thereof 有权
标题翻译：形成具有多层硬掩模并构图的FeRAM的方法
公开(公告)号：US06828161B2
公开(公告)日：2004-12-07
申请号：US10313068
申请日：2002-12-06
申请人： Scott R. Summerfelt , Sanjeev Aggarwal , Luigi Colombo , Theodore S. Moise, IV , J. Scott Martin
发明人： Scott R. Summerfelt , Sanjeev Aggarwal , Luigi Colombo , Theodore S. Moise, IV , J. Scott Martin
IPC分类号： H01L2100
CPC分类号： H01L27/11502 , H01L27/11507
摘要： The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a multi-layer hard mask. The multi-layer hard mask comprises a hard masking layer overlying an etch stop layer. The etch stop layer is substantially more selective than the overlying masking layer with respect to an etch employed to remove the bottom electrode diffusion barrier layer. Therefore during an etch of the capacitor stack, an etch of the bottom electrode diffusion barrier layer results in a substantially complete removal of the hard masking layer. However, due to the substantial selectivity (e.g., 10:1 or more) of the etch stop layer with respect to the overlying masking layer, the etch stop layer completely protects the underlying top electrode, thereby preventing exposure thereof.
摘要翻译：本发明涉及一种形成FeRAM集成电路的方法，其包括形成多层硬掩模。多层硬掩模包括覆盖在蚀刻停止层上的硬掩模层。相对于用于去除底部电极扩散阻挡层的蚀刻，蚀刻停止层比上覆掩模层更具选择性。因此，在电容器堆叠的蚀刻期间，底部电极扩散阻挡层的蚀刻导致硬掩模层的基本上完全去除。然而，由于蚀刻停止层相对于上覆掩模层的实质选择性（例如10:1或更多），蚀刻停止层完全保护下面的顶部电极，从而防止其暴露。

10. 发明授权

US06773930B2 Method of forming an FeRAM capacitor having a bottom electrode diffusion barrier 有权
标题翻译：形成具有底部电极扩散阻挡层的FeRAM电容器的方法
公开(公告)号：US06773930B2
公开(公告)日：2004-08-10
申请号：US10305838
申请日：2002-11-26
申请人： Scott R. Summerfelt , Sanjeev Aggarwal , Tomojuki Sakoda , Chiu Chi , Theodore S. Moise, IV
发明人： Scott R. Summerfelt , Sanjeev Aggarwal , Tomojuki Sakoda , Chiu Chi , Theodore S. Moise, IV
IPC分类号： H01L2100
CPC分类号： H01L27/11502 , H01L21/28568 , H01L27/11507 , H01L28/75
摘要： The present invention is directed to a method of forming an FeRAM integrated circuit, which includes forming a TiAlON bottom electrode diffusion barrier layer prior to formation of the bottom electrode layer in an FeRAM capacitor stack. Subsequently, when performing the capacitor stack etch, the portion of the TiAlON diffusion barrier layer not covered by the FeRAM capacitor stack is etched substantially anisotropically due to the oxygen within the TiAlON diffusion barrier layer substantially preventing a lateral etching thereof. In the above manner, an undercut of the TiAlON diffusion barrier layer under the FeRAM capacitor stack is prevented. In another aspect of the invention, a method of forming an FeRAM capacitor comprises forming a multi-layer bottom electrode diffusion barrier layer. Such formation comprises forming a TiN layer over the interlayer dielectric layer and the conductive contact and forming a diffusion barrier layer thereover. The TiN layer at least partially fills any seam that exists within the conductive contact, thus improving a conductivity between the FeRAM capacitor and a conductive contact in the interlayer dielectric.
摘要翻译：本发明涉及一种形成FeRAM集成电路的方法，其包括在FeRAM电容器堆叠中形成底部电极层之前形成TiAlON底部电极扩散阻挡层。随后，当执行电容器堆叠蚀刻时，TiAlON扩散阻挡层中未被FeRAM电容器堆叠覆盖的部分被TiAlON扩散阻挡层内的氧基本上各向异性地蚀刻，基本上防止了其横向蚀刻。以上述方式，防止了FeRAM电容器堆叠下的TiAlON扩散阻挡层的底切。在本发明的另一方面，形成FeRAM电容器的方法包括形成多层底电极扩散阻挡层。这种形成包括在层间电介质层和导电接触面上形成TiN层，并在其上形成扩散阻挡层。 TiN层至少部分地填充存在于导电接触中的任何接缝，从而提高了FeRAM电容器和层间电介质中的导电接触之间的导电性。

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