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    • 3. 发明授权
    • Reducing implementation costs of communicating cache invalidation information in a multicore processor
    • 降低在多核处理器中传送缓存无效信息的实施成本
    • US08639885B2
    • 2014-01-28
    • US12643238
    • 2009-12-21
    • Prashant JainSandip DasSanjay Patel
    • Prashant JainSandip DasSanjay Patel
    • G06F12/00
    • G06F12/0897Y02D10/13
    • A processor may include several processor cores, each including a respective higher-level cache, wherein each higher-level cache includes higher-level cache lines; and a lower-level cache including lower-level cache lines, where each of the lower-level cache lines may be configured to store data that corresponds to multiple higher-level cache lines. In response to invalidating a given lower-level cache line, the lower-level cache may be configured to convey a sequence including several invalidation packets to the processor cores via an interface, where each member of the sequence of invalidation packets corresponds to a respective higher-level cache line to be invalidated, and where the interface is narrower than an interface capable of concurrently conveying all invalidation information corresponding to the given lower-level cache line. Each invalidation packet may include invalidation information indicative of a location of the respective higher-level cache line within different ones of the processor cores.
    • 处理器可以包括几个处理器核心,每个处理器核心包括相应的更高级别的高速缓存,其中每个更高级别的高速缓存包括更高级别的高速缓存行; 以及包括较低级别高速缓存行的下级缓存,其中每个下级高速缓存行可以被配置为存储对应于多个更高级别的高速缓存行的数据。 响应于使给定的低级高速缓存行无效,低级缓存可以被配置为经由接口将包括若干无效分组的序列传送到处理器核,其中无效分组序列中的每个成员对应于相应较高的 高级缓存行将被无效,并且其中接口比能够同时传送对应于给定下级高速缓存行的所有无效信息的接口更窄。 每个无效分组可以包括指示相应的较高级别高速缓存行在不同处理器核心内的位置的无效信息。
    • 4. 发明申请
    • Apparatus and Method for Guest and Root Register Sharing in a Virtual Machine
    • 虚拟机中访客和根注册器共享的装置和方法
    • US20130263124A1
    • 2013-10-03
    • US13436654
    • 2012-03-30
    • Sanjay PatelRanjit Joseph Rozario
    • Sanjay PatelRanjit Joseph Rozario
    • G06F9/455
    • G06F9/4555
    • A computer readable storage medium includes executable instructions to define a processor with guest mode control registers supporting guest mode operating behavior defined by guest context specified in the guest mode control registers. The guest mode control registers include a control bit to specify a guest access blocked register state and a shared register state. Root mode control registers support root mode operating behavior defined by root context specified in the root mode control registers. The root mode control registers include control bits to enable replicated register state access and shared register state access. The guest context and the root context support virtualization of hardware resources such that multiple operating systems supporting multiple applications are executed by the hardware resources.
    • 计算机可读存储介质包括可执行指令,以定义具有访客模式控制寄存器的处理器,所述访客模式控制寄存器支持由访客模式控制寄存器中指定的访客上下文定 访客模式控制寄存器包括一个控制位,用于指定访客阻止寄存器状态和共享寄存器状态。 根模式控制寄存器支持在根模式控制寄存器中指定的根上下文定义的根模式操作行为。 根模式控制寄存器包括用于启用复制寄存器状态访问和共享寄存器状态访问的控制位。 访客环境和根本环境支持硬件资源的虚拟化,使得支持多个应用的​​多个操作系统由硬件资源执行。
    • 7. 发明授权
    • Optical coupling structure
    • 光耦合结构
    • US07616854B2
    • 2009-11-10
    • US11746162
    • 2007-05-09
    • Douglas M. GillSanjay PatelMahmoud Rasras
    • Douglas M. GillSanjay PatelMahmoud Rasras
    • G02B6/26
    • G02B6/1228
    • The present invention provides an apparatus and method for operation therefore. The apparatus, in one embodiment, includes an optical coupling structure disposed within a cladding region, wherein the optical coupling structure includes a first guiding portion and a second guiding portion. In this embodiment the first guiding portion has a first end proximate a core of a planar waveguide, and a second end proximate the second guiding portion and having a first thickness. Moreover, in this embodiment the second guiding portion has a first end proximate the first guiding portion and a second end, the second end of the second guiding portion having a second thickness less than the first thickness.
    • 本发明提供一种用于操作的装置和方法。 在一个实施例中,该装置包括设置在包层区域内的光耦合结构,其中光耦合结构包括第一引导部分和第二引导部分。 在该实施例中,第一引导部分具有靠近平面波导的芯的第一端和靠近第二引导部的第二端,并具有第一厚度。 此外,在该实施例中,第二引导部分具有靠近第一引导部分的第一端和第二端,第二引导部分的第二端具有小于第一厚度的第二厚度。