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1. 发明授权

US08639885B2 Reducing implementation costs of communicating cache invalidation information in a multicore processor 有权
标题翻译：降低在多核处理器中传送缓存无效信息的实施成本
公开(公告)号：US08639885B2
公开(公告)日：2014-01-28
申请号：US12643238
申请日：2009-12-21
申请人： Prashant Jain , Sandip Das , Sanjay Patel
发明人： Prashant Jain , Sandip Das , Sanjay Patel
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , Y02D10/13
摘要： A processor may include several processor cores, each including a respective higher-level cache, wherein each higher-level cache includes higher-level cache lines; and a lower-level cache including lower-level cache lines, where each of the lower-level cache lines may be configured to store data that corresponds to multiple higher-level cache lines. In response to invalidating a given lower-level cache line, the lower-level cache may be configured to convey a sequence including several invalidation packets to the processor cores via an interface, where each member of the sequence of invalidation packets corresponds to a respective higher-level cache line to be invalidated, and where the interface is narrower than an interface capable of concurrently conveying all invalidation information corresponding to the given lower-level cache line. Each invalidation packet may include invalidation information indicative of a location of the respective higher-level cache line within different ones of the processor cores.
摘要翻译：处理器可以包括几个处理器核心，每个处理器核心包括相应的更高级别的高速缓存，其中每个更高级别的高速缓存包括更高级别的高速缓存行; 以及包括较低级别高速缓存行的下级缓存，其中每个下级高速缓存行可以被配置为存储对应于多个更高级别的高速缓存行的数据。响应于使给定的低级高速缓存行无效，低级缓存可以被配置为经由接口将包括若干无效分组的序列传送到处理器核，其中无效分组序列中的每个成员对应于相应较高的高级缓存行将被无效，并且其中接口比能够同时传送对应于给定下级高速缓存行的所有无效信息的接口更窄。每个无效分组可以包括指示相应的较高级别高速缓存行在不同处理器核心内的位置的无效信息。

2. 发明申请

US20120239883A1 RESOURCE SHARING TO REDUCE IMPLEMENTATION COSTS IN A MULTICORE PROCESSOR 有权
标题翻译：资源共享，以减少多处理器中的执行成本
公开(公告)号：US20120239883A1
公开(公告)日：2012-09-20
申请号：US13486091
申请日：2012-06-01
申请人： Prashant Jain , Yoganand Chillarige , Sandip Das , Shukur Moulali Pathan , Srinivasan R. Iyengar , Sanjay Patel
发明人： Prashant Jain , Yoganand Chillarige , Sandip Das , Shukur Moulali Pathan , Srinivasan R. Iyengar , Sanjay Patel
IPC分类号： G06F12/08
CPC分类号： G06F12/0811 , G06F12/0813
摘要： A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers in a given tag unit may share access to a resource that may include one or more of an interconnect egress port coupled to the interconnect network, an interconnect ingress port coupled to the interconnect network, a test controller, or a data storage structure.
摘要翻译：处理器可以包括几个处理器核心，每个处理器核心包括相应的更高级别的高速缓存; 包括几个标签单元的低级缓存，每个标签单元包括多个控制器，其中每个控制器对应于被配置为存储数据的相应缓存组，并且其中控制器同时可操作以访问其各自的高速缓存存储体; 以及被配置为在所述核和所述下级缓存之间传送数据的互连网络。给定标签单元中的控制器可以共享对可以包括耦合到互连网络的互连出口端口，耦合到互连网络的互连入口端口，测试控制器或数据存储结构中的一个或多个的资源的访问。

3. 发明申请

US20110185125A1 RESOURCE SHARING TO REDUCE IMPLEMENTATION COSTS IN A MULTICORE PROCESSOR 有权
标题翻译：资源共享，以减少多处理器中的执行成本
公开(公告)号：US20110185125A1
公开(公告)日：2011-07-28
申请号：US12694877
申请日：2010-01-27
申请人： Prashant Jain , Yoganand Chillarige , Sandip Das , Shukur Moulali Pathan , Srinivasan R. Iyengar , Sanjay Patel
发明人： Prashant Jain , Yoganand Chillarige , Sandip Das , Shukur Moulali Pathan , Srinivasan R. Iyengar , Sanjay Patel
IPC分类号： G06F12/08 , G06F12/00 , G06F13/28
CPC分类号： G06F12/0811 , G06F12/0813
摘要： A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers may share access to an interconnect egress port coupled to the interconnect network, and may generate multiple concurrent requests to convey data via the shared port, where each of the requests is destined for a corresponding core, and where a datapath width of the port is less than a combined width of the multiple requests. The given tag unit may arbitrate among the controllers for access to the shared port, such that the requests are transmitted to corresponding cores serially rather than concurrently.
摘要翻译：处理器可以包括几个处理器核心，每个处理器核心包括相应的更高级别的高速缓存; 包括几个标签单元的低级缓存，每个标签单元包括多个控制器，其中每个控制器对应于被配置为存储数据的相应缓存组，并且其中控制器同时可操作以访问其各自的高速缓存存储体; 以及被配置为在所述核和所述下级缓存之间传送数据的互连网络。控制器可以共享对耦合到互连网络的互连出口端口的访问，并且可以生成多个并发请求以经由共享端口传送数据，其中每个请求去往相应的核心，并且其中端口的数据路径宽度小于多个请求的组合宽度。给定标签单元可以在控制器之间仲裁以访问共享端口，使得请求被串行地发送到相应的核心而不是同时发送。

4. 发明授权

US08195883B2 Resource sharing to reduce implementation costs in a multicore processor 有权
标题翻译：资源共享以降低多核处理器中的实施成本
公开(公告)号：US08195883B2
公开(公告)日：2012-06-05
申请号：US12694877
申请日：2010-01-27
申请人： Prashant Jain , Yoganand Chillarige , Sandip Das , Shukur Moulali Pathan , Srinivasan R. Iyengar , Sanjay Patel
发明人： Prashant Jain , Yoganand Chillarige , Sandip Das , Shukur Moulali Pathan , Srinivasan R. Iyengar , Sanjay Patel
IPC分类号： G06F13/00
CPC分类号： G06F12/0811 , G06F12/0813
摘要： A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers may share access to an interconnect egress port coupled to the interconnect network, and may generate multiple concurrent requests to convey data via the shared port, where each of the requests is destined for a corresponding core, and where a datapath width of the port is less than a combined width of the multiple requests. The given tag unit may arbitrate among the controllers for access to the shared port, such that the requests are transmitted to corresponding cores serially rather than concurrently.
摘要翻译：处理器可以包括几个处理器核心，每个处理器核心包括相应的更高级别的高速缓存; 包括几个标签单元的低级缓存，每个标签单元包括多个控制器，其中每个控制器对应于被配置为存储数据的相应缓存组，并且其中控制器同时可操作以访问其各自的高速缓存存储体; 以及被配置为在所述核和所述下级缓存之间传送数据的互连网络。控制器可以共享对耦合到互连网络的互连出口端口的访问，并且可以生成多个并发请求以经由共享端口传送数据，其中每个请求去往相应的核心，并且其中端口的数据路径宽度小于多个请求的组合宽度。给定标签单元可以在控制器之间仲裁以访问共享端口，使得请求被串行地发送到相应的核心而不是同时发送。

5. 发明授权

US08516196B2 Resource sharing to reduce implementation costs in a multicore processor 有权
标题翻译：资源共享以降低多核处理器中的实施成本
公开(公告)号：US08516196B2
公开(公告)日：2013-08-20
申请号：US13486091
申请日：2012-06-01
申请人： Prashant Jain , Yoganand Chillarige , Sandip Das , Shukur Moulali Pathan , Srinivasan R. Iyengar , Sanjay Patel
发明人： Prashant Jain , Yoganand Chillarige , Sandip Das , Shukur Moulali Pathan , Srinivasan R. Iyengar , Sanjay Patel
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0813
摘要： A processor may include several processor cores, each including a respective higher-level cache; a lower-level cache including several tag units each including several controllers, where each controller corresponds to a respective cache bank configured to store data, and where the controllers are concurrently operable to access their respective cache banks; and an interconnect network configured to convey data between the cores and the lower-level cache. The controllers in a given tag unit may share access to a resource that may include one or more of an interconnect egress port coupled to the interconnect network, an interconnect ingress port coupled to the interconnect network, a test controller, or a data storage structure.
摘要翻译：处理器可以包括几个处理器核，每个处理器核包括相应的更高级的高速缓存; 包括几个标签单元的低级缓存，每个标签单元包括多个控制器，其中每个控制器对应于被配置为存储数据的相应缓存组，并且其中控制器同时可操作以访问其各自的高速缓存存储体; 以及被配置为在所述核和所述下级缓存之间传送数据的互连网络。给定标签单元中的控制器可以共享对可以包括耦合到互连网络的互连出口端口，耦合到互连网络的互连入口端口，测试控制器或数据存储结构中的一个或多个的资源的访问。

6. 发明申请

US20110153942A1 REDUCING IMPLEMENTATION COSTS OF COMMUNICATING CACHE INVALIDATION INFORMATION IN A MULTICORE PROCESSOR 有权
标题翻译：减少多媒体处理程序中高速缓存无效信息的实现成本
公开(公告)号：US20110153942A1
公开(公告)日：2011-06-23
申请号：US12643238
申请日：2009-12-21
申请人： Prashant Jain , Sandip Das , Sanjay Patel
发明人： Prashant Jain , Sandip Das , Sanjay Patel
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0897 , Y02D10/13
摘要： A processor may include several processor cores, each including a respective higher-level cache, wherein each higher-level cache includes higher-level cache lines; and a lower-level cache including lower-level cache lines, where each of the lower-level cache lines may be configured to store data that corresponds to multiple higher-level cache lines. In response to invalidating a given lower-level cache line, the lower-level cache may be configured to convey a sequence including several invalidation packets to the processor cores via an interface, where each member of the sequence of invalidation packets corresponds to a respective higher-level cache line to be invalidated, and where the interface is narrower than an interface capable of concurrently conveying all invalidation information corresponding to the given lower-level cache line. Each invalidation packet may include invalidation information indicative of a location of the respective higher-level cache line within different ones of the processor cores.
摘要翻译：处理器可以包括几个处理器核心，每个处理器核心包括相应的更高级别的高速缓存，其中每个更高级别的高速缓存包括更高级别的高速缓存行; 以及包括较低级别高速缓存行的下级缓存，其中每个下级高速缓存行可以被配置为存储对应于多个更高级别的高速缓存行的数据。响应于使给定的低级高速缓存行无效，低级缓存可以被配置为经由接口将包括若干无效分组的序列传送到处理器核，其中无效分组序列中的每个成员对应于相应较高的高级缓存行将被无效，并且其中接口比能够同时传送对应于给定下级高速缓存线的所有无效信息的接口窄。每个无效分组可以包括指示相应的较高级别高速缓存行在不同处理器核心内的位置的无效信息。

7. 发明授权

US07359532B2 Fingerprint minutiae matching using scoring techniques 有权
标题翻译：使用评分技术的指纹细节匹配
公开(公告)号：US07359532B2
公开(公告)日：2008-04-15
申请号：US10734335
申请日：2003-12-11
申请人： Tinku Acharya , Bhargab B. Bhattacharya , Arindam Biswas , Partha Bhowmick , Arijit Bishnu , Sandip Das , Malay K. Kundu , Chivukula A. Murthy , Subhas C. Nandy
发明人： Tinku Acharya , Bhargab B. Bhattacharya , Arindam Biswas , Partha Bhowmick , Arijit Bishnu , Sandip Das , Malay K. Kundu , Chivukula A. Murthy , Subhas C. Nandy
IPC分类号： G06K9/00
CPC分类号： G06K9/00087
摘要： Disclosed is a method and apparatus to provide for fingerprint minutiae matching using scoring techniques. A plurality of minutiae in a fingerprint image is defined. A score associated with each minutia corresponding to the validity of each minutia is estimated. The fingerprint image is then matched against one or more sample fingerprint images utilizing a partial point set pattern matching (PSPM) algorithm.
摘要翻译：公开了一种使用评分技术提供指纹细节匹配的方法和装置。定义指纹图像中的多个细节。估计与每个细节的有效性对应的每个细节相关联的分数。然后使用部分点集模式匹配（PSPM）算法将指纹图像与一个或多个样本指纹图像进行匹配。

8. 发明申请

US20050129293A1 Fingerprint minutiae matching using scoring techniques 有权
标题翻译：使用评分技术的指纹细节匹配
公开(公告)号：US20050129293A1
公开(公告)日：2005-06-16
申请号：US10734335
申请日：2003-12-11
申请人： Tinku Acharya , Bhargab Bhattacharya , Arindam Biswas , Partha Bhowmick , Arijit Bishnu , Sandip Das , Malay Kundu , C. Murthy , Subhas Nandy
发明人： Tinku Acharya , Bhargab Bhattacharya , Arindam Biswas , Partha Bhowmick , Arijit Bishnu , Sandip Das , Malay Kundu , C. Murthy , Subhas Nandy
IPC分类号： G06K9/00
CPC分类号： G06K9/00087
摘要： Disclosed is a method and apparatus to provide for fingerprint minutiae matching using scoring techniques. A plurality of minutiae in a fingerprint image is defined. A score associated with each minutia corresponding to the validity of each minutia is estimated. The fingerprint image is then matched against one or more sample fingerprint images utilizing a partial point set pattern matching (PSPM) algorithm.
摘要翻译：公开了一种使用评分技术提供指纹细节匹配的方法和装置。定义指纹图像中的多个细节。估计与每个细节的有效性对应的每个细节相关联的分数。然后使用部分点集模式匹配（PSPM）算法将指纹图像与一个或多个样本指纹图像进行匹配。

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