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1. 发明公开

US20240029784A1 DRAM DEVICE AND ODT RESISTOR VALUE ADJUSTMENT METHOD AND COMPUTER PROGRAM FOR THE SAME 审中-公开
公开(公告)号：US20240029784A1
公开(公告)日：2024-01-25
申请号：US18476475
申请日：2023-09-28
申请人： Sang-Seok Kang , Young-Hee Jung , Sun-Young LEE
发明人： Sang-Seok Kang , Young-Hee Jung , Sun-Young LEE
IPC分类号： G11C11/4093 , G11C5/04 , G11C11/4096 , G11C11/408
CPC分类号： G11C11/4093 , G11C5/04 , G11C11/4096 , G11C11/4082 , G11C11/4076
摘要： Disclosed are a dynamic random access memory (DRAM) device, an on-die termination (ODT) resistance value setting method thereof, and a computer program therefor, and the DRAM device includes at least one DRAM module and a memory controller configured to measure a resistance value of an ODT resistor corresponding to one of a rank included in the DRAM module, a chipset included in the rank, and a DQ included in the chipset and set a resistance value of an ODT resistor corresponding to one of the rank, the chipset, and the DQ on the basis of the measured resistance value.

2. 发明授权

US11837278B2 DRAM device and ODT resistor value adjustment method and computer program for the same 有权
公开(公告)号：US11837278B2
公开(公告)日：2023-12-05
申请号：US17678500
申请日：2022-02-23
申请人： Sang-Seok Kang , Young-Hee Jung , Sun-Young Lee
发明人： Sang-Seok Kang , Young-Hee Jung , Sun-Young Lee
IPC分类号： G11C7/10 , G11C11/4093 , G11C5/04 , G11C11/4096 , G11C11/408 , G11C11/4076
CPC分类号： G11C11/4093 , G11C5/04 , G11C11/4082 , G11C11/4096 , G11C11/4076
摘要： Disclosed are a dynamic random access memory (DRAM) device, an on-die termination (ODT) resistance value setting method thereof, and a computer program therefor, and the DRAM device includes at least one DRAM module and a memory controller configured to measure a resistance value of an ODT resistor corresponding to one of a rank included in the DRAM module, a chipset included in the rank, and a DQ included in the chipset and set a resistance value of an ODT resistor corresponding to one of the rank, the chipset, and the DQ on the basis of the measured resistance value.

3. 发明申请

US20220284946A1 DRAM DEVICE AND ODT RESISTOR VALUE ADJUSTMENT METHOD AND COMPUTER PROGRAM FOR THE SAME 有权
公开(公告)号：US20220284946A1
公开(公告)日：2022-09-08
申请号：US17678500
申请日：2022-02-23
申请人： Sang-Seok Kang , Young-Hee Jung , Sun-Young LEE
发明人： Sang-Seok Kang , Young-Hee Jung , Sun-Young LEE
IPC分类号： G11C11/4093 , G11C5/04 , G11C11/408 , G11C11/4096
摘要： Disclosed are a dynamic random access memory (DRAM) device, an on-die termination (ODT) resistance value setting method thereof, and a computer program therefor, and the DRAM device includes at least one DRAM module and a memory controller configured to measure a resistance value of an ODT resistor corresponding to one of a rank included in the DRAM module, a chipset included in the rank, and a DQ included in the chipset and set a resistance value of an ODT resistor corresponding to one of the rank, the chipset, and the DQ on the basis of the measured resistance value.

4. 发明授权

US06906545B1 Voltage measurement device tolerant of undershooting or overshooting input voltage of pad 有权
标题翻译：电压测量装置容许欠压或过冲垫的输入电压
公开(公告)号：US06906545B1
公开(公告)日：2005-06-14
申请号：US10359527
申请日：2003-02-05
申请人： Young-Hee Jung , Sang-Seok Kang
发明人： Young-Hee Jung , Sang-Seok Kang
IPC分类号： G11C5/14 , G01R31/26 , H03K17/16 , H03K17/687
CPC分类号： H03K17/162 , H03K17/6872
摘要： There is provided a voltage measurement device that is stable with respect to an undershot or overshot input voltage of a pad. The voltage measurement device includes a voltage line, a pad, a signal generating unit, a first switch, and a second switch. The first switch is connected between the pad and the second switch and the second switch is connected to the voltage line. The signal generating unit receives a control signal and generates an inverted control signal. The voltage line is connected to the pad through the first and second switches that are responsive to the control signal. The pad is also connected to an internal circuit block, so that the internal circuit block is driven according to a pad input. Specifically, the first and second switches can be implemented with an NMOS transistor and a PMOS transistor that are responsive to the control signal and the inverted control signal, respectively. Therefore, even if a logic level input to the pad is an undershot or overshot voltage level, a voltage level of the voltage line is not changed.
摘要翻译：提供了一种电压测量装置，其相对于焊盘的欠压或过冲输入电压是稳定的。电压测量装置包括电压线，焊盘，信号产生单元，第一开关和第二开关。第一开关连接在焊盘和第二开关之间，第二开关连接到电压线。信号发生单元接收控制信号并产生反相控制信号。电压线通过响应于控制信号的第一和第二开关连接到焊盘。焊盘也连接到内部电路块，使得内部电路块根据焊盘输入被驱动。具体地说，第一和第二开关可以用分别响应于控制信号和反相控制信号的NMOS晶体管和PMOS晶体管来实现。因此，即使输入到焊盘的逻辑电平是欠压或过压电压电平，电压线的电压电平也不会改变。

5. 发明授权

US07116127B2 Circuit with fuse and semiconductor device having the same circuit 失效
标题翻译：具有保险丝和半导体器件的电路具有相同的电路
公开(公告)号：US07116127B2
公开(公告)日：2006-10-03
申请号：US10640736
申请日：2003-08-13
申请人： Young-Hee Jung , Sang-Seok Kang
发明人： Young-Hee Jung , Sang-Seok Kang
IPC分类号： H03K17/16
CPC分类号： G11C17/18 , G11C29/781
摘要： A circuit with fuses and a semiconductor device having the same circuit include a first switch connected to a power supply voltage or a signal input terminal and turned on in response to a first pulse signal, a second switch connected to a ground voltage and turned on in response to a second pulse signal, a fuse connected between the first switch and the second switch, and a signal generating circuit for producing the first and second pulse signals. The first pulse signal turns off the first switch before the second pulse signal turns on the second switch and the first pulse signal turns on the first switch after the second pulse signal turns off the second switch.
摘要翻译：具有熔丝和具有相同电路的半导体器件的电路包括连接到电源电压或信号输入端的第一开关并响应于第一脉冲信号而导通，第二开关连接到接地电压并接通响应于第二脉冲信号，连接在第一开关和第二开关之间的保险丝，以及用于产生第一和第二脉冲信号的信号发生电路。第一脉冲信号在第二脉冲信号接通第二开关之前关闭第一开关，并且在第二脉冲信号关闭第二开关之后第一脉冲信号接通第一开关。

6. 发明授权

US07675316B2 Semiconductor memory device including on die termination circuit and on die termination method thereof 失效
标题翻译：半导体存储器件包括管芯端接电路及其管芯端接方法
公开(公告)号：US07675316B2
公开(公告)日：2010-03-09
申请号：US11429365
申请日：2006-05-05
申请人： Jong-Hyoung Lim , Sang-Seok Kang
发明人： Jong-Hyoung Lim , Sang-Seok Kang
IPC分类号： H03K17/16
CPC分类号： G11C7/1078 , G11C5/063 , G11C7/1048 , G11C7/1057 , G11C7/1084
摘要： A semiconductor memory device is provided. The device includes an on die termination circuit controlling a termination resistance value by detecting a phase change of a signal inputted through a pad. Additionally, the on die termination circuit changes the termination resistance value when an identical phase signal is inputted during n (n is positive integer) periods of a clock signal.
摘要翻译：提供半导体存储器件。该器件包括通过检测通过焊盘输入的信号的相位变化来控制终端电阻值的芯片上终端电路。此外，当在时钟信号的n（n为正整数）周期期间输入相同的相位信号时，导线端接电路改变终端电阻值。

7. 发明申请

US20080052567A1 Semiconductor memory device and method thereof 有权
标题翻译：半导体存储器件及其方法
公开(公告)号：US20080052567A1
公开(公告)日：2008-02-28
申请号：US11730273
申请日：2007-03-30
申请人： Jong-Hyoung Lim , Sang-Seok Kang
发明人： Jong-Hyoung Lim , Sang-Seok Kang
IPC分类号： G11C29/00
CPC分类号： G11C7/1078 , G11C7/1006 , G11C7/1096 , G11C11/4096
摘要： A semiconductor memory device and method thereof are provided. The example method may be directed to performing a memory operation in a semiconductor memory device, and may include receiving data and a data masking signal corresponding to at least a portion of the received data, the received data scheduled to be written into memory in response to a write command and the data masking signal configured to block the at least a portion of the received data from being written into the memory and configuring timing parameters differently for each of the received data and the data masking signal so as to execute the write command without writing the at least a portion of the received data into the memory.
摘要翻译：提供一种半导体存储器件及其方法。示例性方法可以涉及在半导体存储器件中执行存储器操作，并且可以包括接收对应于所接收的数据的至少一部分的数据和数据屏蔽信号，响应于写入命令和数据屏蔽信号，被配置为阻止所接收的数据的至少一部分被写入到存储器中，并且针对每个接收的数据和数据屏蔽信号配置不同的定时参数，从而执行写入命令而没有将所接收的数据的至少一部分写入存储器。

8. 发明授权

US06972612B2 Semiconductor device with malfunction control circuit and controlling method thereof 有权
标题翻译：具有故障控制电路的半导体器件及其控制方法
公开(公告)号：US06972612B2
公开(公告)日：2005-12-06
申请号：US10277573
申请日：2002-10-21
申请人： Sang-Seok Kang , Kyeong-Seon Shin , Ki-Sang Kang
发明人： Sang-Seok Kang , Kyeong-Seon Shin , Ki-Sang Kang
IPC分类号： G01R31/30 , G11C17/18 , G11C29/00 , H01L23/544 , H01H37/76 , H01H85/00
CPC分类号： G01R31/30 , G11C17/18 , G11C29/006 , G11C2029/4402 , H01L23/544 , H01L2223/5444 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit of a semiconductor device has a chip malfunction controlling circuit embedded in a chip. The circuit comprises a fusing part, to which a cutting will be made in the manufacturing process according to the result of the discrimination of a defect in a chip, with one end thereof being connected to a first power terminal. A signal generating part is connected to the other end of the fusing part, and to a second power terminal. The signal generating part generates a discrimination signal of discriminating whether the chip is defective or not, by whether the fusing part has been cut or not. The discrimination signal is supplied to at least one internal function circuit, and inhibits its operation if the fusing part has been cut. Furthermore, the chip malfunction controlling method comprises generating a discrimination signal that has a first state if a test fuse has been cut and a second state if the test fuse has not been cut. Then the discrimination signal is applied to the chip internal function circuits, to inhibit their operation if the fuse has been cut.
摘要翻译：半导体器件的集成电路具有嵌入芯片中的芯片故障控制电路。该电路包括一个定影部分，根据鉴别芯片中的缺陷的结果，在制造过程中将进行切割，其一端连接到第一电源端子。信号产生部分连接到定影部分的另一端，并连接到第二电源端子。信号产生部分通过定影部分是否被切断来产生鉴别芯片是否有故障的鉴别信号。鉴别信号被提供给至少一个内部功能电路，并且如果定影部件被切割，则禁止其操作。此外，芯片故障控制方法包括：如果测试保险丝已被切断，则产生具有第一状态的判别信号，如果测试保险丝未被切断，则产生第二状态。然后，识别信号被施加到芯片内部功能电路，如果保险丝被切断，则抑制它们的操作。

9. 发明授权

US06658612B1 Test signal generating circuit of a semiconductor device with pins receiving signals of multiple voltage levels and method for invoking test modes 失效
标题翻译：具有接收多电压电平信号的引脚的半导体器件的测试信号发生电路和用于调用测试模式的方法
公开(公告)号：US06658612B1
公开(公告)日：2003-12-02
申请号：US09550944
申请日：2000-04-17
申请人： Cheol-Hong Park , Sang-Seok Kang , Jong-Hyun Choi
发明人： Cheol-Hong Park , Sang-Seok Kang , Jong-Hyun Choi
IPC分类号： G01R3128
CPC分类号： G11C29/46 , G01R31/31813 , G11C2029/5004
摘要： A signal generating circuit of a semiconductor device comprises n input test pins for receiving respective coded input signals. At least one of the input signals is coded in more than two possible levels, such as 3 levels or four levels. The device also includes an indicator I/O signal generators, each coupled respectively with an associated input test pin. Each indicator signal generator generates two-level indicator signals in response to the coded input signal received by its associated input test pin. A decoder receives the indicator signals to produce decoded signals, and a mode selecting circuit generates mode selecting signals with the decoded signals responsive to mode setting signals. Each indicator signal generators outputs a regular signal when the input test signal is an ordinary low, a control signal when the input test signal is an ordinary high, and a higher first level signal when the input test signal is a super high. If more than three levels are used, the indicator signal generator further generates corresponding signals for these higher values.
摘要翻译：半导体器件的信号发生电路包括用于接收各个编码输入信号的n个输入测试引脚。输入信号中的至少一个以多于两个可能的级别编码，例如3级或4级。该装置还包括一个指示器I / O信号发生器，每个发生器分别与相关的输入测试引脚相连。每个指示信号发生器响应于由其相关输入测试引脚接收到的编码输入信号产生两电平指示信号。解码器接收指示信号以产生解码信号，并且模式选择电路响应于模式设置信号产生具有解码信号的模式选择信号。当输入测试信号为普通低电平时，指示信号发生器输出常规信号，当输入测试信号为普通高电平时输入控制信号，当输入测试信号为超高电平时，输出高电平信号。如果使用三个以上的电平，指示信号发生器进一步产生这些较高值的相应信号。

10. 发明授权

US6084808A Circuits and methods for burn-in of integrated circuits using potential differences between adjacent main word lines 有权
标题翻译：使用相邻主字线之间的潜在差异来集成电路老化的电路和方法
公开(公告)号：US6084808A
公开(公告)日：2000-07-04
申请号：US199903
申请日：1998-11-25
申请人： Jong-Hyoung Lim , Sang-Seok Kang , Jin-Seok Lee , Byung-Il Ryu
发明人： Jong-Hyoung Lim , Sang-Seok Kang , Jin-Seok Lee , Byung-Il Ryu
IPC分类号： G01R31/26 , G11C29/00 , G11C29/02 , G11C29/06 , G11C29/50 , G11C7/00
CPC分类号： G11C29/025 , G11C29/02 , G11C29/50
摘要： External address signals are applied to an integrated circuit in a burn-in test mode. The external address signals control the voltage levels of adjacent main word lines in a memory array in the integrated circuit. The adjacent main word lines may thereby be configured in to be in opposing logic states. The opposing logic states may provide a potential difference between the adjacent main word lines, thereby increasing the likelihood of detecting microbridges between the adjacent main word lines formed during fabrication of the integrated circuit. The reliability of the integrated circuit may thereby be improved.
摘要翻译：外部地址信号以老化测试模式应用于集成电路。外部地址信号控制集成电路中的存储器阵列中的相邻主字线的电压电平。因此，相邻的主字线可以被配置为处于相反的逻辑状态。相对的逻辑状态可以提供相邻主字线之间的电位差，从而增加在集成电路制造期间形成的相邻主字线之间检测微桥的可能性。可以提高集成电路的可靠性。

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