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1. 发明授权

US07173872B2 Method and apparatus for controlling a high voltage generator in a wafer burn-in test 有权
标题翻译：用于在晶片老化测试中控制高压发生器的方法和装置
公开(公告)号：US07173872B2
公开(公告)日：2007-02-06
申请号：US11327104
申请日：2006-01-05
申请人： Choong-Sun Park , Hyung-Dong Kim , Sang-Seok Kang , Jong-Hyun Choi , Yong-Hwan Jung
发明人： Choong-Sun Park , Hyung-Dong Kim , Sang-Seok Kang , Jong-Hyun Choi , Yong-Hwan Jung
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C5/145 , G11C5/146 , G11C29/006 , G11C29/02 , G11C29/021 , G11C29/12005 , G11C29/1201
摘要： The invention relates to a method and apparatus for controlling a high voltage generator during wafer burn-in. The method includes generating an enable signal for enabling a high voltage generator responsive to a mode signal, e.g., a wafer burn-in test mode. The method provides an external voltage to a semiconductor memory device through a pad responsive to the enable signal. The method varies a high voltage level being output from the high voltage generator in response to a reference voltage level.
摘要翻译：本发明涉及一种用于在晶片老化期间控制高压发生器的方法和装置。该方法包括产生响应于模式信号的高电压发生器的使能信号，例如晶片老化测试模式。该方法通过响应于使能信号的焊盘向半导体存储器件提供外部电压。该方法响应于参考电压电平而改变从高电压发生器输出的高电压电平。

2. 发明授权

US07016248B2 Method and apparatus for controlling a high voltage generator in a wafer burn-in test 有权
标题翻译：用于在晶片老化测试中控制高压发生器的方法和装置
公开(公告)号：US07016248B2
公开(公告)日：2006-03-21
申请号：US10423505
申请日：2003-04-25
申请人： Choong-Sun Park , Hyung-Dong Kim , Sang-Seok Kang , Jong-Hyun Choi , Yong-Hwan Jung
发明人： Choong-Sun Park , Hyung-Dong Kim , Sang-Seok Kang , Jong-Hyun Choi , Yong-Hwan Jung
IPC分类号： G11C7/00
CPC分类号： G11C5/145 , G11C5/146 , G11C29/006 , G11C29/02 , G11C29/021 , G11C29/12005 , G11C29/1201
摘要： The invention relates to a method and apparatus for controlling a high voltage generator during wafer burn-in. The method includes generating an enable signal for enabling a high voltage generator responsive to a mode signal, e.g., a wafer bum-in test mode. The method provides an external voltage to a semiconductor memory device through a pad responsive to the enable signal. The method varies a high voltage level being output from the high voltage generator in response to a reference voltage level.
摘要翻译：本发明涉及一种用于在晶片老化期间控制高压发生器的方法和装置。该方法包括产生响应于模式信号（例如，晶片烧入测试模式）使得高电压发生器能够使能的使能信号。该方法通过响应于使能信号的焊盘向半导体存储器件提供外部电压。该方法响应于参考电压电平而改变从高电压发生器输出的高电压电平。

3. 发明申请

US20100034031A1 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US20100034031A1
公开(公告)日：2010-02-11
申请号：US12461277
申请日：2009-08-06
申请人： Sang-Seok Kang , Hyung-Dong Kim
发明人： Sang-Seok Kang , Hyung-Dong Kim
IPC分类号： G11C5/14 , G11C7/00 , G11C7/02
CPC分类号： G11C11/406 , G11C5/147 , G11C11/40615 , G11C11/4074 , G11C2211/4068
摘要： A semiconductor memory device includes a voltage level selection unit configured to output a plurality of voltage level selection signals according to a fuse program in response to a self-refresh command signal and a reference voltage generator configured to receive a reference voltage and output a target reference voltage having a different voltage level depending on a normal mode or a self-refresh mode in response to the voltage level selection signals.
摘要翻译：半导体存储器件包括：电压电平选择单元，被配置为响应于自刷新命令信号，根据熔丝程序输出多个电压电平选择信号;以及参考电压发生器，被配置为接收参考电压并输出目标参考响应于电压电平选择信号，具有取决于正常模式或自刷新模式的不同电压电平的电压。

4. 发明申请

US20060114731A1 Method and apparatus for controlling a high voltage generator in a wafer burn-in test 有权
标题翻译：用于在晶片老化测试中控制高压发生器的方法和装置
公开(公告)号：US20060114731A1
公开(公告)日：2006-06-01
申请号：US11327104
申请日：2006-01-05
申请人： Choong-Sun Park , Hyung-Dong Kim , Sang-Seok Kang , Jong-Hyun Choi , Yong-Hwan Jung
发明人： Choong-Sun Park , Hyung-Dong Kim , Sang-Seok Kang , Jong-Hyun Choi , Yong-Hwan Jung
IPC分类号： G11C7/06 , G11C5/14
CPC分类号： G11C5/145 , G11C5/146 , G11C29/006 , G11C29/02 , G11C29/021 , G11C29/12005 , G11C29/1201
摘要： The invention relates to a method and apparatus for controlling a high voltage generator during wafer burn-in. The method includes generating an enable signal for enabling a high voltage generator responsive to a mode signal, e.g., a wafer burn-in test mode. The method provides an external voltage to a semiconductor memory device through a pad responsive to the enable signal. The method varies a high voltage level being output from the high voltage generator in response to a reference voltage level.
摘要翻译：本发明涉及一种用于在晶片老化期间控制高压发生器的方法和装置。该方法包括产生响应于模式信号的高电压发生器的使能信号，例如晶片老化测试模式。该方法通过响应于使能信号的焊盘向半导体存储器件提供外部电压。该方法响应于参考电压电平而改变从高电压发生器输出的高电压电平。

5. 发明授权

US08208317B2 Semiconductor memory device 有权
标题翻译：半导体存储器件
公开(公告)号：US08208317B2
公开(公告)日：2012-06-26
申请号：US12461277
申请日：2009-08-06
申请人： Sang-Seok Kang , Hyung-Dong Kim
发明人： Sang-Seok Kang , Hyung-Dong Kim
IPC分类号： G11C5/14 , G11C7/00 , G11C7/02
CPC分类号： G11C11/406 , G11C5/147 , G11C11/40615 , G11C11/4074 , G11C2211/4068
摘要： A semiconductor memory device includes a voltage level selection unit configured to output a plurality of voltage level selection signals according to a fuse program in response to a self-refresh command signal and a reference voltage generator configured to receive a reference voltage and output a target reference voltage having a different voltage level depending on a normal mode or a self-refresh mode in response to the voltage level selection signals.
摘要翻译：半导体存储器件包括：电压电平选择单元，被配置为响应于自刷新命令信号，根据熔丝程序输出多个电压电平选择信号;以及参考电压发生器，被配置为接收参考电压并输出目标参考响应于电压电平选择信号，具有取决于正常模式或自刷新模式的不同电压电平的电压。

6. 发明公开

US20240029784A1 DRAM DEVICE AND ODT RESISTOR VALUE ADJUSTMENT METHOD AND COMPUTER PROGRAM FOR THE SAME 审中-公开
公开(公告)号：US20240029784A1
公开(公告)日：2024-01-25
申请号：US18476475
申请日：2023-09-28
申请人： Sang-Seok Kang , Young-Hee Jung , Sun-Young LEE
发明人： Sang-Seok Kang , Young-Hee Jung , Sun-Young LEE
IPC分类号： G11C11/4093 , G11C5/04 , G11C11/4096 , G11C11/408
CPC分类号： G11C11/4093 , G11C5/04 , G11C11/4096 , G11C11/4082 , G11C11/4076
摘要： Disclosed are a dynamic random access memory (DRAM) device, an on-die termination (ODT) resistance value setting method thereof, and a computer program therefor, and the DRAM device includes at least one DRAM module and a memory controller configured to measure a resistance value of an ODT resistor corresponding to one of a rank included in the DRAM module, a chipset included in the rank, and a DQ included in the chipset and set a resistance value of an ODT resistor corresponding to one of the rank, the chipset, and the DQ on the basis of the measured resistance value.

7. 发明授权

US07675316B2 Semiconductor memory device including on die termination circuit and on die termination method thereof 失效
标题翻译：半导体存储器件包括管芯端接电路及其管芯端接方法
公开(公告)号：US07675316B2
公开(公告)日：2010-03-09
申请号：US11429365
申请日：2006-05-05
申请人： Jong-Hyoung Lim , Sang-Seok Kang
发明人： Jong-Hyoung Lim , Sang-Seok Kang
IPC分类号： H03K17/16
CPC分类号： G11C7/1078 , G11C5/063 , G11C7/1048 , G11C7/1057 , G11C7/1084
摘要： A semiconductor memory device is provided. The device includes an on die termination circuit controlling a termination resistance value by detecting a phase change of a signal inputted through a pad. Additionally, the on die termination circuit changes the termination resistance value when an identical phase signal is inputted during n (n is positive integer) periods of a clock signal.
摘要翻译：提供半导体存储器件。该器件包括通过检测通过焊盘输入的信号的相位变化来控制终端电阻值的芯片上终端电路。此外，当在时钟信号的n（n为正整数）周期期间输入相同的相位信号时，导线端接电路改变终端电阻值。

8. 发明申请

US20080052567A1 Semiconductor memory device and method thereof 有权
标题翻译：半导体存储器件及其方法
公开(公告)号：US20080052567A1
公开(公告)日：2008-02-28
申请号：US11730273
申请日：2007-03-30
申请人： Jong-Hyoung Lim , Sang-Seok Kang
发明人： Jong-Hyoung Lim , Sang-Seok Kang
IPC分类号： G11C29/00
CPC分类号： G11C7/1078 , G11C7/1006 , G11C7/1096 , G11C11/4096
摘要： A semiconductor memory device and method thereof are provided. The example method may be directed to performing a memory operation in a semiconductor memory device, and may include receiving data and a data masking signal corresponding to at least a portion of the received data, the received data scheduled to be written into memory in response to a write command and the data masking signal configured to block the at least a portion of the received data from being written into the memory and configuring timing parameters differently for each of the received data and the data masking signal so as to execute the write command without writing the at least a portion of the received data into the memory.
摘要翻译：提供一种半导体存储器件及其方法。示例性方法可以涉及在半导体存储器件中执行存储器操作，并且可以包括接收对应于所接收的数据的至少一部分的数据和数据屏蔽信号，响应于写入命令和数据屏蔽信号，被配置为阻止所接收的数据的至少一部分被写入到存储器中，并且针对每个接收的数据和数据屏蔽信号配置不同的定时参数，从而执行写入命令而没有将所接收的数据的至少一部分写入存储器。

9. 发明授权

US06972612B2 Semiconductor device with malfunction control circuit and controlling method thereof 有权
标题翻译：具有故障控制电路的半导体器件及其控制方法
公开(公告)号：US06972612B2
公开(公告)日：2005-12-06
申请号：US10277573
申请日：2002-10-21
申请人： Sang-Seok Kang , Kyeong-Seon Shin , Ki-Sang Kang
发明人： Sang-Seok Kang , Kyeong-Seon Shin , Ki-Sang Kang
IPC分类号： G01R31/30 , G11C17/18 , G11C29/00 , H01L23/544 , H01H37/76 , H01H85/00
CPC分类号： G01R31/30 , G11C17/18 , G11C29/006 , G11C2029/4402 , H01L23/544 , H01L2223/5444 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit of a semiconductor device has a chip malfunction controlling circuit embedded in a chip. The circuit comprises a fusing part, to which a cutting will be made in the manufacturing process according to the result of the discrimination of a defect in a chip, with one end thereof being connected to a first power terminal. A signal generating part is connected to the other end of the fusing part, and to a second power terminal. The signal generating part generates a discrimination signal of discriminating whether the chip is defective or not, by whether the fusing part has been cut or not. The discrimination signal is supplied to at least one internal function circuit, and inhibits its operation if the fusing part has been cut. Furthermore, the chip malfunction controlling method comprises generating a discrimination signal that has a first state if a test fuse has been cut and a second state if the test fuse has not been cut. Then the discrimination signal is applied to the chip internal function circuits, to inhibit their operation if the fuse has been cut.
摘要翻译：半导体器件的集成电路具有嵌入芯片中的芯片故障控制电路。该电路包括一个定影部分，根据鉴别芯片中的缺陷的结果，在制造过程中将进行切割，其一端连接到第一电源端子。信号产生部分连接到定影部分的另一端，并连接到第二电源端子。信号产生部分通过定影部分是否被切断来产生鉴别芯片是否有故障的鉴别信号。鉴别信号被提供给至少一个内部功能电路，并且如果定影部件被切割，则禁止其操作。此外，芯片故障控制方法包括：如果测试保险丝已被切断，则产生具有第一状态的判别信号，如果测试保险丝未被切断，则产生第二状态。然后，识别信号被施加到芯片内部功能电路，如果保险丝被切断，则抑制它们的操作。

10. 发明授权

US06658612B1 Test signal generating circuit of a semiconductor device with pins receiving signals of multiple voltage levels and method for invoking test modes 失效
标题翻译：具有接收多电压电平信号的引脚的半导体器件的测试信号发生电路和用于调用测试模式的方法
公开(公告)号：US06658612B1
公开(公告)日：2003-12-02
申请号：US09550944
申请日：2000-04-17
申请人： Cheol-Hong Park , Sang-Seok Kang , Jong-Hyun Choi
发明人： Cheol-Hong Park , Sang-Seok Kang , Jong-Hyun Choi
IPC分类号： G01R3128
CPC分类号： G11C29/46 , G01R31/31813 , G11C2029/5004
摘要： A signal generating circuit of a semiconductor device comprises n input test pins for receiving respective coded input signals. At least one of the input signals is coded in more than two possible levels, such as 3 levels or four levels. The device also includes an indicator I/O signal generators, each coupled respectively with an associated input test pin. Each indicator signal generator generates two-level indicator signals in response to the coded input signal received by its associated input test pin. A decoder receives the indicator signals to produce decoded signals, and a mode selecting circuit generates mode selecting signals with the decoded signals responsive to mode setting signals. Each indicator signal generators outputs a regular signal when the input test signal is an ordinary low, a control signal when the input test signal is an ordinary high, and a higher first level signal when the input test signal is a super high. If more than three levels are used, the indicator signal generator further generates corresponding signals for these higher values.
摘要翻译：半导体器件的信号发生电路包括用于接收各个编码输入信号的n个输入测试引脚。输入信号中的至少一个以多于两个可能的级别编码，例如3级或4级。该装置还包括一个指示器I / O信号发生器，每个发生器分别与相关的输入测试引脚相连。每个指示信号发生器响应于由其相关输入测试引脚接收到的编码输入信号产生两电平指示信号。解码器接收指示信号以产生解码信号，并且模式选择电路响应于模式设置信号产生具有解码信号的模式选择信号。当输入测试信号为普通低电平时，指示信号发生器输出常规信号，当输入测试信号为普通高电平时输入控制信号，当输入测试信号为超高电平时，输出高电平信号。如果使用三个以上的电平，指示信号发生器进一步产生这些较高值的相应信号。

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