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1. 发明授权

US07173872B2 Method and apparatus for controlling a high voltage generator in a wafer burn-in test 有权
标题翻译：用于在晶片老化测试中控制高压发生器的方法和装置
公开(公告)号：US07173872B2
公开(公告)日：2007-02-06
申请号：US11327104
申请日：2006-01-05
申请人： Choong-Sun Park , Hyung-Dong Kim , Sang-Seok Kang , Jong-Hyun Choi , Yong-Hwan Jung
发明人： Choong-Sun Park , Hyung-Dong Kim , Sang-Seok Kang , Jong-Hyun Choi , Yong-Hwan Jung
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C5/145 , G11C5/146 , G11C29/006 , G11C29/02 , G11C29/021 , G11C29/12005 , G11C29/1201
摘要： The invention relates to a method and apparatus for controlling a high voltage generator during wafer burn-in. The method includes generating an enable signal for enabling a high voltage generator responsive to a mode signal, e.g., a wafer burn-in test mode. The method provides an external voltage to a semiconductor memory device through a pad responsive to the enable signal. The method varies a high voltage level being output from the high voltage generator in response to a reference voltage level.
摘要翻译：本发明涉及一种用于在晶片老化期间控制高压发生器的方法和装置。该方法包括产生响应于模式信号的高电压发生器的使能信号，例如晶片老化测试模式。该方法通过响应于使能信号的焊盘向半导体存储器件提供外部电压。该方法响应于参考电压电平而改变从高电压发生器输出的高电压电平。

2. 发明授权

US07016248B2 Method and apparatus for controlling a high voltage generator in a wafer burn-in test 有权
标题翻译：用于在晶片老化测试中控制高压发生器的方法和装置
公开(公告)号：US07016248B2
公开(公告)日：2006-03-21
申请号：US10423505
申请日：2003-04-25
申请人： Choong-Sun Park , Hyung-Dong Kim , Sang-Seok Kang , Jong-Hyun Choi , Yong-Hwan Jung
发明人： Choong-Sun Park , Hyung-Dong Kim , Sang-Seok Kang , Jong-Hyun Choi , Yong-Hwan Jung
IPC分类号： G11C7/00
CPC分类号： G11C5/145 , G11C5/146 , G11C29/006 , G11C29/02 , G11C29/021 , G11C29/12005 , G11C29/1201
摘要： The invention relates to a method and apparatus for controlling a high voltage generator during wafer burn-in. The method includes generating an enable signal for enabling a high voltage generator responsive to a mode signal, e.g., a wafer bum-in test mode. The method provides an external voltage to a semiconductor memory device through a pad responsive to the enable signal. The method varies a high voltage level being output from the high voltage generator in response to a reference voltage level.
摘要翻译：本发明涉及一种用于在晶片老化期间控制高压发生器的方法和装置。该方法包括产生响应于模式信号（例如，晶片烧入测试模式）使得高电压发生器能够使能的使能信号。该方法通过响应于使能信号的焊盘向半导体存储器件提供外部电压。该方法响应于参考电压电平而改变从高电压发生器输出的高电压电平。

3. 发明申请

US20060114731A1 Method and apparatus for controlling a high voltage generator in a wafer burn-in test 有权
标题翻译：用于在晶片老化测试中控制高压发生器的方法和装置
公开(公告)号：US20060114731A1
公开(公告)日：2006-06-01
申请号：US11327104
申请日：2006-01-05
申请人： Choong-Sun Park , Hyung-Dong Kim , Sang-Seok Kang , Jong-Hyun Choi , Yong-Hwan Jung
发明人： Choong-Sun Park , Hyung-Dong Kim , Sang-Seok Kang , Jong-Hyun Choi , Yong-Hwan Jung
IPC分类号： G11C7/06 , G11C5/14
CPC分类号： G11C5/145 , G11C5/146 , G11C29/006 , G11C29/02 , G11C29/021 , G11C29/12005 , G11C29/1201
摘要： The invention relates to a method and apparatus for controlling a high voltage generator during wafer burn-in. The method includes generating an enable signal for enabling a high voltage generator responsive to a mode signal, e.g., a wafer burn-in test mode. The method provides an external voltage to a semiconductor memory device through a pad responsive to the enable signal. The method varies a high voltage level being output from the high voltage generator in response to a reference voltage level.
摘要翻译：本发明涉及一种用于在晶片老化期间控制高压发生器的方法和装置。该方法包括产生响应于模式信号的高电压发生器的使能信号，例如晶片老化测试模式。该方法通过响应于使能信号的焊盘向半导体存储器件提供外部电压。该方法响应于参考电压电平而改变从高电压发生器输出的高电压电平。

4. 发明申请

US20100246300A1 SEMICONDUCTOR MEMORY DEVICES INCLUDING BURN-IN TEST CIRCUITS 有权
标题翻译：包含烧录电路的半导体存储器件
公开(公告)号：US20100246300A1
公开(公告)日：2010-09-30
申请号：US12731749
申请日：2010-03-25
申请人： Jong-Hyun Choi , Sang-Seok Kang
发明人： Jong-Hyun Choi , Sang-Seok Kang
IPC分类号： G11C29/00 , G11C7/12
CPC分类号： G11C29/02 , G11C11/401 , G11C29/025 , G11C29/12005 , G11C2029/1204
摘要： A semiconductor memory device includes a memory cell array including a first memory cell coupled to a first bit line and a word line, and a second memory cell coupled to a second bit line and the word line and disposed adjacent to the first memory cell. A controller circuit is configured to provide first and second precharge voltages to the first and second bitlines, respectively. The first precharge voltage is provided as a positive power supply voltage and the second precharge voltage is provided as a negative stress voltage during a burn-in test operation. Related methods of operation are also discussed.
摘要翻译：半导体存储器件包括存储单元阵列，该存储单元阵列包括耦合到第一位线和字线的第一存储器单元，以及耦合到第二位线和字线并且邻近第一存储单元设置的第二存储单元。控制器电路被配置为分别向第一和第二位线提供第一和第二预充电电压。第一预充电电压被提供为正电源电压，并且在老化测试操作期间将第二预充电电压设置为负应力电压。还讨论了相关的操作方法。

5. 发明授权

US06490222B2 Decoding circuit for controlling activation of wordlines in a semiconductor memory device 失效
标题翻译：用于控制半导体存储器件中的字线激活的解码电路
公开(公告)号：US06490222B2
公开(公告)日：2002-12-03
申请号：US09875371
申请日：2001-06-05
申请人： Jong-Hyun Choi , Sang-Seok Kang , Jei-Hwan Yoo , Jae-Hoon Joo
发明人： Jong-Hyun Choi , Sang-Seok Kang , Jei-Hwan Yoo , Jae-Hoon Joo
IPC分类号： G11C800
CPC分类号： G11C8/08 , G11C8/14 , G11C29/34
摘要： A semiconductor memory device of the invention includes: main decoders for generating wordline enable signals in response to first decoding signals, a first precharge signal, and a second precharge signal; wordline drivers for wordline drive signals in response to the wordline enable signals and second decoding signals; and a circuit for generating the second precharge signal in response to a command signal. The wordline drive signals are inactivated in sequence in response to the first decoding signals and the second precharge signal, in order to reducing ground noises.
摘要翻译：本发明的半导体存储器件包括：主解码器，用于响应于第一解码信号，第一预充电信号和第二预充电信号产生字线使能信号; 响应于字线使能信号和第二解码信号的字线驱动信号的字线驱动器; 以及用于响应于命令信号产生第二预充电信号的电路。响应于第一解码信号和第二预充电信号，字线驱动信号被顺序地去激活，以便减少地面噪声。

6. 发明授权

US06438042B1 Arrangement of bitline boosting capacitor in semiconductor memory device 有权
标题翻译：半导体存储器件中位线升压电容器的布置
公开(公告)号：US06438042B1
公开(公告)日：2002-08-20
申请号：US09879076
申请日：2001-06-11
申请人： Sang-Seok Kang , Yun-Sang Lee , Jong-Hyun Choi , Jae-Hoon Joo
发明人： Sang-Seok Kang , Yun-Sang Lee , Jong-Hyun Choi , Jae-Hoon Joo
IPC分类号： G11C700
CPC分类号： G11C11/4094 , G11C7/12 , H01L27/10897
摘要： A semiconductor memory device includes first and second isolation transistors for electrically connecting/isolating a pair of bitlines to/from a sense amplifier circuit, and a MOS transistor having a source region that is shared with one of sources of the first and second isolation transistors. The MOS transistor may be used as a bitline boosting capacitor.
摘要翻译：半导体存储器件包括第一和第二隔离晶体管，用于将一对位线与读出放大器电路电连接/隔离;以及MOS晶体管，其具有与第一和第二隔离晶体管的源极之一共享的源极区域。 MOS晶体管可以用作位线升压电容器。

7. 发明授权

US08441877B2 Semiconductor memory devices including burn-in test circuits 有权
标题翻译：半导体存储器件包括老化测试电路
公开(公告)号：US08441877B2
公开(公告)日：2013-05-14
申请号：US12731749
申请日：2010-03-25
申请人： Jong-Hyun Choi , Sang-Seok Kang
发明人： Jong-Hyun Choi , Sang-Seok Kang
IPC分类号： G11C7/00
CPC分类号： G11C29/02 , G11C11/401 , G11C29/025 , G11C29/12005 , G11C2029/1204
摘要： A semiconductor memory device includes a memory cell array including a first memory cell coupled to a first bit line and a word line, and a second memory cell coupled to a second bit line and the word line and disposed adjacent to the first memory cell. A controller circuit is configured to provide first and second precharge voltages to the first and second bitlines, respectively. The first precharge voltage is provided as a positive power supply voltage and the second precharge voltage is provided as a negative stress voltage during a burn-in test operation. Related methods of operation are also discussed.
摘要翻译：半导体存储器件包括存储单元阵列，该存储单元阵列包括耦合到第一位线和字线的第一存储器单元，以及耦合到第二位线和字线并且邻近第一存储单元设置的第二存储单元。控制器电路被配置为分别向第一和第二位线提供第一和第二预充电电压。第一预充电电压被提供为正电源电压，并且在老化测试操作期间将第二预充电电压设置为负应力电压。还讨论了相关的操作方法。

8. 发明授权

US07057217B2 Fuse arrangement and integrated circuit device using the same 失效
标题翻译：保险丝布置和集成电路器件使用相同
公开(公告)号：US07057217B2
公开(公告)日：2006-06-06
申请号：US10672035
申请日：2003-09-26
申请人： Sang-Seok Kang , Jong-Hyun Choi , Sang-Ki Hwang
发明人： Sang-Seok Kang , Jong-Hyun Choi , Sang-Ki Hwang
IPC分类号： H01L27/10
CPC分类号： G11C17/143 , G11C29/785 , H01L23/5258 , H01L2924/0002 , H01L2924/00
摘要： A fuse circuit according to the present invention includes first and second fuses, each of which has a first end and a second end. The first and second ends of the first fuse are connected in a straight line. The first end of the second fuse is spaced by a first interval from the first end of the first fuse, and the second end thereof is spaced by a second interval from the second end of the first fuse. The first ends of the first and second fuses have the same widths as those of the second ends thereof. Alternatively, the first ends of the first and second fuses have narrower widths that those of the second ends thereof.
摘要翻译：根据本发明的熔丝电路包括第一和第二熔丝，每个熔丝具有第一端和第二端。第一保险丝的第一端和第二端以直线连接。第二保险丝的第一端与第一保险丝的第一端隔开第一间隔，并且第二保险丝的第二端与第一保险丝的第二端隔开第二间隔。第一和第二熔断器的第一端具有与其第二端相同的宽度。或者，第一和第二熔断器的第一端的宽度比第二端的宽度窄。

9. 发明授权

US06658612B1 Test signal generating circuit of a semiconductor device with pins receiving signals of multiple voltage levels and method for invoking test modes 失效
标题翻译：具有接收多电压电平信号的引脚的半导体器件的测试信号发生电路和用于调用测试模式的方法
公开(公告)号：US06658612B1
公开(公告)日：2003-12-02
申请号：US09550944
申请日：2000-04-17
申请人： Cheol-Hong Park , Sang-Seok Kang , Jong-Hyun Choi
发明人： Cheol-Hong Park , Sang-Seok Kang , Jong-Hyun Choi
IPC分类号： G01R3128
CPC分类号： G11C29/46 , G01R31/31813 , G11C2029/5004
摘要： A signal generating circuit of a semiconductor device comprises n input test pins for receiving respective coded input signals. At least one of the input signals is coded in more than two possible levels, such as 3 levels or four levels. The device also includes an indicator I/O signal generators, each coupled respectively with an associated input test pin. Each indicator signal generator generates two-level indicator signals in response to the coded input signal received by its associated input test pin. A decoder receives the indicator signals to produce decoded signals, and a mode selecting circuit generates mode selecting signals with the decoded signals responsive to mode setting signals. Each indicator signal generators outputs a regular signal when the input test signal is an ordinary low, a control signal when the input test signal is an ordinary high, and a higher first level signal when the input test signal is a super high. If more than three levels are used, the indicator signal generator further generates corresponding signals for these higher values.
摘要翻译：半导体器件的信号发生电路包括用于接收各个编码输入信号的n个输入测试引脚。输入信号中的至少一个以多于两个可能的级别编码，例如3级或4级。该装置还包括一个指示器I / O信号发生器，每个发生器分别与相关的输入测试引脚相连。每个指示信号发生器响应于由其相关输入测试引脚接收到的编码输入信号产生两电平指示信号。解码器接收指示信号以产生解码信号，并且模式选择电路响应于模式设置信号产生具有解码信号的模式选择信号。当输入测试信号为普通低电平时，指示信号发生器输出常规信号，当输入测试信号为普通高电平时输入控制信号，当输入测试信号为超高电平时，输出高电平信号。如果使用三个以上的电平，指示信号发生器进一步产生这些较高值的相应信号。

10. 发明授权

US06459636B2 Mode selection circuit for semiconductor memory device 有权
公开(公告)号：US06459636B2
公开(公告)日：2002-10-01
申请号：US09838358
申请日：2001-04-19
申请人： Yun-Sang Lee , Sang-Seok Kang , Kyu-Nam Lim , Jong-Hyun Choi
发明人： Yun-Sang Lee , Sang-Seok Kang , Kyu-Nam Lim , Jong-Hyun Choi
IPC分类号： G11C700
CPC分类号： G11C29/46
摘要： A mode selection circuit for a semiconductor memory device includes a timing register for generating first and second control signals in response to a command signal and a first address signal, a programming control signal generator for generating third control signals in response to a second address signal and the first control signal, and a mode selection signal generator for generating mode selection signals in response to a master signal, the second control signal, and the third control signals, wherein the mode selection signals are activated in accordance with a sequential order of activation of the third control signals.

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