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1. 发明授权

US5910178A Method for controlling a message send in a packet-switched interconnection network 失效
标题翻译：用于控制在分组交换互连网络中发送的消息的方法
公开(公告)号：US5910178A
公开(公告)日：1999-06-08
申请号：US899552
申请日：1997-07-24
申请人： Sang Man Moh , Sang Seok Shin , Suk Han Yoon , Kee Wook Rim
发明人： Sang Man Moh , Sang Seok Shin , Suk Han Yoon , Kee Wook Rim
IPC分类号： H04L12/54 , H04L12/861 , H04L12/879 , H04L12/00 , G06F15/16
CPC分类号： H04L49/901 , H04L12/5693 , H04L49/90
摘要： The present invention discloses a method for controlling a message send in a packet-switched interconnection network, which incorporates a message send controller supporting an efficient message send and a dedicated hardware capable of maximizing a message send rate, taking the structural characteristics of the message-passing parallel computer system method into maximum considerations, thereby minimizing software and hardware overhead in sending a message and being capable of selecting a message send method in accordance with the message characteristics.
摘要翻译：本发明公开了一种用于控制分组交换互联网络中的消息发送的方法，其包括支持有效消息发送的消息发送控制器和能够最大化消息发送速率的专用硬件，采用消息发送的结构特征，通过并行计算机系统方法进行最大限度的考虑，从而最小化发送消息时的软件和硬件开销，并根据消息特性选择消息发送方法。

2. 发明授权

US6023732A Message transfer apparatus for controlling a message send in a packet switched interconnection network 失效
标题翻译：用于控制在分组交换互连网络中发送的消息的消息传送装置
公开(公告)号：US6023732A
公开(公告)日：2000-02-08
申请号：US899957
申请日：1997-07-24
申请人： Sang Man Moh , Sang Seok Shin , Suk Han Yoon , Kee Wook Rim
发明人： Sang Man Moh , Sang Seok Shin , Suk Han Yoon , Kee Wook Rim
IPC分类号： H04L12/54 , H04L12/861 , H04L12/879 , H04L12/00 , G06F15/16
CPC分类号： H04L49/901 , H04L12/5693 , H04L49/90
摘要： The present invention relates to a message-passing computer system and a packet-switched interconnection network. The message transfer apparatus in a packet-switched interconnection network includes a message send controller controlling a send procedure in which messages requested by a processor are sent via an output port, and a timer enabled by an output signal of the message send controller and generating a timeout signal. A buffer unit is connected to the message send controller and is composed of a message buffer having four buffers and a data buffer. A local bus controller connects the message send controller and the buffer unit to the local bus and controls a transfer request and a transfer response to the local bus. An output port controller connected to both the message send controller and the buffer unit controls the output port which sends a packet to an interconnection network.
摘要翻译：本发明涉及消息传递计算机系统和分组交换互连网络。分组交换互连网络中的消息传送装置包括控制发送过程的消息发送控制器，其中经由输出端口发送由处理器请求的消息，以及由消息发送控制器的输出信号启用的定时器，超时信号缓冲单元连接到消息发送控制器，并由具有四个缓冲器和数据缓冲器的消息缓冲器组成。本地总线控制器将消息发送控制器和缓冲器单元连接到本地总线，并控制传输请求和对本地总线的传输响应。连接到消息发送控制器和缓冲器单元的输出端口控制器控制向互连网络发送分组的输出端口。

3. 发明授权

US06415361B1 Apparatus for controlling cache by using dual-port transaction buffers 有权
标题翻译：用于通过使用双端口事务缓冲器来控制高速缓存的装置
公开(公告)号：US06415361B1
公开(公告)日：2002-07-02
申请号：US09487348
申请日：2000-01-19
申请人： Sang Man Moh , Jong Seok Han , An Do Ki , Woo Jong Hahn , Suk Han Yoon , Gil Rok Oh
发明人： Sang Man Moh , Jong Seok Han , An Do Ki , Woo Jong Hahn , Suk Han Yoon , Gil Rok Oh
IPC分类号： G06F1200
CPC分类号： G06F12/0828 , G06F2212/2542
摘要： An apparatus for controlling a cache in a computing node, which is located between a node bus and an interconnection network to perform a cache coherence protocol, includes: a node bus interface for interfacing with the node bus; an interconnection network interface for interfacing with the interconnection network; a cache control logic means for controlling the cache to perform the cache coherence protocol; bus-side dual-port transaction buffers coupled between said node bus interface and said cache control logic means for buffering transaction requested and replied from or to local processors contained in the computing node; and network-side dual-port transaction buffers coupled between said interconnection network interface and said cache control logic for buffering transaction requested and replied from or to remote processors contained in another computing node coupled to the interconnection network.
摘要翻译：一种用于控制位于节点总线和互连网络之间以执行高速缓存一致性协议的计算节点中的高速缓存的装置包括：用于与节点总线接口的节点总线接口; 用于与互连网络对接的互连网络接口; 用于控制高速缓存以执行高速缓存一致性协议的高速缓存控制逻辑装置; 耦合在所述节点总线接口和所述高速缓存控制逻辑装置之间的总线端双端口事务缓冲器，用于缓冲从计算节点中包含的本地处理器请求和应答的事务; 以及耦合在所述互连网络接口和所述高速缓存控制逻辑之间的网络侧双端口事务缓冲器，用于缓存从耦合到互连网络的另一个计算节点中包含的远程处理器请求和回复的事务。

4. 发明授权

US06505289B1 Apparatus and method for interconnecting 3-link nodes and parallel processing apparatus using the same 有权
标题翻译：用于互连3链路节点的装置和方法以及使用其的并行处理装置
公开(公告)号：US06505289B1
公开(公告)日：2003-01-07
申请号：US09475049
申请日：1999-12-30
申请人： Jong Seok Han , Sang Man Moh , Woo Jong Hahn , Suk Han Yoon
发明人： Jong Seok Han , Sang Man Moh , Woo Jong Hahn , Suk Han Yoon
IPC分类号： G06F1300
CPC分类号： G06F15/17337
摘要： The present invention relates to a node connection apparatus. The 3-link node interconnection apparatus and parallel processing apparatus using the same confirm expanding nodes freely, only using fixed three connecting links, and are suitable to normal packaging method because of easy dividing into 2n (n>1) nodes. The apparatuses comprise the following nodes. The first node has three links connected to other nodes respectively. The second node has three links, one links of them is connected to the first node, and the other two links are in charge of connection of X+ direction, X− direction. The third node has three links, one link of them is connected to the first node, and the other two links are in charge of connection of Y+ direction, Y− direction. The fourth node has three links, one link of them is connected to the first node, and the other two links are in charge of connection of Z+ direction, Z− direction.
摘要翻译：节点连接装置技术领域本发明涉及节点连接装置。 3链节点互连设备和使用该链路节点的并行处理设备可以自由地确定扩展节点，只使用固定的三个连接链路，由于容易划分成2n（n> 1）个节点，因此适合正常的封装方法。这些装置包括以下节点。第一个节点分别连接到其他节点的三个链路。第二节点有三个链路，一个链路连接到第一个节点，另外两个链路负责连接X +方向，X方向。第三节点有三个链路，一个链路连接到第一个节点，另外两个链路负责Y +方向，Y方向的连接。第四个节点有三个链路，一个链路连接到第一个节点，另外两个链路负责Z +方向，Z方向的连接。

5. 发明授权

US6108766A Structure of processor having a plurality of main processors and sub processors, and a method for sharing the sub processors 失效
标题翻译：具有多个主处理器和子处理器的处理器的结构以及用于共享子处理器的方法
公开(公告)号：US6108766A
公开(公告)日：2000-08-22
申请号：US131891
申请日：1998-08-10
申请人： Woo Jong Hahn , Kyong Park , Suk Han Yoon
发明人： Woo Jong Hahn , Kyong Park , Suk Han Yoon
IPC分类号： G06F15/16 , G06F9/30 , G06F9/318 , G06F9/38 , G06F12/08 , G06F15/78
CPC分类号： G06F9/3826 , G06F12/0888 , G06F15/7864 , G06F9/30116 , G06F9/30123 , G06F9/3017 , G06F9/3824 , G06F9/3836 , G06F9/3838 , G06F9/3863 , G06F9/3877
摘要： The present invention relates to a structure of processor having a plurality of main processors and sub processors, and a method for sharing the sub processors, wherein a method is used for preserving a state of a register file by using a shadow register file when main processor inputs an instruction of the sub processor in case that an exceptional situation happens under processing of an instruction of sub processor and for rolling back thereafter the preserved state in case there is an information of occurrence of the exceptional situation from the sub processor. Also, in order to solve a problem that cache efficiency is reduced due to the use of a first cache which is relatively small and frequently used, there is suggested a first cache bypassing function. Further, in order to solve a problem that its processing speed is reduced when the main processor transfers instructions in sub processor, it is possible to improve the processors' parallelism and its efficiency by providing an extra register file.
摘要翻译：本发明涉及具有多个主处理器和子处理器的处理器的结构以及用于共享子处理器的方法，其中使用一种方法来在主处理器上使用影子寄存器文件来保留寄存器文件的状态在处理子处理器的处理中发生异常情况的情况下输入子处理器的指令，并且在存在来自子处理器的异常情况的发生信息的情况下，将其保存在保存状态之后。此外，为了解决由于使用相对小且频繁使用的第一高速缓存而导致的高速缓存效率降低的问题，提出了第一高速缓存旁路功能。此外，为了解决当主处理器在子处理器中传送指令时其处理速度降低的问题，可以通过提供额外的寄存器文件来提高处理器的并行性及其效率。

6. 发明授权

US6138234A Node booting method in high-speed parallel computer 有权
标题翻译：节点启动方法在高速并行计算机中
公开(公告)号：US6138234A
公开(公告)日：2000-10-24
申请号：US139726
申请日：1998-08-31
申请人： Jae Kyung Lee , Hae Jin Kim , Suk Han Yoon , Chee Hang Park
发明人： Jae Kyung Lee , Hae Jin Kim , Suk Han Yoon , Chee Hang Park
IPC分类号： G06F15/16 , G06F9/445
CPC分类号： G06F15/177 , G06F9/4405
摘要： There is disclosed a node booting method in a high-speed parallel computer. Other than the method in which the system using a conventional network down loads the operating system kernel image from the boot server, the method according to the present invention provides an environment by which a boot can be progressed in parallel and a boot progress state can be monitored through a console terminal, thus improving a boot speed. The node booting method according to the present invention is comprised of a first step of finding a logical boot path using a node construction table managed by a firmware; a second step of determining boot subject nodes so that copy of an operating system kernel image can be made simultaneously; a third step of copying effective portions of the operating system loaded at the memories onto the subject nodes; a fourth step of informing a boot node of the node state and to display the boot progress state on a console terminal at the start and end time of the booting; and a fifth step of simultaneously starting execution at the remaining portions of the copied operating system when the kernel image are completely copied onto all the nodes.
摘要翻译：在高速并行计算机中公开了节点引导方法。除了使用传统网络的系统下载方法从引导服务器加载操作系统内核映像之外，根据本发明的方法提供了可以并行进行引导并且引导进程状态可以是通过控制台终端监控，从而提高启动速度。根据本发明的节点引导方法包括：使用由固件管理的节点构造表找到逻辑引导路径的第一步骤; 确定引导对象节点的第二步骤，使得可以同时进行操作系统内核映像的拷贝; 将加载在存储器上的操作系统的有效部分复制到对象节点上的第三步骤; 在启动的开始和结束时间，通知引导节点节点状态并在控制台终端上显示引导进程状态的第四步骤; 以及当内核图像被完全复制到所有节点上时，在复制的操作系统的其余部分同时开始执行的第五步骤。

7. 发明授权

US06314487B1 Adaptive routing controller of a crossbar core module used in a crossbar routing switch 失效
标题翻译：用于交叉开关的交叉开关核心模块的自适应路由控制器
公开(公告)号：US06314487B1
公开(公告)日：2001-11-06
申请号：US09209429
申请日：1998-12-11
申请人： Jong Seok Hahn , Won Sae Sim , Woo Jong Hahn , Suk Han Yoon
发明人： Jong Seok Hahn , Won Sae Sim , Woo Jong Hahn , Suk Han Yoon
IPC分类号： G06F1300
CPC分类号： G06F13/364
摘要： The present invention relates to a routing control apparatus for performing a round robin arbitration and an adaptive routing control. The present invention relates to a routing controller for performing an arbitration and a routing control which are nucleus functions of the crossbar routing switch and, in particular, to a normal routing controller unit for performing a priority based round robin arbitration and an adaptive routing controller unit for performing an adaptive routing control by adding an adaptive routing switch logic to the normal routing controller.
摘要翻译：本发明涉及一种用于执行循环仲裁和自适应路由控制的路由控制装置。本发明涉及一种用于执行仲裁和路由控制的路由选择控制，该路由控制是交叉开关路由交换机的核心功能，特别是涉及用于执行基于优先级的循环仲裁的正常路由控制器单元和自适应路由控制器单元用于通过将自适应路由交换逻辑添加到正常路由控制器来执行自适应路由控制。

8. 发明授权

US6052822A Fast destaging method using parity engine 失效
标题翻译：使用奇偶校验引擎的快速降级方法
公开(公告)号：US6052822A
公开(公告)日：2000-04-18
申请号：US141094
申请日：1998-08-26
申请人： Jin Pyo Kim , Joong Bae Kim , Yong Yeon Kim , Suk Han Yoon
发明人： Jin Pyo Kim , Joong Bae Kim , Yong Yeon Kim , Suk Han Yoon
IPC分类号： G06F11/00 , G06F11/10 , G06F12/08 , H03M13/00
CPC分类号： G06F11/1076 , G06F12/0866 , G06F12/0804 , G06F2211/1009 , G06F2211/1059 , G06F2212/312
摘要： The present invention relates to the fast destaging method using a parity engine, and more particularly to the fast destaging method for constituting and administering the cache of disk array in order to minimize lowering of write performance which occurs in high-speed disk array controller using VRAM parity engine.According to the invention, the disk cache is composed of the read cache, the write cache and the destaging cache. The write caching is processed as being divided into the write cache and the destaging cache. The destaging cache, which has just one more block for mid parity to its data block, uses less memory and enables the write cache to be allocated with more blocks, and thereby it can improve hit ratio of cache. Write requests are first stored on the write cache, and if the write cache is full, they move blocks that would be least used thereafter into the destaging cache. Once destaging is requested, it is practicable with one parity calculation and two write operations by selecting blocks that is least recently used.Also in destaging, block parity calculation can increase its speed and relieve the processor burden by using a VRAM based parity engine which has its dual ports.
摘要翻译：本发明涉及使用奇偶校验引擎的快速降级方法，更具体地说，涉及用于构成和管理磁盘阵列的高速缓存的快速分级方法，以便最小化在使用VRAM的高速磁盘阵列控制器中发生的写性能的降低奇偶校验引擎根据本发明，磁盘高速缓存由读高速缓存，写高速缓冲存储器和后期高速缓存组成。写缓存被处理为分为写缓存和后期缓存。对于其数据块而言，中间奇偶校验只有一个块的后台缓存使用较少的内存，并使写入缓存分配更多的块，从而可以提高高速缓存的命中率。写入请求首先存储在写入高速缓存中，如果写入高速缓存已满，它们将将最少使用的块移动到后续缓存中。一旦请求降级，通过选择最近最少使用的块，可以进行一次奇偶校验计算和两次写操作。同样在降级中，块奇偶校验计算可以通过使用具有双端口的基于VRAM的奇偶校验引擎来提高其速度并减轻处理器负担。

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