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1. 发明授权

US08618592B2 Dynamic random access memory (DRAM) cells and methods for fabricating the same 有权
标题翻译：动态随机存取存储器（DRAM）单元及其制造方法
公开(公告)号：US08618592B2
公开(公告)日：2013-12-31
申请号：US13098193
申请日：2011-04-29
申请人： Hyun-Jin Cho , Sang H. Dhong , Jung-Suk Goo , Gurupada Mandal
发明人： Hyun-Jin Cho , Sang H. Dhong , Jung-Suk Goo , Gurupada Mandal
IPC分类号： H01L21/00
CPC分类号： H01L27/10802 , H01L27/108 , H01L27/1082 , H01L27/1087 , H01L29/7841
摘要： A semiconductor memory cell is provided that includes a trench capacitor and an access transistor. The access transistor comprises a source region, a drain region, a gate structure overlying the trench capacitor, and an active body region that couples the drain region to the source region. The active body region directly contacts the trench capacitor.
摘要翻译：提供一种包括沟槽电容器和存取晶体管的半导体存储单元。存取晶体管包括源区域，漏极区域，覆盖沟槽电容器的栅极结构以及将漏极区域耦合到源极区域的有源体区域。有源体区域直接接触沟槽电容器。

2. 发明授权

US07977172B2 Dynamic random access memory (DRAM) cells and methods for fabricating the same 有权
标题翻译：动态随机存取存储器（DRAM）单元及其制造方法
公开(公告)号：US07977172B2
公开(公告)日：2011-07-12
申请号：US12330282
申请日：2008-12-08
申请人： Hyun-Jin Cho , Sang H. Dhong , Jung-Suk Goo , Gurupada Mandal
发明人： Hyun-Jin Cho , Sang H. Dhong , Jung-Suk Goo , Gurupada Mandal
IPC分类号： H01L21/84
CPC分类号： H01L27/10802 , H01L27/108 , H01L27/1082 , H01L27/1087 , H01L29/7841
摘要： A method for fabricating a memory cell is provided. A trench is formed in a semiconductor structure that comprises a semiconductor layer, and a trench capacitor is formed in the trench. Conductivity determining impurities are implanted into the semiconductor structure to create a well region in the semiconductor layer that is directly coupled to the trench capacitor. A gate structure is formed overlying a portion of the well region. Conductivity determining ions are then implanted into other portions of the well region to form a source region and a drain region, and to define an active body region between the source region and the drain region. The active body region directly contacts the trench capacitor.
摘要翻译：提供一种制造存储单元的方法。在包括半导体层的半导体结构中形成沟槽，并且在沟槽中形成沟槽电容器。将导电性确定杂质注入到半导体结构中以在直接耦合到沟槽电容器的半导体层中形成阱区。形成覆盖阱区域的一部分的栅极结构。然后将确定电导的离子注入阱区的其它部分以形成源区和漏区，并且在源区和漏区之间限定有源体区。有源体区域直接接触沟槽电容器。

3. 发明申请

US20100102867A1 SENSE AMPLIFIER BASED FLIP-FLOP 审中-公开
标题翻译：基于感光放大器的FLIP-FLOP
公开(公告)号：US20100102867A1
公开(公告)日：2010-04-29
申请号：US12258873
申请日：2008-10-27
申请人： Sang H. Dhong , Gurupada Mandal
发明人： Sang H. Dhong , Gurupada Mandal
IPC分类号： H03K3/289
CPC分类号： H03K3/356121
摘要： A sense amplifier based flip-flop having built-in logic functions. The flip-flop includes a first and second input circuits configured to cause complementary first and second logic values to be provided on first and second logic nodes, respectively. The flip-flop further includes a sense circuit configured to sense and capture the first and second logic values on first and second capture nodes, respectively, during an evaluation phase, and a precharge circuit configured to precharge the first and second logic node and the first and second capture nodes during a precharge phase. The flip-flop also includes a noise immunity circuit, configured to, during the evaluation phase, become active subsequent to the sense circuit capturing the first and second logic values, wherein, when activated, the noise immunity circuit prevents floating voltages on the first and second logic nodes.
摘要翻译：具有内置逻辑功能的基于读出放大器的触发器。触发器包括被配置为分别在第一和第二逻辑节点上提供互补的第一和第二逻辑值的第一和第二输入电路。触发器还包括感测电路，其被配置为在评估阶段期间分别在第一和第二捕获节点上感测和捕获第一和第二逻辑值，并且预充电电路被配置为对第一和第二逻辑节点和第一以及在预充电阶段期间的第二捕获节点。触发器还包括噪声抗扰电路，其被配置为在评估阶段期间在感测电路捕获第一和第二逻辑值之后变得有效，其中当激活时，抗噪声电路防止浮动电压在第一和第二逻辑值第二个逻辑节点。

4. 发明授权

US5635858A Zero-stopping incrementers 失效
标题翻译：零停止增量
公开(公告)号：US5635858A
公开(公告)日：1997-06-03
申请号：US476299
申请日：1995-06-07
申请人： Chin-An Chang , Sang H. Dhong
发明人： Chin-An Chang , Sang H. Dhong
IPC分类号： G06F7/50 , G06F7/505 , H03K19/21
CPC分类号： G06F7/5055
摘要： A zero-stopping incrementer operates on the recognition that half of all digital values that require incrementing will be even numbers; that is, the least significant bit (LSB) is a binary "0". Incrementing such a number merely requires changing the LSB from a binary "0" to a binary "1". For odd numbers (i.e., those where the LSB is a binary "1"), the zero-stopping incrementer searches for the first binary "0" beginning with the LSB. Once found, that binary "0" is changed to a binary "1" and all the binary "1s" preceding it are changed to binary "0s". No change is required to the higher order bits following the first binary "0". This operation is very fast, the worst case being the case when all the binary bits of the number to be incremented are "1s". Nevertheless, the process is significantly increased, especially for 64-bit numbers which are processed by modern superscalar microprocessors. As compared with conventional incrementers using an adder-like scheme, the zero-stopping incrementer is about three times faster with power consumption less than half of the conventional incrementers.
摘要翻译：零停止增量器对识别需要递增的所有数字值的一半将为偶数的操作。也就是说，最低有效位（LSB）是二进制“0”。增加这样的数字只需要将LSB从二进制“0”改变为二进制“1”。对于奇数（即，LSB是二进制“1”的那些），零停止增量器从LSB开始搜索第一个二进制“0”。一旦找到，该二进制“0”被改变为二进制“1”，并且其前面的所有二进制“1”被改变为二进制“0”。在第一个二进制“0”之后的高阶位不需要改变。这个操作是非常快的，最坏的情况就是要增加数字的所有二进制位都是“1s”的情况。然而，该过程显着增加，特别是对于由现代超标量微处理器处理的64位数字。与使用加法器方案的常规增量器相比，零停止增量器的功耗大约是常规加法器的一半的功耗的三倍。

5. 发明授权

US5453953A Bandgap voltage reference generator 失效
标题翻译：带隙电压基准发生器
公开(公告)号：US5453953A
公开(公告)日：1995-09-26
申请号：US281236
申请日：1994-07-27
申请人： Sang H. Dhong , Hyun J. Shin , Wei Hwang
发明人： Sang H. Dhong , Hyun J. Shin , Wei Hwang
IPC分类号： G11C11/407 , G11C5/14 , G11C8/08 , H01L21/822 , H01L27/04 , G05F3/24
CPC分类号： G11C8/08 , G11C5/147
摘要： A voltage regulator is provided for controlling an on-chip voltage generator which produces a boost voltage across a charge reservoir for supply to one input of a plurality of word line drivers in a memory array. The regulator is configured such that the charge reservoir voltage will track the power supply voltage and the difference between the power supply voltage and the charge reservoir voltage will be maintained substantially constant over a predefined power supply range. The voltage regulator includes a bandgap reference generator, a first differential circuit for producing a transition voltage from the reference voltage and the power supply voltage, a first transistor for comparing the power supply voltage with the boost voltage, a second transistor for comparing the transition voltage with the reference voltage and a latching comparator for equating the signal outputs from the first and second transistors so as to define a control signal for the on-chip voltage generator. Along with further specific details of the voltage regulator, a preferred bandgap reference generator is described.
摘要翻译：提供电压调节器用于控制片上电压发生器，其在电荷储存器两端产生升压电压，以供给存储器阵列中的多个字线驱动器的一个输入端。调节器被配置为使得电荷储存器电压将跟踪电源电压，并且电源电压和电荷储存器电压之间的差将在预定义的电源范围内保持基本上恒定。电压调节器包括带隙参考发生器，用于从参考电压和电源电压产生转换电压的第一差分电路，用于将电源电压与升压电压进行比较的第一晶体管，用于将转换电压与参考电压和锁存比较器，用于使来自第一和第二晶体管的信号输出相等，以便为片上电压发生器定义一个控制信号。除了电压调节器的进一步具体细节之外，还描述了优选的带隙参考发生器。

6. 发明授权

US5331189A Asymmetric multilayered dielectric material and a flash EEPROM using the same 失效
标题翻译：非对称多层电介质材料和使用其的闪存EEPROM
公开(公告)号：US5331189A
公开(公告)日：1994-07-19
申请号：US901281
申请日：1992-06-19
申请人： Kevin K. Chan , Sang H. Dhong , Dieter P. E. Kern , Young H. Lee
发明人： Kevin K. Chan , Sang H. Dhong , Dieter P. E. Kern , Young H. Lee
IPC分类号： H01L21/8247 , H01L27/115 , H01L29/51 , H01L29/788 , H01L29/792 , H01L29/78
CPC分类号： H01L29/513 , H01L27/115 , H01L29/7883
摘要： A flash EEPROM is produced comprising multiple MOS cells. In each cell, programming and erasing are performed through tunneling from the write gate to the floating gate and by tunneling from the floating gate to the erase gate, respectively. The directional dielectric employed is a multilayered structured (MLS) oxide, where thin oxide and thin polycrystalline silicon form alternating layers. The layering is asymmetric: that is, either the uppermost or bottommost layer is thicker than the other layers. As a result of this structure, the oxide exhibits directionality, that is, the tunneling is easier in one direction than the reverse direction, and significantly enhances the tunneling phenomena (tunneling current can be observed at as low as 4.7 V). In addition, the MLS oxide can be fabricated having different dielectric constants. The directionality, coupled with the separate write and erase gates, gives the new flash EEPROM cell a number of advantages: it is low-voltage operable, it is highly resistant to disturbance and has an easily scalable structure (that is, it can be made to operate at any given voltage within a specified scale).
摘要翻译：制造包括多个MOS单元的快闪EEPROM。在每个单元中，通过从写入栅极到浮动栅极的隧穿以及分别从浮置栅极到擦除栅极的隧穿来执行编程和擦除。所采用的定向电介质是多层结构（MLS）氧化物，其中薄的氧化物和薄的多晶硅形成交替层。分层是不对称的，也就是说，最上层或最底层比其他层厚。作为该结构的结果，氧化物具有方向性，即，在一个方向上的隧道比反向更容易，并且显着增强了隧道现象（隧道电流可以在低至4.7V）。此外，可以制造具有不同介电常数的MLS氧化物。方向性与单独的写入和擦除门相结合，为新的快闪EEPROM单元提供了许多优点：它是低电压可操作的，它具有高度的抗干扰性，并且具有易于扩展的结构（即可以制成在指定电压范围内工作）。

7. 发明授权

US5300800A Low leakage substrate plate DRAM cell 失效
标题翻译：低泄漏衬底板DRAM单元
公开(公告)号：US5300800A
公开(公告)日：1994-04-05
申请号：US966893
申请日：1992-10-26
申请人： Gary B. Bronner , Sang H. Dhong , Wei Hwang
发明人： Gary B. Bronner , Sang H. Dhong , Wei Hwang
IPC分类号： H01L21/76 , H01L21/8242 , H01L27/10 , H01L27/108 , H01L29/68 , H01L29/78 , H01L29/92
CPC分类号： H01L27/10829
摘要： Disclosed is a Dynamic Random Access Memory (DRAM) cell which includes a storage capacitor disposed in a trench formed in a semiconductor substrate and an access transistor disposed in a well which is opposite in conductivity type to that of the substrate and a buried oxide collar which surrounds an upper portion of the trench.
摘要翻译：公开了一种动态随机存取存储器（DRAM）单元，其包括设置在形成在半导体衬底中的沟槽中的存储电容器和设置在与衬底的导电类型相反的阱中的存取晶体管和埋入氧化物环，围绕沟槽的上部。

8. 发明授权

US5214603A Folded bitline, ultra-high density dynamic random access memory having access transistors stacked above trench storage capacitors 失效
标题翻译：折叠的双列，超高密度动态随机存取存储器存储上述堆叠存储电容器
公开(公告)号：US5214603A
公开(公告)日：1993-05-25
申请号：US740758
申请日：1991-08-05
申请人： Sang H. Dhong , Wei Hwang , Lewis M. Terman , Matthew R. Wordeman
发明人： Sang H. Dhong , Wei Hwang , Lewis M. Terman , Matthew R. Wordeman
IPC分类号： H01L27/04 , H01L21/822 , H01L21/8242 , H01L27/10 , H01L27/108
CPC分类号： H01L27/10832
摘要： A folded bitline DRAM cell is described which includes a trench capacitor and a planar-configured access transistor. The access transistor is stacked over the capacitor and has a first terminal connected thereto. The access transistor includes a planar-oriented gate. A first wordline has a minor surface in contact with the gate and a major surface that is oriented orthogonally to the gate. An insulating pedestal is positioned adjacent the gate and a passing wordline is positioned on the pedestal, the passing wordline having a major surface parallel to the first wordline. In another embodiment, the folded bitline DRAM cell includes a vertically oriented access transistor having one terminal formed on the upper extent of a contact to the trench capacitor, to provide optimum electrical connection thereto.

9. 发明授权

US5107459A Stacked bit-line architecture for high density cross-point memory cell array 失效
标题翻译：用于高密度交叉点存储器单元阵列的堆叠式位线结构
公开(公告)号：US5107459A
公开(公告)日：1992-04-21
申请号：US513315
申请日：1990-04-20
申请人： Christopher M. Chu , Sang H. Dhong , Wei Hwang , Nicky C-C. Lu
发明人： Christopher M. Chu , Sang H. Dhong , Wei Hwang , Nicky C-C. Lu
IPC分类号： H01L27/10 , G11C11/401 , G11C11/4097 , H01L21/8242 , H01L27/108
CPC分类号： H01L27/10841 , G11C11/4097
摘要： A stacked bit-line architecture utilizing high density cross-point memory arrays forms a DRAM semiconductor memory device. The true and complementary bit-line pairs connected to the respective memory cell arrays are formed in two metal layers, one above the other. A bit-line interconnector region is provided that uses a third interconnection layer together with the first and second layers to transpose the vertical stacking of each pair and to transpose the planar alignment of adjacent bit-line pairs. The DRAM memory cell array has a high density cross-point memory cell architecture that behaves electrically as a folded bit-line array.

10. 发明授权

US4910709A Complementary metal-oxide-semiconductor transistor and one-capacitor dynamic-random-access memory cell 失效
标题翻译：互补金属氧化物半导体晶体管和单电容器动态随机存取存储器单元
公开(公告)号：US4910709A
公开(公告)日：1990-03-20
申请号：US230410
申请日：1988-08-10
申请人： Sang H. Dhong , Nicky C. Lu , Walter H. Henkels
发明人： Sang H. Dhong , Nicky C. Lu , Walter H. Henkels
IPC分类号： G11C11/405 , G11C11/404 , G11C11/409 , H01L21/8238 , H01L21/8242 , H01L27/06 , H01L27/092 , H01L27/108
CPC分类号： G11C11/404 , H01L27/0688 , H01L27/108
摘要： A complementary MOS one-capacitor dynamic RAM cell which operates with a non-boosted wordline without a threshold loss problem and which includes one storage capacitor and n- and p-type transfer devices connected to the storage capacitor which function as two complementary transistor devices having gates controlled by complementary signals on the RAM wordlines.

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