专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US08618592B2 Dynamic random access memory (DRAM) cells and methods for fabricating the same 有权
标题翻译：动态随机存取存储器（DRAM）单元及其制造方法
公开(公告)号：US08618592B2
公开(公告)日：2013-12-31
申请号：US13098193
申请日：2011-04-29
申请人： Hyun-Jin Cho , Sang H. Dhong , Jung-Suk Goo , Gurupada Mandal
发明人： Hyun-Jin Cho , Sang H. Dhong , Jung-Suk Goo , Gurupada Mandal
IPC分类号： H01L21/00
CPC分类号： H01L27/10802 , H01L27/108 , H01L27/1082 , H01L27/1087 , H01L29/7841
摘要： A semiconductor memory cell is provided that includes a trench capacitor and an access transistor. The access transistor comprises a source region, a drain region, a gate structure overlying the trench capacitor, and an active body region that couples the drain region to the source region. The active body region directly contacts the trench capacitor.
摘要翻译：提供一种包括沟槽电容器和存取晶体管的半导体存储单元。存取晶体管包括源区域，漏极区域，覆盖沟槽电容器的栅极结构以及将漏极区域耦合到源极区域的有源体区域。有源体区域直接接触沟槽电容器。

2. 发明授权

US07977172B2 Dynamic random access memory (DRAM) cells and methods for fabricating the same 有权
标题翻译：动态随机存取存储器（DRAM）单元及其制造方法
公开(公告)号：US07977172B2
公开(公告)日：2011-07-12
申请号：US12330282
申请日：2008-12-08
申请人： Hyun-Jin Cho , Sang H. Dhong , Jung-Suk Goo , Gurupada Mandal
发明人： Hyun-Jin Cho , Sang H. Dhong , Jung-Suk Goo , Gurupada Mandal
IPC分类号： H01L21/84
CPC分类号： H01L27/10802 , H01L27/108 , H01L27/1082 , H01L27/1087 , H01L29/7841
摘要： A method for fabricating a memory cell is provided. A trench is formed in a semiconductor structure that comprises a semiconductor layer, and a trench capacitor is formed in the trench. Conductivity determining impurities are implanted into the semiconductor structure to create a well region in the semiconductor layer that is directly coupled to the trench capacitor. A gate structure is formed overlying a portion of the well region. Conductivity determining ions are then implanted into other portions of the well region to form a source region and a drain region, and to define an active body region between the source region and the drain region. The active body region directly contacts the trench capacitor.
摘要翻译：提供一种制造存储单元的方法。在包括半导体层的半导体结构中形成沟槽，并且在沟槽中形成沟槽电容器。将导电性确定杂质注入到半导体结构中以在直接耦合到沟槽电容器的半导体层中形成阱区。形成覆盖阱区域的一部分的栅极结构。然后将确定电导的离子注入阱区的其它部分以形成源区和漏区，并且在源区和漏区之间限定有源体区。有源体区域直接接触沟槽电容器。

3. 发明申请

US20100102867A1 SENSE AMPLIFIER BASED FLIP-FLOP 审中-公开
标题翻译：基于感光放大器的FLIP-FLOP
公开(公告)号：US20100102867A1
公开(公告)日：2010-04-29
申请号：US12258873
申请日：2008-10-27
申请人： Sang H. Dhong , Gurupada Mandal
发明人： Sang H. Dhong , Gurupada Mandal
IPC分类号： H03K3/289
CPC分类号： H03K3/356121
摘要： A sense amplifier based flip-flop having built-in logic functions. The flip-flop includes a first and second input circuits configured to cause complementary first and second logic values to be provided on first and second logic nodes, respectively. The flip-flop further includes a sense circuit configured to sense and capture the first and second logic values on first and second capture nodes, respectively, during an evaluation phase, and a precharge circuit configured to precharge the first and second logic node and the first and second capture nodes during a precharge phase. The flip-flop also includes a noise immunity circuit, configured to, during the evaluation phase, become active subsequent to the sense circuit capturing the first and second logic values, wherein, when activated, the noise immunity circuit prevents floating voltages on the first and second logic nodes.
摘要翻译：具有内置逻辑功能的基于读出放大器的触发器。触发器包括被配置为分别在第一和第二逻辑节点上提供互补的第一和第二逻辑值的第一和第二输入电路。触发器还包括感测电路，其被配置为在评估阶段期间分别在第一和第二捕获节点上感测和捕获第一和第二逻辑值，并且预充电电路被配置为对第一和第二逻辑节点和第一以及在预充电阶段期间的第二捕获节点。触发器还包括噪声抗扰电路，其被配置为在评估阶段期间在感测电路捕获第一和第二逻辑值之后变得有效，其中当激活时，抗噪声电路防止浮动电压在第一和第二逻辑值第二个逻辑节点。

4. 发明申请

US20100146330A1 MEMORY DEVICE AND METHOD THEREOF 有权
标题翻译：存储器件及其方法
公开(公告)号：US20100146330A1
公开(公告)日：2010-06-10
申请号：US12330012
申请日：2008-12-08
申请人： Sang Dhong , Jin Cho , John Wuu , Gurupada Mandal
发明人： Sang Dhong , Jin Cho , John Wuu , Gurupada Mandal
IPC分类号： G06F11/20
CPC分类号： G06F11/1048 , G11C2029/0411
摘要： An error correction module is disclosed whereby two bit cells are used to store a bit of information in a redundant manner so that a redundant error correction module can correct a sporadic data error at one of the two bits.
摘要翻译：公开了一种误差校正模块，其中两个比特单元用于以冗余的方式存储一位信息，使得冗余纠错模块可以校正两个比特之一的零星数据错误。

5. 发明授权

US07724567B2 Memory device and method of refreshing 有权
标题翻译：内存设备和刷新方法
公开(公告)号：US07724567B2
公开(公告)日：2010-05-25
申请号：US12167821
申请日：2008-07-03
申请人： Sang Dhong , Jin Cho , John Wuu , Gurupada Mandal
发明人： Sang Dhong , Jin Cho , John Wuu , Gurupada Mandal
IPC分类号： G11C11/36
CPC分类号： G11C15/04 , G06F12/0864 , G06F12/0895 , G11C11/39
摘要： A content addressable memory includes a first plurality of search lines, a second plurality of search lines, a first match line, and a storage location. Each search line of the first plurality of search lines receives a corresponding high voltage level or low voltage level during a match detect operation, and each search line of the second plurality of search lines to receive a corresponding high voltage level or low voltage level during the match detect operation. The storage location of the content addressable memory includes a plurality of CAM cells, each CAM cell a first thyristor and second thyristor.
摘要翻译：内容可寻址存储器包括第一多个搜索线，第二多个搜索线，第一匹配线和存储位置。第一多个搜索线的每个搜索线在匹配检测操作期间接收相应的高电压电平或低电压电平，并且第二多个搜索线的每个搜索线在期间接收相应的高电压电平或低电压电平匹配检测操作。内容可寻址存储器的存储位置包括多个CAM单元，每个CAM单元都是第一晶闸管和第二晶闸管。

6. 发明申请

US20100002482A1 MEMORY DEVICE AND METHOD 审中-公开
标题翻译：存储器件和方法
公开(公告)号：US20100002482A1
公开(公告)日：2010-01-07
申请号：US12167823
申请日：2008-07-03
申请人： Sang Dhong , Jin Cho , John Wuu , Gurupada Mandal
发明人： Sang Dhong , Jin Cho , John Wuu , Gurupada Mandal
IPC分类号： G11C15/00
CPC分类号： G11C15/04 , G11C11/39
摘要： A content addressable memory includes a first plurality of search lines, a second plurality of search lines, a first match line, and a storage location. Each search line of the first plurality of search lines receives a corresponding high voltage level or low voltage level during a match detect operation, and each search line of the second plurality of search lines to receive a corresponding high voltage level or low voltage level during the match detect operation. The storage location of the content addressable memory includes a plurality of CAM cells, each CAM cell a first thyristor and second thyristor.
摘要翻译：内容可寻址存储器包括第一多个搜索线，第二多个搜索线，第一匹配线和存储位置。第一多个搜索线的每个搜索线在匹配检测操作期间接收相应的高电压电平或低电压电平，并且第二多个搜索线的每个搜索线在期间接收相应的高电压电平或低电压电平匹配检测操作。内容可寻址存储器的存储位置包括多个CAM单元，每个CAM单元都是第一晶闸管和第二晶闸管。

7. 发明授权

US07215175B1 Fuse sensing scheme with auto current reduction 有权
标题翻译：具有自动电流降低的保险丝感测方案
公开(公告)号：US07215175B1
公开(公告)日：2007-05-08
申请号：US10932162
申请日：2004-09-01
申请人： Gurupada Mandal , Suresh Seshadri , David Hugh McIntyre , Raymond A. Heald , William Y. Mo
发明人： Gurupada Mandal , Suresh Seshadri , David Hugh McIntyre , Raymond A. Heald , William Y. Mo
IPC分类号： H01H37/76 , H01H85/00
CPC分类号： G11C17/18
摘要： An improved circuit for sensing and programming fuses in integrated circuits. The circuit is broadly comprised of a fuse cell, a reference circuit, a sense amplifier and a level detector. In one embodiment of the present invention, a two-stage sensing scheme is implemented. The improved fuse sensing circuit uses current-mode sensing and implements an auto-read current reduction scheme. Using a level-detect circuit, the virtual ground is raised automatically if the high-voltage power supply exceeds core supply (Vdd) by a fixed dc voltage. This reduces effective sensing voltage and the read current and thus helps preserve unblown fuse integrity. In one embodiment of the invention, four modes of operation are implemented: “Normal Read,” “Unblown_Read,” “Blown_Read_1” and “Blown_Read_2.” The default read mode is the “normal read” while the “Unblown” and “Blown” read modes are for fuse calibration purposes. In the “Unblown_Read” read mode, the circuit is operable to compare the fuse resistance against a lower reference resistance, closer to an unblown fuse resistance value, in order to make the comparison more stringent. Similarly, the “Blown_Read_1” and “Blown_Read_2” modes allow a more stringent comparison for a blown fuse resistance.
摘要翻译：一种用于在集成电路中感测和编程保险丝的改进电路。该电路广泛地包括熔丝单元，参考电路，读出放大器和电平检测器。在本发明的一个实施例中，实现了两级感测方案。改进的熔丝感测电路使用电流模式感测并实现自动读取电流降低方案。使用电平检测电路，如果高压电源以固定的直流电压超过磁芯电源（Vdd），则虚拟接地将自动升高。这降低了有效的感测电压和读取电流，从而有助于保持未熔断的保险丝完整性。在本发明的一个实施例中，实现了四种操作模式：“Normal Read”，“Unblown_Read”，“Blown_Read_1”和“Blown_Read_2”。 “Unblown”和“Blown”读取模式的默认读取模式是“正常读取”，用于保险丝校准。在“Unblown_Read”读取模式下，该电路可操作以将熔丝电阻与较低的参考电阻进行比较，更接近未熔断的保险丝电阻值，以使比较更加严格。类似地，“Blown_Read_1”和“Blown_Read_2”模式允许对熔断熔断器电阻进行更严格的比较。

8. 发明授权

US07106635B1 Bitline booster circuit and method 有权
标题翻译：位线升压电路及方法
公开(公告)号：US07106635B1
公开(公告)日：2006-09-12
申请号：US10769130
申请日：2004-01-29
申请人： Gurupada Mandal
发明人： Gurupada Mandal
IPC分类号： G11C7/00
CPC分类号： G11C7/12
摘要： A circuit and method for boosting bitline performance uses a bitline booster circuit to allow long bitlines, with large numbers of memory cells attached, to discharge to a digital zero in a faster time. One bitline booster circuit requires only two additional NOR gates, two additional transistors, and one additional control signal. Consequently, the bitline booster circuit does not require a significant number of added components, does not require multiple control signals and takes up minimal additional silicon area.
摘要翻译：用于提升位线性能的电路和方法使用位线升压电路，以允许具有大量存储器单元的长位线在更快的时间内放电到数字零。一个位线升压电路只需要两个额外的NOR门，两个额外的晶体管和一个额外的控制信号。因此，位线升压电路不需要大量的附加元件，不需要多个控制信号并占用最小的额外硅面积。

9. 发明授权

US08464130B2 Memory device and method thereof 有权
标题翻译：存储器件及其方法
公开(公告)号：US08464130B2
公开(公告)日：2013-06-11
申请号：US12330012
申请日：2008-12-08
申请人： Sang Dhong , Jin Cho , John Wuu , Gurupada Mandal
发明人： Sang Dhong , Jin Cho , John Wuu , Gurupada Mandal
IPC分类号： G06F11/00
CPC分类号： G06F11/1048 , G11C2029/0411
摘要： An error correction module is disclosed whereby two bit cells are used to store a bit of information in a redundant manner so that a redundant error correction module can correct a sporadic data error at one of the two bits.
摘要翻译：公开了一种误差校正模块，其中两个比特单元用于以冗余的方式存储一位信息，使得冗余纠错模块可以校正两个比特之一的零星数据错误。

10. 发明申请

US20100002502A1 MEMORY DEVICE AND METHOD OF REFRESHING 有权
标题翻译：存储器件和刷新方法
公开(公告)号：US20100002502A1
公开(公告)日：2010-01-07
申请号：US12167821
申请日：2008-07-03
申请人： Sang Dhong , Jin Cho , John Wuu , Gurupada Mandal
发明人： Sang Dhong , Jin Cho , John Wuu , Gurupada Mandal
IPC分类号： G11C11/34 , G11C7/00
CPC分类号： G11C15/04 , G06F12/0864 , G06F12/0895 , G11C11/39
摘要： A content addressable memory includes a first plurality of search lines, a second plurality of search lines, a first match line, and a storage location. Each search line of the first plurality of search lines receives a corresponding high voltage level or low voltage level during a match detect operation, and each search line of the second plurality of search lines to receive a corresponding high voltage level or low voltage level during the match detect operation. The storage location of the content addressable memory includes a plurality of CAM cells, each CAM cell a first thyristor and second thyristor.
摘要翻译：内容可寻址存储器包括第一多个搜索线，第二多个搜索线，第一匹配线和存储位置。第一多个搜索线的每个搜索线在匹配检测操作期间接收相应的高电压电平或低电压电平，并且第二多个搜索线的每个搜索线在期间接收相应的高电压电平或低电压电平匹配检测操作。内容可寻址存储器的存储位置包括多个CAM单元，每个CAM单元都是第一晶闸管和第二晶闸管。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式