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1. 发明授权

US4754433A Dynamic ram having multiplexed twin I/O line pairs 失效
标题翻译：具有复用双I / O线对的动态RAM
公开(公告)号：US4754433A
公开(公告)日：1988-06-28
申请号：US908440
申请日：1986-09-16
申请人： Daeje Chin , Wei Hwang , Nicky C. Lu
发明人： Daeje Chin , Wei Hwang , Nicky C. Lu
IPC分类号： G11C11/401 , G11C7/10 , G11C11/409 , G11C11/4096 , G11C7/00
CPC分类号： G11C11/4096 , G11C7/1021 , G11C7/1033 , G11C7/1048
摘要： A dynamic random access memory (DRAM) is comprised of a first and a second input/output (I/O) bus, a first and a second I/O sense amplifier, and a first and a second I/O bus precharge circuit. A control circuit is responsive to the state of a mode control signal for enabling the operation of the I/O buses and the precharge circuits such that in one mode of operation the DRAM operates in a conventional single bit per CAS cycle page mode. In a second mode of operation a high speed dual bit per CAS cycle page mode is achieved, wherein the I/O buses are alternately enabled, one being enabled when CAS is asserted and the other being enabled when CAS is deasserted. The dual bit mode of operation provides also for precharging the I/O bus which is not enabled during the period when the other bus is enabled. Thus, in the dual bit mode of operation data transfers to or from the DRAM occur both when CAS is asserted and also when CAS is deasserted, thereby doubling the data transfer rate over that of the conventional page mode of operation.
摘要翻译：动态随机存取存储器（DRAM）由第一和第二输入/输出（I / O）总线，第一和第二I / O读出放大器以及第一和第二I / O总线预充电电路组成。控制电路响应于模式控制信号的状态，以使得I / O总线和预充电电路的操作能够使得在一种操作模式下，DRAM以每个CAS循环页面模式以常规单位操作。在第二种操作模式下，实现了每个CAS循环页面模式的高速双位模式，其中I / O总线被交替使能，一个在CAS被断言时被使能，另一个在CAS被取消置位时使能。双位操作模式还用于对在其他总线使能的时段内未使能的I / O总线进行预充电。因此，在双位操作模式下，当CAS被断言并且当CAS被断言时，数据传送到DRAM或从DRAM发生的数据传输速率超过常规页面操作模式的数据传输速率。

2. 发明授权

US4678941A Boost word-line clock and decoder-driver circuits in semiconductor memories 失效
标题翻译：升压半导体存储器中的字线时钟和解码器驱动电路
公开(公告)号：US4678941A
公开(公告)日：1987-07-07
申请号：US727301
申请日：1985-04-25
申请人： Hu H. Chao , Nicky C. Lu
发明人： Hu H. Chao , Nicky C. Lu
IPC分类号： G11C11/407 , G11C8/08 , G11C8/10 , G11C8/18 , H03K19/096
CPC分类号： G11C8/08 , G11C8/10 , G11C8/18
摘要： A CMOS boost word-line clock and decoder-driver circuit which can be used for CMOS DRAM's with substrate bias in addition to VDD supply. A boost word-line clock circuit including simple CMOS inverters is used for the word-line boost and the possible voltage overshoot, which usually occurs because of capacitor two-way boost, can be completely eliminated. Also, the circuit can be triggered by a single clock. A high performance decoder circuit is provided in combination with the aforesaid CMOS boost word-line clock circuit, such decoder using NMOS pass-gate in the decoder driver and providing fast word-line boosting. The timing between the decoder and the word-line clock activation is not crucial.
摘要翻译：一个CMOS升压字线时钟和解码器驱动电路，可以用于具有衬底偏置的CMOS DRAM以及VDD电源。包括简单CMOS反相器的升压字线时钟电路用于字线升压，并且由于电容器双向升压而通常发生的可能的电压过冲可以被完全消除。此外，电路可以由单个时钟触发。与上述CMOS升压字线时钟电路组合提供了一种高性能解码器电路，这种解码器在解码器驱动器中使用NMOS通道并提供快速的字线升压。解码器和字线时钟激活之间的时序并不重要。

3. 发明授权

US06107134A High performance DRAM structure employing multiple thickness gate oxide 有权
标题翻译：采用多层栅极氧化物的高性能DRAM结构
公开(公告)号：US06107134A
公开(公告)日：2000-08-22
申请号：US431134
申请日：1999-11-01
申请人： Nicky C. Lu , Kun-Zen Chang
发明人： Nicky C. Lu , Kun-Zen Chang
IPC分类号： H01L21/8239 , H01L21/8242 , H01L27/105
CPC分类号： H01L27/10873 , H01L27/105 , H01L27/1052
摘要： A DRAM device having improved performance of peripheral circuitry is described. The performance is improved by selectively having MOS transistors with a thinner gate oxide in peripheral circuits having a lower voltage applied to their gate electrodes. The DRAM device will maintain reliability by having MOS transistors with a thicker gate oxide in the memory cells and selected peripheral circuitry that are subjected to a higher voltage at their gate electrodes. Further this invention describes methods of fabricating the DRAM device with selectively placed multiple gate oxide thickness.
摘要翻译：描述了具有改善的外围电路性能的DRAM装置。通过选择性地具有在其栅电极施加较低电压的外围电路中具有较薄栅极氧化物的MOS晶体管来提高性能。 DRAM器件将通过在存储器单元中具有较厚栅极氧化物的MOS晶体管以及在其栅电极处受到较高电压的选定外围电路来保持可靠性。此外，本发明描述了制造具有选择性地放置多个栅极氧化物厚度的DRAM器件的方法。

4. 发明授权

US4954731A Wordline voltage boosting circuits for complementary MOSFET dynamic memories 失效
标题翻译：用于互补MOSFET动态存储器的字线升压电路
公开(公告)号：US4954731A
公开(公告)日：1990-09-04
申请号：US344340
申请日：1989-04-26
申请人： Sang H. Dhong , Wei Hwang , Nicky C. Lu
发明人： Sang H. Dhong , Wei Hwang , Nicky C. Lu
IPC分类号： G11C11/407 , G11C11/408 , H03K5/02
CPC分类号： G11C11/4085 , H03K5/023
摘要： Two embodiments of a wordline boost clock circuit that can be used in high speed DRAM circuits are disclosed. The clock circuits require only one boost capacitor and discharge the wordlines faster, improving the DRAM access time. The basic feature of the clock circuit is in the floating gate structure of the nmos device which drives the load to negative during the boosting. In the first embodiment of the clock, the gate of a first device is connected to a first node through a second device. A second node, connected to a wordline, is discharged through the first and a third device when a third node is high with a fourth node low. After a sufficient discharge of the second node, the fourth node is pulled to VDD turning the second device on and a fourth device off. The first (NMOS) transistor has its gate and drain connected together and forms a diode. When a boost capacitor pulls the first node down to negative, the first device stays completely off because of its diode configuration and the second node is pulled to negative through the third device. In the second embodiment, a first device is connected between a boost capacitor and a second node. The load is discharged through a third device with a fourth device on but a first and second device off. After a sufficient discharge of the load, a fourth device is turned off but a second device is turned on, making the third device a diode. When a fifth node is pulled to ground, the second node is pulled down to negative with the first device on. In the second embodiment circuit, the load discharges through only one nmos device and consequently discharges faster than the circuit of the first embodiment.

5. 发明授权

US4833516A High density memory cell structure having a vertical trench transistor self-aligned with a vertical trench capacitor and fabrication methods therefor 失效
标题翻译：具有与垂直沟槽电容器自对准的垂直沟槽晶体管的高密度存储单元结构及其制造方法
公开(公告)号：US4833516A
公开(公告)日：1989-05-23
申请号：US81270
申请日：1987-08-03
申请人： Wei Hwang , Nicky C. Lu
发明人： Wei Hwang , Nicky C. Lu
IPC分类号： H01L27/10 , H01L21/822 , H01L21/8242 , H01L27/04 , H01L27/108 , H01L29/78
CPC分类号： H01L27/10864 , H01L27/10841 , H01L29/7827 , H01L29/7834
摘要： A new high density vertical trench transistor and trench capacitor DRAM (dynamic-random-access memory) cell is described incorporating a wafer with a semiconductor substrate and an epitaxial layer thereon including a vertical transistor disposed in a shallow trench stacked above and self-aligned with a capacitor in a deep trench. The stacked vertical transistor 14 has a channel partly on the horizontal surface and partly along the shallow trench sidewalls. The drain of the access transistor is a lightly-doped drain structure connected to a bitline element. The source of the transistor, located at the bottom of the transistor trench and on top of the center of the trench capacitor, is self-aligned and connected to polysilicon contained inside the trench capacitor. Three sidewalls of the access transistor are surrounded by thick oxide isolation and the remaining one side is connected to drain and bitline contacts. The memory cell is located inside an n-well and uses the n-well and heavily-doped substrate as the capacitor counter-electrode plate. The cell storage node is the polysilicon inside the trench capacitor and include steps for growing epitaxial layers wherein an opening is left which serves as the shallow trench access transistor region and provides self-alignment with the deep trench storage capacitor.

6. 发明授权

US4688063A Dynamic ram cell with MOS trench capacitor in CMOS 失效
标题翻译：具有MOS沟槽电容器的动态RAM单元
公开(公告)号：US4688063A
公开(公告)日：1987-08-18
申请号：US920916
申请日：1986-10-21
申请人： Nicky C. Lu , Tak H. Ning , Lewis M. Terman
发明人： Nicky C. Lu , Tak H. Ning , Lewis M. Terman
IPC分类号： H01L27/108 , H01L29/94 , H01L29/78
CPC分类号： H01L27/10832 , H01L29/945
摘要： This invention relates generally to Dynamic Random Access Memory (DRAM) cells and more particularly relates to a DRAM cell wherein the storage capacitor of the cell is disposed in a trench formed in a semiconductor substrate. Still more particularly, it relates to a DRAM cell wherein at least a portion of the substrate is heavily doped and forms the counterelectrode of the storage capacitor while a heavily doped polycrystalline plug disposed in the trench capacitor forms the other electrode of the storage capacitor. The DRAM cell includes a field effect access transistor disposed in a well which is opposite in conductivity type to that of the substrate. The well itself is formed in a lightly doped portion of the substrate and may be n or p-type conductivity with the other portions of the cell having conductivity types appropriate for devices fabricated in the CMOS environment. The trench capacitor extends from the surface of the well through the well and lightly doped substrate portion into the heavily doped portion of the substrate. The electrode disposed in the trench is directly connected to the source/drain of the access transistor.
摘要翻译：本发明一般涉及动态随机存取存储器（DRAM）单元，更具体地说，涉及一种DRAM单元，其中单元的存储电容器设置在形成于半导体衬底中的沟槽中。更具体地说，本发明涉及一种DRAM单元，其中基板的至少一部分被重掺杂并形成存储电容器的反电极，而设置在沟槽电容器中的重掺杂多晶硅形成存储电容器的另一个电极。 DRAM单元包括放置在与衬底的导电类型相反的阱中的场效应存取晶体管。阱本身形成在衬底的轻掺杂部分中，并且可以是n型或p型导电性，其中电池的其它部分具有适合于在CMOS环境中制造的器件的导电类型。沟槽电容器从阱的表面延伸穿过阱和轻掺杂衬底部分到衬底的重掺杂部分。设置在沟槽中的电极直接连接到存取晶体管的源极/漏极。

7. 发明授权

US5021355A Method of fabricating cross-point lightly-doped drain-source trench transistor 失效
标题翻译：制造交叉点轻掺杂漏极 - 沟槽晶体管的方法
公开(公告)号：US5021355A
公开(公告)日：1991-06-04
申请号：US513711
申请日：1990-05-18
申请人： Sang H. Dhong , Wei Hwang , Nicky C. Lu
发明人： Sang H. Dhong , Wei Hwang , Nicky C. Lu
IPC分类号： H01L21/223 , H01L21/8242 , H01L27/108 , H01L27/112 , H01L29/78
CPC分类号： H01L27/10844 , H01L21/2236 , H01L27/10838 , H01L29/7827 , H01L29/7834 , H01L27/112
摘要： A structure and fabrication process for a self-aligned, lightly-doped drain/source n-channel field-effect transistor wherein a trench is formed in a well region in a wafer including an epitaxial layer on a substrate. A first, heavily doped drain region and bit line element is formed around the trench on the surface of the well, and a second, lightly-doped drain region is formed proximate to the first drain region and self-aligned to the trench sidewalls. A source region is located beneath the trench, which is filled with polysilicon, above which is gate and further polysilicon forming a transfer wordline. The well region at the trench sidewalls are doped to control the device threshold level, and the device is thereby also located at a wordline/bitline cross-point.
摘要翻译：用于自对准，轻掺杂漏极/源极n沟道场效应晶体管的结构和制造工艺，其中在衬底中的包括外延层的晶片的阱区中形成沟槽。在阱的表面上的沟槽周围形成第一重掺杂漏极区和位线元件，并且第二轻掺杂漏极区形成在靠近第一漏极区并且与沟槽侧壁自对准。源极区位于沟槽下面，其被多晶硅填充，其上方是栅极，并且另外的多晶硅形成传输字线。在沟槽侧壁处的阱区被掺杂以控制器件阈值电平，因此器件也位于字线/位线交叉点。

8. 发明授权

US4983544A Silicide bridge contact process 失效
标题翻译：硅化物桥接触过程
公开(公告)号：US4983544A
公开(公告)日：1991-01-08
申请号：US920471
申请日：1986-10-20
申请人： Nicky C. Lu , Brian J. Machesney , Rick L. Mohler , Glen L. Miles , Chung-Yu Ting , Stephen D. Warley
发明人： Nicky C. Lu , Brian J. Machesney , Rick L. Mohler , Glen L. Miles , Chung-Yu Ting , Stephen D. Warley
IPC分类号： H01L21/3205 , H01L21/768 , H01L23/482 , H01L23/52 , H01L29/45
CPC分类号： H01L21/76895 , H01L21/76886 , H01L23/4821 , H01L29/456 , H01L2924/0002 , Y10S148/019 , Y10S148/147
摘要： A method of forming a bridge contact between a source diffusion region of a transfer gate FET and a polysilicon-filled trench storage capacitor electrodes of the FET. A layer of titanium is evaporated at a temperature of approximately 370.degree. C., so that the titanium has a substantially columnar grain structure and a minimum of matrix material. The bottom portions of the columnar grains have a lateral length that approximates the lateral length of the dielectric separating the source diffusion from the poly-filled trench. Thus, upon sintering at 700.degree. C. in an N.sub.2 atmosphere, titanium silicide will form over all exposed silicon regions as well as the dielectric, without shorting the FET electrodes together.
摘要翻译：在传输栅极FET的源极扩散区域和FET的多晶硅填充的沟槽存储电容器电极之间形成桥接触的方法。在约370℃的温度下蒸发一层钛，使得钛具有基本上柱状的晶粒结构和最小的基体材料。柱状晶粒的底部具有近似于将源极扩散与多孔填充沟槽分离的介质的横向长度的横向长度。因此，在N 2气氛中在700℃烧结时，在所有暴露的硅区域和电介质上形成硅化钛，而不会将FET电极短路在一起。

9. 发明授权

US4927779A Complementary metal-oxide-semiconductor transistor and one-capacitor dynamic-random-access memory cell and fabrication process therefor 失效
标题翻译：互补金属氧化物半导体晶体管和单电容器动态随机存取存储器单元及其制造工艺
公开(公告)号：US4927779A
公开(公告)日：1990-05-22
申请号：US428159
申请日：1989-10-27
申请人： Sang H. Dhong , Nicky C. Lu , Walter H. Henkels
发明人： Sang H. Dhong , Nicky C. Lu , Walter H. Henkels
IPC分类号： G11C11/404 , H01L27/06 , H01L27/108
CPC分类号： H01L27/0688 , G11C11/404 , H01L27/108
摘要： A complementary MOS one-capacitor dynamic RAM cell which operates with a non-boosted wordline without a threshold loss problem and which includes one storage capacitor and n- and p-type transfer devices connected to the storage capacitor which function as two complementary transistor devices having gates controlled by complementary signals on the RAM wordlines.
摘要翻译：一种互补的MOS单电容器动态RAM单元，其在没有阈值损耗问题的情况下与非升压字线一起工作，并且包括连接到存储电容器的一个存储电容器和n型和p型转移装置，其作为两个互补晶体管器件起作用，由RAM字线上的互补信号控制的门。

10. 发明授权

US5198995A Trench-capacitor-one-transistor storage cell and array for dynamic random access memories 失效
标题翻译：用于动态随机存取存储器的沟槽电容器一晶体管存储单元和阵列
公开(公告)号：US5198995A
公开(公告)日：1993-03-30
申请号：US605892
申请日：1990-10-30
申请人： Robert H. Dennard , Nicky C. Lu
发明人： Robert H. Dennard , Nicky C. Lu
IPC分类号： G11C11/4091 , H01L27/108
CPC分类号： G11C11/4091 , H01L27/10829
摘要： Lightly Depleted PMOS (LDP) substrate-plate trench-capacitor (SPT) cell Array architecture is disclosed including three types of devices: An enhancement NMOS transistor (ENMOS) which has a n+ poly gate with a positive threshold voltage range, an enhancement PMOS transistor (EPMOS) having a p+ poly gate with a negative threshold voltage range, and a lightly depleted PMOS transistor (LDPMOS) having a p+ poly gate. The LDPMOS is used as the access transistor in the SPT cell with body biased at the power supply voltage VDD, and can also be used in the write drivers. A sense amplifier is included which is a CMOS cross-coupled latch. An n-well is biased at a lower voltage than VDD, such as (VDD--Vg) where Vg is the silicon bandgap, and the lower thresholds enhance faster sensing. The CMOS cross-coupled latch is activated by turning on latching devices. The bitlines are prevented from charging to greater than VDD--Vg, which could cause the array devices of unselected cells to conduct current and alter the stored low-voltage state of such cells.
摘要翻译：公开了具有三种类型器件的轻度耗尽的PMOS（LDP）衬底板沟槽电容器（SPT）单元阵列结构：具有正阈值电压范围的n +多晶硅栅极的增强型NMOS晶体管（ENMOS），增强型PMOS晶体管（EPMOS）具有负阈值电压范围的p +多晶硅栅极，以及具有p +多晶硅栅极的低耗尽PMOS晶体管（LDPMOS）。 LDPMOS用作SPT单元中的存取晶体管，其主体在电源电压VDD处偏置，并且也可用于写入驱动器。包括一个CMOS交叉耦合锁存器的读出放大器。 n阱被偏置在比VDD低的电压，例如（VDD-Vg），其中Vg是硅带隙，并且下阈值增强更快的感测。通过开启锁存器件来激活CMOS交叉耦合锁存器。阻止位线大于VDD-Vg，这可能导致未选择的单元的阵列器件导通电流并改变这种单元的存储的低电压状态。

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