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1. 发明申请

US20070166995A1 METHOD FOR DIRECT ELECTROPLATING OF COPPER ONTO A NON-COPPER PLATEABLE LAYER 有权
标题翻译：将铜直接电镀在非镀层上的方法
公开(公告)号：US20070166995A1
公开(公告)日：2007-07-19
申请号：US11306932
申请日：2006-01-17
申请人： Sandra Malhotra , Hariklia Deligianni , Stephen Rossnagel , Xiaoyan Shao , Tsong-Lin Tai , Oscar van der Straten
发明人： Sandra Malhotra , Hariklia Deligianni , Stephen Rossnagel , Xiaoyan Shao , Tsong-Lin Tai , Oscar van der Straten
IPC分类号： H01L21/4763
CPC分类号： H01L21/76843 , H01L21/28562 , H01L21/76861 , H01L21/76862 , H01L21/76873 , Y10S438/952
摘要： A process for the formation of an interconnect in a semiconductor structure including the steps of forming a dielectric layer on a substrate, forming a first barrier layer on the dielectric layer, forming a second barrier layer on the first barrier layer, wherein the second barrier layer is selected from the group consisting of ruthenium, platinum, palladium, rhodium and iridium and wherein the formation of the second barrier layer is manipulated so that the bulk concentration of oxygen in the second barrier layer is 20 atomic percent or less, and forming a conductive layer on the second barrier layer. The process may additionally include a step of treating the second barrier to reduce the amount of oxide on the surface of the second barrier layer.
摘要翻译：一种在半导体结构中形成互连的方法，包括以下步骤：在衬底上形成电介质层，在电介质层上形成第一阻挡层，在第一阻挡层上形成第二阻挡层，其中第二阻挡层选自钌，铂，钯，铑和铱，并且其中操作第二阻挡层的形成，使得第二阻挡层中的氧的体积浓度为20原子％以下，并且形成导电层在第二阻挡层上。该方法可以另外包括处理第二阻挡层以减少第二阻挡层表面上的氧化物的量的步骤。

2. 发明申请

US20070222066A1 STRUCTURE AND METHOD OF FORMING ELECTRODEPOSITED CONTACTS 有权
标题翻译：形成电沉积联系的结构和方法
公开(公告)号：US20070222066A1
公开(公告)日：2007-09-27
申请号：US11308433
申请日：2006-03-24
申请人： Cyril Cabral , Hariklia Deligianni , Randolph Knarr , Sandra Malhotra , Stephen Rossnagel , Xiaoyan Shao , Anna Topol , Philippe Vereecken
发明人： Cyril Cabral , Hariklia Deligianni , Randolph Knarr , Sandra Malhotra , Stephen Rossnagel , Xiaoyan Shao , Anna Topol , Philippe Vereecken
IPC分类号： H01L23/48
CPC分类号： H01L23/485 , H01L21/2885 , H01L21/76843 , H01L21/76846 , H01L21/76877 , H01L23/53252 , H01L2924/0002 , H01L2924/00
摘要： A contact metallurgy structure comprising a patterned dielectric layer having cavities on a substrate; a silicide or germanide layer such as of cobalt and/or nickel located at the bottom of cavities; a contact layer comprising Ti or Ti/TiN located on top of the dielectric layer and inside the cavities and making contact to the silicide or germanide layer on the bottom; a diffusion barrier layer located on top of the contact layer and inside the cavities; optionally a seed layer for plating located on top of the barrier layer; a metal fill layer in vias is provided along with a method of fabrication. The metal fill layer is electrodeposited with at least one member selected from the group consisting of copper, rhodium, ruthenium, iridium, molybdenum, gold, silver, nickel, cobalt, silver, gold, cadmium and zinc and alloys thereof. When the metal fill layer is rhodium, ruthenium, or iridium, an effective diffusion barrier layer is not required between the fill metal and the dielectric. When the barrier layer is platable, such as ruthenium, rhodium, platinum, or iridium, the seed layer is not required.
摘要翻译：一种接触式冶金结构，包括在基底上具有空腔的图案化电介质层; 位于空腔底部的硅化物或锗化物层，例如钴和/或镍; 接触层，其包含位于介电层顶部并且在空腔内并与底部的硅化物或锗化物层接触的Ti或Ti / TiN; 位于所述接触层顶部和所述空腔内的扩散阻挡层; 可选地，位于阻挡层顶部的用于电镀的种子层; 提供通孔中的金属填充层以及制造方法。金属填充层用选自铜，铑，钌，铱，钼，金，银，镍，钴，银，金，镉和锌中的至少一种电池和其合金电沉积。当金属填充层是铑，钌或铱时，在填充金属和电介质之间不需要有效的扩散阻挡层。当阻挡层是可镀的，例如钌，铑，铂或铱时，不需要种子层。

3. 发明申请

US20050199502A1 Method for electroplating on resistive substrates 审中-公开
标题翻译：电阻基板电镀方法
公开(公告)号：US20050199502A1
公开(公告)日：2005-09-15
申请号：US11123117
申请日：2005-05-06
申请人： Panayotis Andricacos , Hariklia Deligianni , Wilma Horkans , Keith Kwietniak , Michael Lane , Sandra Malhotra , Fenton McFeely , Conal Murray , Kenneth Rodbell , Philippe Vereecken
发明人： Panayotis Andricacos , Hariklia Deligianni , Wilma Horkans , Keith Kwietniak , Michael Lane , Sandra Malhotra , Fenton McFeely , Conal Murray , Kenneth Rodbell , Philippe Vereecken
IPC分类号： C25D5/18 , C25D7/12 , C25D5/02
CPC分类号： C25D5/18 , C25D7/12 , Y10S428/926 , Y10T428/12493 , Y10T428/12528 , Y10T428/12771 , Y10T428/12778 , Y10T428/12903
摘要： A conductive material is electroplated onto a platable resistive metal barrier layer(s) employing a plating bath optionally comprising a super filling additive and a suppressor, and by changing the current or voltage as a function of the area of plated metal. A structure is also provided that comprises a substrate, a platable metal barrier layer(s) located on the substrate and a relatively continuous uniform electroplated layer of a conductive material located on the platable resistive metal barrier layer.
摘要翻译：导电材料电镀在可镀敷的电阻金属阻挡层上，该层使用任选地包含超填充添加剂和抑制剂的电镀槽，并且通过改变作为电镀金属面积的函数的电流或电压。还提供了一种结构，其包括衬底，位于衬底上的可镀金属阻挡层和位于可镀电阻金属阻挡层上的导电材料的相对连续的均匀电镀层。

4. 发明申请

US20060160350A1 On-chip Cu interconnection using 1 to 5 nm thick metal cap 有权
标题翻译：使用1至5nm厚的金属帽的片上Cu互连
公开(公告)号：US20060160350A1
公开(公告)日：2006-07-20
申请号：US11037970
申请日：2005-01-18
申请人： John Bruley , Roy Carruthers , Lynne Gignac , Chao-Kun Hu , Eric Liniger , Sandra Malhotra , Stephen Rossnagel
发明人： John Bruley , Roy Carruthers , Lynne Gignac , Chao-Kun Hu , Eric Liniger , Sandra Malhotra , Stephen Rossnagel
IPC分类号： H01L21/4763
CPC分类号： H01L21/76849 , H01L21/76829 , H01L23/53238 , H01L23/53295 , H01L2924/0002 , H01L2924/3011 , H01L2924/00
摘要： Disclosed is a procedure to coat the free surface of Cu damascene lines by a 1-5 nm thick element prior to deposition of the inter-level dielectric or dielectric diffusion barrier layer. The coating provides protection against oxidation, increases the adhesion strength between the Cu and dielectric, and reduces interface diffusion of Cu. In addition, the thin cap layer further increases electromigration Cu lifetime and reduces the stress induced voiding. The selective elements can be directly deposited onto the Cu embedded within the under layer dielectric without causing an electric short circuit between the Cu lines. These chosen elements are based on their high negative reduction potentials with oxygen and water, and a low solubility in and formation of compounds with Cu.
摘要翻译：公开了在沉积层间电介质或电介质扩散阻挡层之前，通过1-5nm厚的元件涂覆Cu镶嵌线的自由表面的步骤。涂层提供防氧化保护，增加Cu和介电层之间的粘合强度，并减少Cu的界面扩散。此外，薄盖层进一步增加电迁移Cu寿命，并减少应力引起的空隙。选择元件可以直接沉积在嵌入在下层电介质中的Cu上，而不会在Cu线之间引起电短路。这些选择的元素是基于它们具有氧和水的高的负还原电位，以及与Cu的化合物的低溶解度和形成。

5. 发明授权

US08900422B2 Yttrium and titanium high-K dielectric film 有权
标题翻译：钇和钛高K电介质膜
公开(公告)号：US08900422B2
公开(公告)日：2014-12-02
申请号：US12921776
申请日：2009-04-17
申请人： Imran Hashim , Indranil De , Tony Chiang , Edward Haywood , Hanhong Chen , Nobi Fuchigami , Pragati Kumar , Sandra Malhotra , Sunil Shanker
发明人： Imran Hashim , Indranil De , Tony Chiang , Edward Haywood , Hanhong Chen , Nobi Fuchigami , Pragati Kumar , Sandra Malhotra , Sunil Shanker
IPC分类号： B05D5/12 , C23C14/34 , H01L49/02 , C23C16/40 , C23C16/455 , H01L21/314 , H01L21/316 , H01L27/108 , H01L21/02
CPC分类号： H01L28/65 , C23C16/405 , C23C16/45529 , C23C16/45531 , H01L21/02697 , H01L21/3141 , H01L21/31604 , H01L27/10852 , H01L28/40
摘要： This disclosure provides (a) methods of making an oxide layer (e.g., a dielectric layer) based on yttrium and titanium, to have a high dielectric constant and low leakage characteristic and (b) related devices and structures. An oxide layer having both yttrium and titanium may be fabricated either as an amorphous oxide or as an alternating series of monolayers. In several embodiments, the oxide is characterized by a yttrium contribution to total metal that is specifically controlled. The oxide layer can be produced as the result of a reactive process, if desired, via either a PVD process or, alternatively, via an atomic layer deposition process that employs specific precursor materials to allow for a common process temperature window for both titanium and yttrium reactions.
摘要翻译：本公开内容提供（a）制造基于钇和钛的氧化物层（例如，电介质层）的方法，以具有高介电常数和低泄漏特性，以及（b）相关的器件和结构。具有钇和钛的氧化物层可以制成无定形氧化物或交替的单层系列。在几个实施方案中，氧化物的特征在于对特定控制的总金属的钇贡献。如果需要，可以通过PVD工艺或者通过使用特定的前体材料以允许钛和钇的共同工艺温度窗口的原子层沉积工艺，作为反应过程的结果来生产氧化物层反应。

6. 发明授权

US08765570B2 Manufacturable high-k DRAM MIM capacitor structure 有权
标题翻译：可制造的高k DRAM MIM电容器结构
公开(公告)号：US08765570B2
公开(公告)日：2014-07-01
申请号：US13494808
申请日：2012-06-12
申请人： Sandra Malhotra , Wim Deweerd , Hiroyuki Ode
发明人： Sandra Malhotra , Wim Deweerd , Hiroyuki Ode
IPC分类号： H01L21/20
CPC分类号： H01L28/56 , H01L27/10852 , H01L28/60 , H01L28/90
摘要： A method for forming a capacitor stack is described. In some embodiments of the present invention, a first dielectric material is formed above a first electrode material. The first electrode material is rigid and has good mechanical strength and serves as a robust frame for the capacitor stack. The first dielectric material is sufficiently thin ( 3 nm) or lightly doped or non-doped so that it crystallizes after subsequent anneal treatments. A second electrode material is formed adjacent to the second dielectric material. The second electrode material has a high work function and a crystal structure that serves to promote the formation of the high k-value crystal structure of the second dielectric material.
摘要翻译：描述形成电容器堆叠的方法。在本发明的一些实施例中，第一电介质材料形成在第一电极材料之上。第一电极材料是刚性的并且具有良好的机械强度并且用作用于电容器叠层的坚固框架。第一介电材料足够薄（<2nm）或高度掺杂，使得在随后的退火处理之后其保持非晶态。在第一电介质材料上方形成第二电介质材料。第二介电材料足够厚（> 3nm）或轻掺杂或未掺杂，使得其在随后的退火处理之后结晶。与第二电介质材料相邻地形成第二电极材料。第二电极材料具有高功函数和用于促进形成第二电介质材料的高k值晶体结构的晶体结构。

7. 发明授权

US08574998B2 Leakage reduction in DRAM MIM capacitors 有权
标题翻译： DRAM MIM电容器的漏电减少
公开(公告)号：US08574998B2
公开(公告)日：2013-11-05
申请号：US13311368
申请日：2011-12-05
申请人： Sandra Malhotra , Kenichi Koyanagi , Hiroyuki Ode , Xiangxin Rui , Takashi Arao , Naonori Fujiwara
发明人： Sandra Malhotra , Kenichi Koyanagi , Hiroyuki Ode , Xiangxin Rui , Takashi Arao , Naonori Fujiwara
IPC分类号： H01L21/02
CPC分类号： H01L28/40 , H01G4/1272 , H01G4/306 , H01G4/33 , H01L21/02175 , H01L21/02189 , H01L21/02192 , H01L21/02194 , H01L21/022 , H01L21/0228
摘要： A method for reducing the leakage current in DRAM MIM capacitors comprises forming a multi-layer dielectric stack from an amorphous highly doped material, an amorphous high band gap material, and a lightly or non-doped material. The highly doped material will remain amorphous (
摘要翻译：用于减少DRAM MIM电容器中的漏电流的方法包括从非晶高掺杂材料，非晶高带隙材料以及轻掺杂或非掺杂材料形成多层电介质叠层。退火步骤后，高掺杂材料将保持无定形（<30％结晶）。在退火步骤之后，高带隙材料将保持无定形（<30％结晶）。在退火步骤之后，轻掺杂或非掺杂材料将变成晶体（> = 30％结晶）。高带隙材料形成在无定形高掺杂材料和轻掺杂材料和非掺杂材料之间，并提供通过多层电介质叠层的导电的中间屏障。

8. 发明授权

US08563392B2 Method of forming an ALD material 有权
标题翻译：形成ALD材料的方法
公开(公告)号：US08563392B2
公开(公告)日：2013-10-22
申请号：US13310980
申请日：2011-12-05
申请人： Sandra Malhotra , Wim Deweerd , Edward Haywood , Hiroyuki Ode
发明人： Sandra Malhotra , Wim Deweerd , Edward Haywood , Hiroyuki Ode
IPC分类号： H01L21/02
CPC分类号： C23C16/45534 , C23C16/405 , H01L21/28562 , H01L21/32051 , H01L28/60
摘要： In some embodiments of the present invention, methods are developed wherein a gas flow of an electron donating compound (EDC) is introduced in sequence with a precursor pulse and alters the deposition of the precursor material. In some embodiments, the EDC pulse is introduced sequentially with the precursor pulse with a purge step used to remove the non-adsorbed EDC from the process chamber before the precursor is introduced. In some embodiments, the EDC pulse is introduced using a vapor draw technique or a bubbler technique. In some embodiments, the EDC pulse is introduced in the same gas distribution manifold as the precursor pulse. In some embodiments, the EDC pulse is introduced in a separate gas distribution manifold from the precursor pulse.
摘要翻译：在本发明的一些实施方案中，开发了一种方法，其中给电子化合物（EDC）的气流按前驱脉冲依次导入并改变前体材料的沉积。在一些实施方案中，EDC脉冲依次与前体脉冲一起引入，其中吹扫步骤用于在引入前体之前从处理室去除未吸附的EDC。在一些实施例中，使用蒸汽抽吸技术或起泡器技术引入EDC脉冲。在一些实施例中，EDC脉冲被引入与前驱脉冲相同的气体分配歧管中。在一些实施例中，EDC脉冲从前驱脉冲引入到单独的气体分配歧管中。

9. 发明申请

US20130122678A1 ADSORPTION SITE BLOCKING METHOD FOR CO-DOPING ALD FILMS 有权
标题翻译：用于混合ALD膜的吸附位点阻断方法
公开(公告)号：US20130122678A1
公开(公告)日：2013-05-16
申请号：US13294341
申请日：2011-11-11
申请人： Sandra Malhotra , Hanhong Chen , Wim Deweerd , Toshiyuki Hirota , Hiroyuki Ode
发明人： Sandra Malhotra , Hanhong Chen , Wim Deweerd , Toshiyuki Hirota , Hiroyuki Ode
IPC分类号： H01L21/02
CPC分类号： H01L28/60 , C23C16/45534 , H01L21/02175 , H01L21/02178 , H01L21/02186 , H01L21/02189 , H01L21/02194 , H01L21/0228 , H01L27/10852 , H01L28/40 , H01L28/56 , H01L29/4234
摘要： A method for doping a dielectric material by pulsing a first dopant precursor, purging the non-adsorbed precursor, pulsing a second precursor, purging the non-adsorbed precursor, and pulsing a oxidant to form an intermixed layer of two (or more) metal oxide dielectric dopant materials. The method may also be used to form a blocking layer between a bulk dielectric layer and a second electrode layer. The method improves the control of the composition and the control of the uniformity of the dopants throughout the thickness of the doped dielectric material.
摘要翻译：一种用于通过脉冲第一掺杂剂前体掺杂电介质材料的方法，清洗未吸附的前体，脉冲第二前体，净化未吸附的前体，以及脉冲氧化剂以形成两个（或多个）金属氧化物的混合层电介质掺杂剂材料。该方法还可用于在体电介质层和第二电极层之间形成阻挡层。该方法改善了组合物的控制和掺杂介质材料整个厚度均匀性的控制。

10. 发明授权

US08440537B1 Adsorption site blocking method for co-doping ALD films 有权
公开(公告)号：US08440537B1
公开(公告)日：2013-05-14
申请号：US13294341
申请日：2011-11-11
申请人： Sandra Malhotra , Hanhong Chen , Wim Deweerd , Toshiyuki Hirota , Hiroyuki Ode
发明人： Sandra Malhotra , Hanhong Chen , Wim Deweerd , Toshiyuki Hirota , Hiroyuki Ode
IPC分类号： H01L21/20
CPC分类号： H01L28/60 , C23C16/45534 , H01L21/02175 , H01L21/02178 , H01L21/02186 , H01L21/02189 , H01L21/02194 , H01L21/0228 , H01L27/10852 , H01L28/40 , H01L28/56 , H01L29/4234
摘要： A method for doping a dielectric material by pulsing a first dopant precursor, purging the non-adsorbed precursor, pulsing a second precursor, purging the non-adsorbed precursor, and pulsing a oxidant to form an intermixed layer of two (or more) metal oxide dielectric dopant materials. The method may also be used to form a blocking layer between a bulk dielectric layer and a second electrode layer. The method improves the control of the composition and the control of the uniformity of the dopants throughout the thickness of the doped dielectric material.

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