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1. 发明授权

US07151059B2 MOS transistor and method of manufacture 有权
标题翻译： MOS晶体管及其制造方法
公开(公告)号：US07151059B2
公开(公告)日：2006-12-19
申请号：US10762788
申请日：2004-01-22
申请人： Samir Chaudhry , Sidhartha Sen , Sundar Srinivasan Chetlur , Richard William Gregor , Pradip Kumar Roy
发明人： Samir Chaudhry , Sidhartha Sen , Sundar Srinivasan Chetlur , Richard William Gregor , Pradip Kumar Roy
IPC分类号： H01L21/31
CPC分类号： H01L21/28194 , C30B29/06 , C30B33/005 , H01L21/02238 , H01L21/26586 , H01L21/28167 , H01L21/28273 , H01L21/31604 , H01L21/31612 , H01L21/31662 , H01L21/3185 , H01L29/1045 , H01L29/1083 , H01L29/513 , H01L29/517
摘要： A reduced feature size MOS transistor and its method of manufacture is disclosed. The present invention reduces short channel effects but does not include an LDD structure In an illustrative embodiment, a MOS transistor has a gate length of 1.25 μm or less. The exemplary MOS transistor includes a gate oxide that forms a planar and substantially stress free interface with a substrate. As a result of the planarity and substantially stress free nature of the oxide/substrate interface, the incidence of hot carriers, and thereby, deleterious hot carrier effects are reduced. By eliminating the use of the LDD structure, fabrication complexity is reduced and series source-drain resistance is reduced resulting in improved drive current and switching speed.
摘要翻译：公开了减小的特征尺寸MOS晶体管及其制造方法。本发明减少短信道效应，但不包括LDD结构。在说明性实施例中，MOS晶体管的栅极长度为1.25μm或更小。示例性MOS晶体管包括与衬底形成平面且基本上无应力的界面的栅极氧化物。由于氧化物/衬底界面的平坦性和基本无应力的性质，热载流子的发生率以及有害的热载流子效应降低。通过消除LDD结构的使用，制造复杂度降低，串联源极 - 漏极电阻降低，从而提高驱动电流和开关速度。

2. 发明授权

US06740912B1 Semiconductor device free of LLD regions 有权
标题翻译：半导体器件无LLD区域
公开(公告)号：US06740912B1
公开(公告)日：2004-05-25
申请号：US09597012
申请日：2000-06-20
申请人： Samir Chaudhry , Sidharta Sen , Sundar Srinivasan Chetlur , Richard William Gregor , Pradip Kumar Roy
发明人： Samir Chaudhry , Sidharta Sen , Sundar Srinivasan Chetlur , Richard William Gregor , Pradip Kumar Roy
IPC分类号： H01L2976
CPC分类号： H01L21/28194 , C30B29/06 , C30B33/005 , H01L21/02238 , H01L21/26586 , H01L21/28167 , H01L21/28273 , H01L21/31604 , H01L21/31612 , H01L21/31662 , H01L21/3185 , H01L29/1045 , H01L29/1083 , H01L29/513 , H01L29/517
摘要： A reduced feature size MOS transistor and its method of manufacture is disclosed. The present invention reduces short channel effects but does not include an LDD structure In an illustrative embodiment, a MOS transistor has a gate length of 1.25 &mgr;m or less. The exemplary MOS transistor includes a gate oxide that forms a planar and substantially stress free interface with a substrate. As a result of the planarity and substantially stress free nature of the oxide/substrate interface, the incidence of hot carriers, and thereby, deleterious hot carrier effects are reduced. By eliminating the use of the LDD structure, fabrication complexity is reduced and series source-drain resistance is reduced resulting in improved drive current and switching speed.
摘要翻译：公开了减小的特征尺寸MOS晶体管及其制造方法。本发明减少短信道效应，但不包括LDD结构。在说明性实施例中，MOS晶体管的栅极长度为1.25μm或更小。示例性MOS晶体管包括与衬底形成平面且基本上无应力的界面的栅极氧化物。由于氧化物/衬底界面的平坦性和基本无应力的性质，热载流子的发生率以及有害的热载流子效应降低。通过消除LDD结构的使用，制造复杂度降低，串联源极 - 漏极电阻降低，从而提高驱动电流和开关速度。

3. 发明授权

US06576522B2 Methods for deuterium sintering 有权
公开(公告)号：US06576522B2
公开(公告)日：2003-06-10
申请号：US09733570
申请日：2000-12-08
申请人： Sundar Srinivasan Chetlur , Pradip Kumar Roy , Minesh Amrat Patel , Sidhartha Sen , Vivek Saxena
发明人： Sundar Srinivasan Chetlur , Pradip Kumar Roy , Minesh Amrat Patel , Sidhartha Sen , Vivek Saxena
IPC分类号： H01L21336
CPC分类号： H01L21/324 , H01L21/28176 , H01L21/28194 , H01L21/3003 , H01L21/76828 , H01L21/76834
摘要： A method for deuterium sintering to improve the hot carrier aging of an integrated circuit includes (a) providing a partially fabricated integrated circuit structure comprising a semiconductor substrate and a dielectric layer formed on at least a portion of the substrate, the dielectric layer having at least one conductive material via plug formed therein and (b) sintering the structure in the presence of a gas comprising deuterium-containing components at high temperatures prior to a metallization layer being deposited on the structure.

4. 发明授权

US06204186B1 Method of making integrated circuit capacitor including tapered plug 有权
标题翻译：制造集成电路电容器包括锥形插头的方法
公开(公告)号：US06204186B1
公开(公告)日：2001-03-20
申请号：US09364366
申请日：1999-07-30
申请人： Samir Chaudhry , Sundar Srinivasan Chetlur , Nace Layadi , Pradip Kumar Roy , Hem M. Vaidya
发明人： Samir Chaudhry , Sundar Srinivasan Chetlur , Nace Layadi , Pradip Kumar Roy , Hem M. Vaidya
IPC分类号： H01L21311
CPC分类号： H01L28/60 , H01L21/76804 , H01L27/10808 , H01L27/10852 , H01L28/40
摘要： A method of making a capacitor includes the steps of forming an interconnection line above a substrate, depositing a first dielectric layer on the interconnection line, and etching a via in the first dielectric layer. The via has a tapered width which increases in a direction toward the substrate. Further, the method includes filling the via with a conductive metal to form a metal plug, and etching a trench in the first dielectric layer around an upper portion of the metal plug. The metal plug has a tapered width which secures it into the dielectric layer. A second dielectric layer is deposited adjacent the metal plug and an upper electrode is deposited on the second dielectric layer. Preferably, a lower electrode is deposited to line the trench and contact the metal plug.
摘要翻译：一种制造电容器的方法包括以下步骤：在衬底上形成互连线，在互连线上沉积第一介电层，以及蚀刻第一介电层中的通孔。通孔具有朝向基板的方向增加的锥形宽度。此外，该方法包括用导电金属填充通孔以形成金属插塞，并且在金属插塞的上部周围蚀刻第一电介质层中的沟槽。金属插头具有将其固定到电介质层中的锥形宽度。第二电介质层沉积在金属插塞附近，并且上电极沉积在第二电介质层上。优选地，沉积下电极以对准沟槽并接触金属插塞。

5. 发明授权

US06249016B1 Integrated circuit capacitor including tapered plug 有权
标题翻译：集成电路电容器包括锥形插头
公开(公告)号：US06249016B1
公开(公告)日：2001-06-19
申请号：US09364603
申请日：1999-07-30
申请人： Samir Chaudhry , Sundar Srinivasan Chetlur , Nace Layadi , Pradip Kumar Roy , Hem M. Vaidya
发明人： Samir Chaudhry , Sundar Srinivasan Chetlur , Nace Layadi , Pradip Kumar Roy , Hem M. Vaidya
IPC分类号： H01L27108
CPC分类号： H01L27/10852 , H01L27/10808 , H01L28/40
摘要： An integrated circuit capacitor includes a first dielectric layer adjacent a substrate and having a trench therein, and a metal plug comprising an upper portion extending upwardly into the trench, and a lower portion disposed in the first dielectric layer. The lower portion has a tapered width which increases in a direction toward the substrate to thereby secure the metal plug in the dielectric layer. Preferably, the upper portion is also tapered. Furthermore, a second dielectric layer is adjacent the metal plug with an upper electrode thereon.
摘要翻译：集成电路电容器包括与衬底相邻并且在其中具有沟槽的第一电介质层和包括向上延伸到沟槽中的上部的金属插塞和设置在第一电介质层中的下部。下部具有朝向基板的方向增加的锥形宽度，从而将金属塞固定在电介质层中。优选地，上部也是锥形的。此外，第二电介质层与其上的上电极邻近金属插塞。

6. 发明授权

US06291848B1 Integrated circuit capacitor including anchored plugs 有权
标题翻译：集成电路电容器，包括固定插头
公开(公告)号：US06291848B1
公开(公告)日：2001-09-18
申请号：US09364767
申请日：1999-07-30
申请人： Sundar Srinivasan Chetlur , James Theodore Clemens , Sailesh Mansinh Merchant , Pradip Kumar Roy , Hem M. Vaidya
发明人： Sundar Srinivasan Chetlur , James Theodore Clemens , Sailesh Mansinh Merchant , Pradip Kumar Roy , Hem M. Vaidya
IPC分类号： H01L27108
CPC分类号： H01L21/76838 , H01L27/10817 , H01L27/10852 , H01L28/60
摘要： An integrated circuit capacitor includes a substrate, a first dielectric layer adjacent the substrate and having a first trench therein, and a first metal plug extending upwardly into the first trench. An interconnection line overlies the first trench and contacts the first metal plug to define anchoring recesses on opposite sides of the first metal plug. A second dielectric layer is on the interconnection line and has a second trench therein. A second metal plug extends upwardly into the second trench. More particularly, the second metal plug includes a body portion extending upwardly into the second trench, and anchor portions connected to the body portion and engaging the anchoring recesses to anchor the second metal plug to the interconnection line. Because the second metal plug is anchored, a depth of the second trench can be greater without the metal plug becoming loose and separating from the underlying interconnection line.
摘要翻译：集成电路电容器包括衬底，与衬底相邻并且在其中具有第一沟槽的第一电介质层和向上延伸到第一沟槽中的第一金属插塞。互连线覆盖在第一沟槽上并接触第一金属插塞以在第一金属插塞的相对侧上限定锚定凹槽。第二介电层位于互连线上并且在其中具有第二沟槽。第二金属插头向上延伸到第二沟槽中。更具体地，第二金属插头包括向上延伸到第二沟槽中的主体部分，以及连接到主体部分并且与固定凹部接合并将第二金属插头固定到互连线的锚定部分。由于第二金属插塞被锚固，所以第二沟槽的深度可以更大，而不会使金属插头松动并与下面的互连线分离。

7. 发明授权

US07148153B2 Process for oxide fabrication using oxidation steps below and above a threshold temperature 有权
公开(公告)号：US07148153B2
公开(公告)日：2006-12-12
申请号：US10316386
申请日：2002-12-11
申请人： Yuanning Chen , Sundar Srinivasan Chetlur , Pradip Kumar Roy
发明人： Yuanning Chen , Sundar Srinivasan Chetlur , Pradip Kumar Roy
IPC分类号： H01L21/31
CPC分类号： H01L21/28185 , H01L21/28211 , H01L29/513 , H01L29/517
摘要： A process for forming an oxide layer includes forming a first oxide portion over a substrate at a temperature below a threshold temperature. A second oxide portion is formed under the first oxide portion at a temperature above the threshold temperature. The substrate is illustratively oxidizable silicon and the threshold temperature is the viscoelastic temperature of silicon dioxide.

8. 发明授权

US06535014B2 Electrical parameter tester having decoupling means 失效
标题翻译：具有去耦装置的电气参数测试仪
公开(公告)号：US06535014B2
公开(公告)日：2003-03-18
申请号：US09756480
申请日：2001-01-08
申请人： Sundar Srinivasan Chetlur , Pradip Kumar Roy
发明人： Sundar Srinivasan Chetlur , Pradip Kumar Roy
IPC分类号： G01R3126
CPC分类号： G01R31/2879
摘要： A tester for a circuit path includes a voltage controlled oscillator (VCO) for generating a controllable frequency oscillating test signal and having a controllable amplitude defined between first and second voltages, a multiplexer for selectively connecting one of the oscillating test signal, the first voltage, and the second voltage to the circuit path, and a selector for selectively connecting the multiplexer to the circuit path. Moreover, at least one of the first and second voltages may be controllable so that the VCO generates the oscillating test signal to selectively have one of an amplitude greater than, less than, and equal to an amplitude of an output of the circuit path. The circuit path may include a plurality of electronic circuit devices connected together.
摘要翻译：用于电路路径的测试器包括用于产生可控频率振荡测试信号并具有在第一和第二电压之间限定的可控幅度的压控振荡器（VCO）;多路复用器，用于选择性地将振荡测试信号，第一电压，和电路路径的第二电压，以及用于选择性地将多路复用器连接到电路路径的选择器。此外，第一和第二电压中的至少一个可以是可控的，使得VCO产生振荡测试信号以选择性地具有大于，小于和等于电路路径的输出的幅度的幅度。电路路径可以包括连接在一起的多个电子电路装置。

9. 发明授权

US06492712B1 High quality oxide for use in integrated circuits 有权
标题翻译：高品质氧化物用于集成电路
公开(公告)号：US06492712B1
公开(公告)日：2002-12-10
申请号：US09597077
申请日：2000-06-20
申请人： Yuanning Chen , Sundar Srinivasan Chetlur , Sailesh Mansinh Merchant , Pradip Kumar Roy
发明人： Yuanning Chen , Sundar Srinivasan Chetlur , Sailesh Mansinh Merchant , Pradip Kumar Roy
IPC分类号： H01L21316
CPC分类号： C30B29/06 , C30B33/005 , H01L21/02238 , H01L21/02255 , H01L21/28185 , H01L21/28211 , H01L21/28273 , H01L21/31662 , H01L29/513 , H01L29/518
摘要： An oxide for use in integrated circuits is substantially stress-free both in the bulk and at the interface between the substrate and the oxide. The interface is planar and has a low interface trap density (Nit). The oxide has a low defect density and may have a thickness of less than 1.5 nm or less.
摘要翻译：用于集成电路的氧化物在本体和衬底与氧化物之间的界面处基本上是无应力的。界面是平面的，并且具有低的界面陷阱密度（Nit）。氧化物的缺陷密度低，可以具有小于1.5nm以下的厚度。

10. 发明授权

US6103586A Method for making integrated circuit capacitor including anchored plugs 有权
标题翻译：制造集成电路电容器包括固定插头的方法
公开(公告)号：US6103586A
公开(公告)日：2000-08-15
申请号：US364025
申请日：1999-07-30
申请人： Sundar Srinivasan Chetlur , James Theodore Clemens , Sailesh Mansinh Merchant , Pradip Kumar Roy , Hem M. Vaidya
发明人： Sundar Srinivasan Chetlur , James Theodore Clemens , Sailesh Mansinh Merchant , Pradip Kumar Roy , Hem M. Vaidya
IPC分类号： H01L21/8242 , H01L21/02 , H01L21/768 , H01L27/108 , H01L21/20
CPC分类号： H01L28/60 , H01L21/76838 , H01L21/76895
摘要： A method for making an integrated circuit capacitor includes forming a first dielectric layer adjacent a substrate, forming a first opening in the first dielectric layer, filling the first opening with a conductive material to define a first metal plug, and forming a trench in the first dielectric layer adjacent the first metal plug. An interconnection line lines the first trench and contacts the first metal plug to define anchoring recesses on opposite sides of the first metal plug. The method further includes forming a second dielectric layer on the interconnection line, forming a second opening in the second dielectric layer, and filling the second opening with a conductive metal to define a second metal plug having a body portion and anchor portions extending downward from the body portion for engaging the anchoring recesses to anchor the second metal plug. A second trench is formed in the second dielectric layer adjacent the second metal plug, and is aligned with the first trench. Because the second metal plug is anchored, a depth of the second trench can be greater without the metal plug becoming loose and separating from the underlying interconnection line. The electrodes and dielectric layers of the capacitor are formed so that they line the second trench.
摘要翻译：一种制造集成电路电容器的方法包括：在基片附近形成第一电介质层，在第一电介质层中形成第一开口，用导电材料填充第一开口以限定第一金属插塞，并在第一电介质层中形成沟槽电介质层邻近第一金属插头。互连线对准第一沟槽并接触第一金属插塞以在第一金属插塞的相对侧上限定锚定凹槽。所述方法还包括在所述互连线上形成第二电介质层，在所述第二电介质层中形成第二开口，并用导电金属填充所述第二开口，以限定第二金属插塞，所述第二金属插塞具有主体部分和从所述第二介质层向下延伸的固定部分主体部分，用于接合所述锚定凹部以锚定所述第二金属插塞。在与第二金属插塞相邻的第二电介质层中形成第二沟槽，并且与第一沟槽对准。由于第二金属插塞被锚固，所以第二沟槽的深度可以更大，而不会使金属插头松动并与下面的互连线分离。电容器的电极和电介质层形成为使得它们与第二沟槽对齐。

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