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1. 发明授权

US3989656A Dextran-alkyl methacrylate graft composition for contact lens and corneas 失效
标题翻译：用于隐形眼镜和角膜的葡聚糖 - 甲基丙烯酸烷基酯接枝组合物
公开(公告)号：US3989656A
公开(公告)日：1976-11-02
申请号：US539151
申请日：1975-01-06
申请人： Sadayoshi Kamiya , Tokihiko Yamamoto , Yasuhiko Onishi , Shusaburo Hokkoku
发明人： Sadayoshi Kamiya , Tokihiko Yamamoto , Yasuhiko Onishi , Shusaburo Hokkoku
IPC分类号： C02F1/52 , C02F1/54 , C08F251/00 , C08L5/02
CPC分类号： C02F1/54 , C02F1/5263 , C08F251/00
摘要： A dextran-alkyl methacrylate graft composition consisting essentially of a dextran unit of the formula (1) ##SPC1##Wherein n is an integer of 5 to 150,000, and a poly(alkyl methacrylate) unit of the formula (2) ##EQU1## WHEREIN M IS AN INTEGER OF 50 TO 200,000 AND R is an alkyl group having 1 to 4 carbon atoms,And a process for producing the same.
摘要翻译：基本上由式（1）的右旋糖酐单元组成的基于葡聚糖 - 甲基丙烯酸烷基酯的接枝组合物，其中N为5至150,000的整数，以及式（2）CH 3 | -CH 2 -C的聚（甲基丙烯酸烷基酯）单元 ---- | COORm（2）其中M为50至200,000的整数，R为具有1至4个碳原子的烷基，以及其制备方法。

2. 发明申请

US20130026560A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20130026560A1
公开(公告)日：2013-01-31
申请号：US13575984
申请日：2011-01-28
申请人： Yasuhiko Onishi , Mutsumi Kitamura , Akio Sugi , Manabu Takei
发明人： Yasuhiko Onishi , Mutsumi Kitamura , Akio Sugi , Manabu Takei
IPC分类号： H01L29/78
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/66712 , H01L29/7813
摘要： A parallel p-n layer (20) is provided as a drift layer between an active portion and an n+ drain region (11). The parallel p-n layer (20) is formed by an n-type region (1) and a p-type region (2) being repeatedly alternately joined. An n-type high concentration region (21) is provided on a first main surface side of the n-type region (1). The n-type high concentration region (21) has an impurity concentration higher than that of an n-type low concentration region (22) provided on a second main surface side of the n-type region (1). The n-type high concentration region (21) has an impurity concentration 1.2 times or more, 3 times or less, preferably 1.5 times or more, 2.5 times or less, greater than that of the n-type low concentration region (22). Also, the n-type high concentration region (21) has one-third or less, preferably one-eighth or more, one-fourth or less, of the thickness of a region of the n-type region (1) adjacent to the p-type region (2).
摘要翻译：在活性部分和n +漏极区域（11）之间提供平行p-n层（20）作为漂移层。平行p-n层（20）由n型区域（1）和重复交替接合的p型区域（2）形成。 n型高浓度区域（21）设置在n型区域（1）的第一主表面侧。 n型高浓度区域（21）的杂质浓度高于设置在n型区域（1）的第二主面侧的n型低浓度区域（22）的杂质浓度。 n型高浓度区域（21）的杂质浓度比n型低浓度区域（22）的杂质浓度大1.2倍以上3倍以下，优选为1.5倍以上2.5倍以下。此外，n型高浓度区域（21）的n区域（1）的相邻区域的厚度的三分之一以下，优选为八分之一以上，四分之一以下。 p型区域（2）。

3. 发明授权

US06768167B2 MIS semiconductor device and the manufacturing method thereof 失效
公开(公告)号：US06768167B2
公开(公告)日：2004-07-27
申请号：US10442647
申请日：2003-05-21
申请人： Tatsuji Nagaoka , Tatsuhiko Fujihira , Yasuhiko Onishi
发明人： Tatsuji Nagaoka , Tatsuhiko Fujihira , Yasuhiko Onishi
IPC分类号： H01L2976
CPC分类号： H01L29/7802 , H01L27/0207 , H01L29/0696 , H01L29/4175 , H01L29/41766 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： A MIS semiconductor device has a greatly improved relation between the on-resistance and the switching time by forming trench completely through a p base region and positioning the trench adjacent to a gate electrode, and then implanting n-type impurity ions using the gate electrode as a mask to form a second drain region, which also serves as a drift region.

4. 发明授权

US06724042B2 Super-junction semiconductor device 有权
标题翻译：超结半导体器件
公开(公告)号：US06724042B2
公开(公告)日：2004-04-20
申请号：US09781066
申请日：2001-02-09
申请人： Yasuhiko Onishi , Tatsuhiko Fujihira , Katsunori Ueno , Susumu Iwamoto , Takahiro Sato , Tatsuji Nagaoka
发明人： Yasuhiko Onishi , Tatsuhiko Fujihira , Katsunori Ueno , Susumu Iwamoto , Takahiro Sato , Tatsuji Nagaoka
IPC分类号： H01L2976
CPC分类号： H01L29/7811 , H01L29/0619 , H01L29/0634 , H01L29/0696 , H01L29/66333 , H01L29/66712 , H01L29/7395 , H01L29/7802 , H01L2924/0002 , H01L2924/00
摘要： Disclosed is a semiconductor device facilitating a peripheral portion thereof with a breakdown voltage higher than the breakdown voltage in the drain drift layer without employing a guard ring or field plate. A preferred embodiment includes a drain drift region with a first alternating conductivity type layer formed of n drift current path regions and p partition regions arranged alternately with each other, and a breakdown withstanding region with a second alternating conductivity type layer formed of n regions and p regions arranged alternately with each other, the breakdown withstanding region providing no current path in the ON-state of the device and being depleted in the OFF-state of the device. Since depletion layers expand in both directions from multiple pn-junctions into n regions and p regions in the OFF-state of the device, the adjacent areas of p-type base regions, the outer area of the semiconductor chip and the deep area of the semiconductor chip are depleted. Thus, the breakdown voltage of breakdown withstanding region is higher than the breakdown voltage of drain drift region.
摘要翻译：公开了一种半导体器件，其使用其周边部分具有高于漏极漂移层中的击穿电压的击穿电压，而不采用保护环或场板。优选实施例包括漏极漂移区，其具有由n个漂移电流通路区域和彼此交替布置的p个分隔区域形成的第一交变导电类型层，以及具有由n个区域和p形成的第二交变导电类型层的击穿承受区域区域彼此交替布置，击穿承受区域在设备的接通状态下不提供电流路径，并且在器件的关断状态被耗尽。由于耗尽层从多个pn结到两个方向扩展到设备的OFF状态的n个区域和p区域，所以p型基极区域的相邻区域，半导体芯片的外部区域和半导体芯片耗尽。因此，击穿耐受区域的击穿电压高于漏极漂移区域的击穿电压。

5. 发明授权

US06700141B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06700141B2
公开(公告)日：2004-03-02
申请号：US09978847
申请日：2001-10-17
申请人： Susumu Iwamoto , Tatsuhiko Fujihira , Katsunori Ueno , Yasuhiko Onishi , Takahiro Sato
发明人： Susumu Iwamoto , Tatsuhiko Fujihira , Katsunori Ueno , Yasuhiko Onishi , Takahiro Sato
IPC分类号： H01L2936
CPC分类号： H01L29/7811 , H01L29/0634 , H01L29/7802
摘要： A reliable super-junction semiconductor device is provided that facilitates relaxing the tradeoff relation between the on-resistance and the breakdown voltage and improving the avalanche withstanding capability under an inductive load. The super-junction semiconductor device includes an active region including a thin first alternating conductivity type layer and a heavily doped n+-type intermediate drain layer between first alternating conductivity type layer and an n++-type drain layer, and a breakdown withstanding region including a thick second alternating conductivity type layer. Alternatively, active region includes a first alternating conductivity type layer and a third alternating conductivity type layer between first alternating conductivity type layer and n++-type drain layer, third alternating conductivity type layer being doped more heavily than first alternating conductivity type layer.
摘要翻译：提供了可靠的超结半导体器件，其有助于放松导通电阻和击穿电压之间的折衷关系，并提高在感性负载下的雪崩耐受能力。超结半导体器件包括在第一交替导电型层和n ++类漏极层之间包括薄的第一交替导电型层和重掺杂n +型中间漏极层的有源区，以及包括厚的第二交替导电类型层的击穿耐受区域。或者，有源区包括第一交替导电类型层和第n +型漏极之间的第一交变导电类型层和第三交变导电类型层，第三交变导电类型层比第一交变导电类型层更重掺杂。

6. 发明授权

US06677643B2 Super-junction semiconductor device 有权
标题翻译：超结半导体器件
公开(公告)号：US06677643B2
公开(公告)日：2004-01-13
申请号：US09811727
申请日：2001-03-19
申请人： Susumu Iwamoto , Tatsuhiko Fujihira , Katsunori Ueno , Yasuhiko Onishi , Takahiro Sato
发明人： Susumu Iwamoto , Tatsuhiko Fujihira , Katsunori Ueno , Yasuhiko Onishi , Takahiro Sato
IPC分类号： H01L2976
CPC分类号： H01L21/26513 , H01L21/266 , H01L29/0634 , H01L29/1095 , H01L29/7802
摘要： A super-junction semiconductor is provided that facilitates easy mass-production thereof, reducing the tradeoff relation between the on-resistance and the breakdown voltage, obtaining a high breakdown voltage and reducing the on-resistance to increase the current capacity thereof. The super-junction semiconductor device includes a semiconductor chip having a first major surface and a second major surface facing in opposite to the first major surface; a layer with low electrical resistance on the side of the second major surface; a first alternating conductivity type layer on low resistance layer, and a second alternating conductivity type layer on the first alternating conductivity type layer. The first alternating conductivity type layer including regions of a first conductivity type and regions of a second conductivity type arranged alternately with each other. The second alternating conductivity type layer including regions of the first conductivity type and regions of the second conductivity type arranged alternately with each other. The spacing between the pn-junctions in the second alternating conductivity type layer is wider than the spacing between the pn-junctions in the first alternating conductivity type layer.
摘要翻译：提供了一种能够容易地进行批量生产，降低导通电阻和击穿电压之间的折衷关系的超结半导体，获得高的击穿电压并降低导通电阻以增加其电流容量。超结半导体器件包括具有第一主表面和面向第一主表面的第二主表面的半导体芯片; 在第二主表面侧具有低电阻的层; 低电阻层上的第一交替导电类型层和第一交变导电类型层上的第二交变导电类型层。第一交变导电类型层包括彼此交替排列的第一导电类型的区域和第二导电类型的区域。包括第一导电类型的区域和第二导电类型的区域的第二交替导电类型层彼此交替排列。第二交变导电类型层中的pn结之间的间隔比第一交变导电类型层中的pn结之间的间隔宽。

7. 发明授权

US06621132B2 Semiconductor device 有权
标题翻译：半导体器件
公开(公告)号：US06621132B2
公开(公告)日：2003-09-16
申请号：US09942378
申请日：2001-08-30
申请人： Yasuhiko Onishi , Tatsuhiko Fujihira , Katsunori Ueno , Susumu Iwamoto , Takahiro Sato
发明人： Yasuhiko Onishi , Tatsuhiko Fujihira , Katsunori Ueno , Susumu Iwamoto , Takahiro Sato
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/0634 , H01L29/0696
摘要： The super-junction semiconductor device, which facilitates increased switching speed and reduced on-resistance, includes an alternating conductivity type layer formed of n-type drift regions and p-type partition regions arranged alternately, a pair of the n-type drift region and p-type partition region repeating at a first repeating pitch, and trenches each containing a gate electrode buried therein, the trenches being arranged repeatedly at a second repeating pitch wider than the first repeating pitch. The device further includes one or more n-type channel regions between a p-type partition regions and a p-type well region.
摘要翻译：有助于提高开关速度和降低导通电阻的超结半导体器件包括由n型漂移区和交替布置的p型分隔区形成的交替导电型层，一对n型漂移区和以第一重复间距重复的p型分隔区和每个包含埋入其中的栅电极的沟槽，所述沟槽以比第一重复间距更宽的第二重复间距重复布置。该装置还包括在p型分隔区域和p型阱区域之间的一个或多个n型沟道区域。

8. 发明授权

US06576935B2 Bidirectional semiconductor device and method of manufacturing the same 有权
公开(公告)号：US06576935B2
公开(公告)日：2003-06-10
申请号：US09894989
申请日：2001-06-28
申请人： Yasuhiko Onishi , Tatsuhiko Fujihira , Susumu Iwamoto , Takahiro Sato
发明人： Yasuhiko Onishi , Tatsuhiko Fujihira , Susumu Iwamoto , Takahiro Sato
IPC分类号： H01L2974
CPC分类号： H01L29/7824 , H01L29/0634 , H01L29/0696 , H01L29/7801 , H01L29/7802 , H01L29/7825 , H01L29/7831
摘要： A bidirectional semiconductor device facilitates making a current flow from the first MOSFET to the second MOSFET and vice versa across low on-resistance and exhibits a high breakdown voltage. The bidirectional semiconductor device includes a first n-channel MOSFET including base regions, a second n-channel MOSFET including base regions, and an alternating conductivity type layer formed of drift region and partition regions arranged alternately. Partition regions are isolated from base regions by a high resistivity region and from base regions by a high resistivity region to maintaining a high breakdown voltage between first MOSFET and the second MOSFET. By connecting high resistivity regions and via drift regions to each other, a current is made flow from the first MOSFET to the second MOSFET and vice versa and the on-voltage is reduced.

9. 发明授权

US5309625A Card type fuse and method of producing the same 失效
标题翻译：卡式保险丝及其制造方法
公开(公告)号：US5309625A
公开(公告)日：1994-05-10
申请号：US71689
申请日：1993-06-03
申请人： Yasuhiko Onishi
发明人： Yasuhiko Onishi
IPC分类号： H01H69/02 , H01H85/00 , H01H85/02 , H01H85/044 , H01H85/046 , H01H85/06 , H01H85/10 , H01H85/11 , H01H85/17 , H05K1/00 , H05K1/09 , H05K3/20 , H05K3/28 , H01H85/04
CPC分类号： H01H85/046 , H05K1/0293 , H01H69/022 , H05K1/095 , H05K2201/09118 , H05K2201/09727 , H05K2201/10181 , H05K3/207 , H05K3/281 , Y10T29/49107
摘要： A card type fuse aimed at reducing production costs and improving a forming precision of an exothermic fusing portion 2a. The card type fuse comprises an insulation substratum 1, fuse circuits 2 arranged on the insulation substratum 1 and having a narrow exothermic fusing portion 2a, and a cover layer 3 covering fuse circuits 2. The cover layer 3 is made of a heat resisting film. The fuse circuits 2 are printed on the heat resisting film by means of a conductive paste. The insulation substratum 1 is made of a heat resisting thermoplastic resin suitable for an SMT. The insulation substratum 1 is integrally formed on the side having the fuse circuits on the heat resisting film.
摘要翻译：一种卡式保险丝，旨在降低生产成本并提高放热熔化部分2a的成形精度。卡式保险丝包括绝缘基底1，布置在绝缘基底1上的熔丝电路2，并具有窄的放热定影部分2a和覆盖熔丝电路2的覆盖层3.覆盖层3由耐热膜制成。熔丝电路2通过导电膏印在耐热膜上。绝缘基材1由适合于SMT的耐热性热塑性树脂制成。绝缘基体1一体地形成在耐热膜上具有熔丝电路的一侧上。

10. 发明授权

US09087893B2 Superjunction semiconductor device with reduced switching loss 有权
标题翻译：具有降低开关损耗的超结半导体器件
公开(公告)号：US09087893B2
公开(公告)日：2015-07-21
申请号：US13575984
申请日：2011-01-28
申请人： Yasuhiko Onishi , Mutsumi Kitamura , Akio Sugi , Manabu Takei
发明人： Yasuhiko Onishi , Mutsumi Kitamura , Akio Sugi , Manabu Takei
IPC分类号： H01L29/66 , H01L29/78 , H01L29/06 , H01L29/08 , H01L29/10
CPC分类号： H01L29/7802 , H01L29/0634 , H01L29/0878 , H01L29/1095 , H01L29/66712 , H01L29/7813
摘要： A parallel p-n layer (20) is provided as a drift layer between an active portion and an n+ drain region (11). The parallel p-n layer (20) is formed by an n-type region (1) and a p-type region (2) being repeatedly alternately joined. An n-type high concentration region (21) is provided on a first main surface side of the n-type region (1). The n-type high concentration region (21) has an impurity concentration higher than that of an n-type low concentration region (22) provided on a second main surface side of the n-type region (1). The n-type high concentration region (21) has an impurity concentration 1.2 times or more, 3 times or less, preferably 1.5 times or more, 2.5 times or less, greater than that of the n-type low concentration region (22). Also, the n-type high concentration region (21) has one-third or less, preferably one-eighth or more, one-fourth or less, of the thickness of a region of the n-type region (1) adjacent to the p-type region (2).
摘要翻译：在活性部分和n +漏极区域（11）之间提供平行p-n层（20）作为漂移层。平行p-n层（20）由n型区域（1）和重复交替接合的p型区域（2）形成。 n型高浓度区域（21）设置在n型区域（1）的第一主表面侧。 n型高浓度区域（21）的杂质浓度高于设置在n型区域（1）的第二主面侧的n型低浓度区域（22）的杂质浓度。 n型高浓度区域（21）的杂质浓度比n型低浓度区域（22）的杂质浓度大1.2倍以上3倍以下，优选为1.5倍以上2.5倍以下。此外，n型高浓度区域（21）的n区域（1）的相邻区域的厚度的三分之一以下，优选为八分之一以上，四分之一以下。 p型区域（2）。

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