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1. 发明申请

US20180322940A1 MEMORY SYSTEM AND OPERATION METHOD OF THE SAME 审中-公开
公开(公告)号：US20180322940A1
公开(公告)日：2018-11-08
申请号：US15832205
申请日：2017-12-05
申请人： SK hynix Inc.
发明人： Yong-Ju Kim , Dong-Gun Kim , Do-Sun Hong
IPC分类号： G11C29/52 , G11C13/00 , G06F11/10 , G06F3/06
CPC分类号： G11C29/52 , G06F3/0659 , G06F11/1068 , G11C13/0004 , G11C13/004 , G11C13/0069 , G11C2211/4062
摘要： A method for operating a memory system includes: reading a data from a memory device; detecting and correcting an error of the data; when the error of the data is equal to or greater than a threshold value, deciding an address corresponding to memory cells from which the data is read in the memory device as a rewrite-requiring address; and rewriting the data of the memory cell corresponding to the rewrite-requiring address.

2. 发明授权

US10079606B2 Clock generation circuit 有权
公开(公告)号：US10079606B2
公开(公告)日：2018-09-18
申请号：US14793451
申请日：2015-07-07
申请人： SK hynix Inc.
发明人： Hae-Rang Choi , Yong-Ju Kim , Dae-Han Kwon , Shin-Deok Kang
IPC分类号： H03D3/24 , H03K23/66 , G06F1/04
CPC分类号： H03K23/662 , G06F1/04
摘要： A clock generation circuit includes a clock generation unit suitable for generating a first clock, a first inversion clock having an opposite phase to the first clock, a second clock having a different phase from the first clock, and a second inversion clock having an opposite phase to the second clock; and a reset control unit suitable for comparing the phases of the first and second clocks, and controlling the clock generation unit to disable for a time and then enable the second clock and the second inversion clock when the second clock leads the first clock.

3. 发明授权

US09787296B1 Delay circuit 有权
公开(公告)号：US09787296B1
公开(公告)日：2017-10-10
申请号：US15234954
申请日：2016-08-11
申请人： SK hynix Inc.
发明人： Sung-Eun Lee , Kyung-Hoon Kim , Myeong-Jae Park , Woo-Yeol Shin , Han-Kyu Chi , Yong-Ju Kim
IPC分类号： H03K5/159 , H03K21/38 , H03K5/00
CPC分类号： H03K5/159 , H03K5/131 , H03K21/38 , H03K2005/00078 , H03K2005/00247 , H03K2005/00273
摘要： A delay circuit includes: a plurality of delay units that are serially coupled with each other in a form of loop and sequentially delay an input signal of the delay circuit; an input control unit that selects a delay unit to receive the input signal of the delay circuit among the plurality of the delay units; and an output control unit that controls an output signal of a predetermined delay unit among the plurality of the delay units to be outputted as an output signal of the delay circuit, when the output signal of the predetermined delay unit is enabled N times, where N is an integer equal to or greater than 0.

4. 发明授权

US09361969B2 Semiconductor device and method for driving the same 有权
标题翻译：半导体装置及其驱动方法
公开(公告)号：US09361969B2
公开(公告)日：2016-06-07
申请号：US14278031
申请日：2014-05-15
申请人： SK hynix Inc.
发明人： Yong-Ju Kim , Dae-Han Kwon , Hae-Rang Choi , Jae-Min Jang
IPC分类号： G11C7/04 , G11C11/406
CPC分类号： G11C11/40626
摘要： A semiconductor device includes a periodic signal generating circuit for generating a periodic signal having a set period regardless of changes in temperature in response to a first trimming signal as a default value and controlling the set period of the periodic signal based on the temperature in response to a second trimming signal, and an internal circuit to perform a set operation in response to the periodic signal.
摘要翻译：一种半导体器件包括周期性信号发生电路，用于响应于作为默认值的第一微调信号产生具有设定周期而不管温度变化的周期信号，并且响应于该温度控制周期信号的设定周期第二微调信号和内部电路，以响应周期信号执行设定操作。

5. 发明授权

US09257968B2 Duty cycle correction circuit and operation method thereof 有权
公开(公告)号：US09257968B2
公开(公告)日：2016-02-09
申请号：US14668542
申请日：2015-03-25
申请人： SK hynix Inc.
发明人： Shin-Deok Kang , Jae-Min Jang , Yong-Ju Kim , Hae-Rang Choi
IPC分类号： H03K3/017 , H03K5/156
CPC分类号： H03K3/017 , H03K5/1565
摘要： A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.

6. 发明授权

US10346301B2 Memory system and method for operating the same 有权
公开(公告)号：US10346301B2
公开(公告)日：2019-07-09
申请号：US15653990
申请日：2017-07-19
申请人： SK hynix Inc.
发明人： Sang-Gu Jo , Yong-Ju Kim
IPC分类号： G06F12/0804 , G06F12/06 , G06F13/16 , G11C11/34 , G11C11/407 , G11C29/44 , G11C29/00
摘要： A memory system includes: a memory device; and a memory controller suitable for controlling the memory device, and the memory device includes: a plurality of normal memory cells; a plurality of redundant memory cells; and a soft repair circuit suitable for replacing a portion of normal memory cells among the plurality of the normal memory cells with the plurality of the redundant memory cells, and the memory controller controls the soft repair circuit to repair the portion of the normal memory cells among the plurality of the normal memory cells with the plurality of the redundant memory cells, commands the memory device to write a secure data in the plurality of the redundant memory cells, and controls the soft repair circuit to recover the repairing of the portion of the normal memory cells with the plurality of the redundant memory cells.

7. 发明授权

US10114587B2 Memory device using extra read and write commands 有权
公开(公告)号：US10114587B2
公开(公告)日：2018-10-30
申请号：US15148911
申请日：2016-05-06
申请人： SK hynix Inc.
发明人： Young-Ook Song , Ki-Joong Kim , Jung-Hyun Kwon , Yong-Ju Kim
IPC分类号： G06F3/06 , G06F13/16 , G06F13/00
摘要： A memory device may include one or more multi-channel memories and an interface unit suitable for interfacing the multi-channel memories. The interface unit may include a first data interface suitable for transferring data for the first channel of the multi-channel memories, a second data interface suitable for transferring data for the second channel of the multi-channel memories, and an extra data interface suitable for transferring data for a selected one of the first channel and the second channel so that the data is additionally transmitted.

8. 发明授权

US09627095B1 Memory module, memory system including the same and operation method thereof 有权
公开(公告)号：US09627095B1
公开(公告)日：2017-04-18
申请号：US15230122
申请日：2016-08-05
申请人： SK hynix Inc.
发明人： Jing-Zhe Xu , Yong-Ju Kim , Jung-Hyun Kwon , Sung-Eun Lee , Jae-Sun Lee
IPC分类号： G11C29/00 , G11C11/4074 , G11C11/4076 , G11C11/4093 , G11C11/408 , G11C11/4094 , G11C17/16
CPC分类号： G11C29/76 , G06F12/0246 , G11C5/04 , G11C11/4076 , G11C11/4087 , G11C11/4093 , G11C17/16 , G11C29/72 , G11C29/78 , G11C29/781 , G11C29/808 , G11C29/814 , G11C29/832 , G11C29/84 , G11C29/886
摘要： A memory system may include a memory module comprising a plurality of memory chips mounted therein each memory chip comprising a plurality of banks, the memory chips being simultaneously accessible based on the same command and address; and a memory controller suitable for mapping the banks of the memory chips to each other while rearranging an order of the banks of each of the memory chips based on repair information of the memory chips.

9. 发明授权

US09424894B2 Signal transfer circuit and operating method thereof 有权
标题翻译：信号传输电路及其操作方法
公开(公告)号：US09424894B2
公开(公告)日：2016-08-23
申请号：US14505115
申请日：2014-10-02
申请人： SK hynix Inc.
发明人： Youk-Hee Kim , Yong-Ju Kim
IPC分类号： H03K3/00 , G11C7/10
CPC分类号： G11C7/1078 , G11C7/106 , G11C7/1084 , G11C7/1087
摘要： A signal transfer circuit includes a signal input unit suitable for generating an input signal corresponding to a first voltage level and a second voltage level, a transfer control unit suitable for controlling a driving path of a transfer node in response to a control signal and selectively driving the transfer node to the second voltage level or a third voltage level, which is higher than the first voltage level, based on the driving path in response to the input signal, and an output control unit suitable for outputting an output signal by driving an output node based on a voltage level of the transfer node or maintaining a previous voltage level of the output node in response to the control signal.
摘要翻译：信号传输电路包括适于产生对应于第一电压电平和第二电压电平的输入信号的信号输入单元，适于响应于控制信号控制传输节点的驱动路径并选择性驱动的传送控制单元基于响应于输入信号的驱动路径而将传输节点转换到第二电压电平或高于第一电压电平的第三电压电平，以及输出控制单元，其适于通过驱动输出来输出输出信号基于传输节点的电压电平或者响应于控制信号保持输出节点的先前电压电平。

10. 发明授权

US09128511B2 Semiconductor device and operation method thereof 有权
标题翻译：半导体装置及其动作方法
公开(公告)号：US09128511B2
公开(公告)日：2015-09-08
申请号：US13709991
申请日：2012-12-10
申请人： SK hynix Inc.
发明人： Hae-Rang Choi , Yong-Ju Kim , Dae-Han Kwon , Jae-Min Jang
IPC分类号： G06F3/00 , G11C7/22 , G11C7/10 , G11C11/4076 , G11C11/4093 , G11C11/4096
CPC分类号： G06F3/00 , G11C7/1012 , G11C7/1066 , G11C7/109 , G11C7/1093 , G11C7/22 , G11C11/4076 , G11C11/4093 , G11C11/4096
摘要： A semiconductor device includes a characteristic code storage unit configured to store signal transfer characteristic information input through a given pad and output a control code corresponding to the signal transfer characteristic information, and a characteristic reflection unit configured to reflect the signal transfer characteristic information in an input signal input through the given pad, in response to the control code, and to output the reflected input signal.
摘要翻译：半导体器件包括：特征码存储单元，被配置为存储通过给定焊盘输入的信号传送特性信息，并输出与信号传送特性信息相对应的控制代码;以及特性反射单元，被配置为将信号传送特性信息反映在输入响应于控制代码通过给定焊盘的信号输入，并输出反射的输入信号。

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