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1. 发明授权

US11409668B2 Memory module, operation method of memory module, memory system, and operation method of memory system 有权
公开(公告)号：US11409668B2
公开(公告)日：2022-08-09
申请号：US16728143
申请日：2019-12-27
申请人： SK hynix Inc.
发明人： Woongrae Kim , Sang-Kwon Lee , Jung-Hyun Kim , Jong-Hyun Park , Jong-Ho Son , Mi-Hyun Hwang , Jeong-Tae Hwang
IPC分类号： H04L29/06 , G06F12/14 , H04L9/08 , G06F3/06 , G06F13/16
摘要： A memory module includes: a plurality of memories, wherein each of the memories comprises: an encryption key storage circuit suitable for storing an encryption key; an address encryption circuit suitable for generating an encrypted address by encrypting an address transferred from a memory controller by using the encryption key stored in the encryption key storage circuit; and a cell array accessed by the encrypted address, wherein the encryption key storage circuits of the memories store different encryption keys.

2. 发明授权

US11107546B2 Memory device and operating method thereof 有权
公开(公告)号：US11107546B2
公开(公告)日：2021-08-31
申请号：US16726741
申请日：2019-12-24
申请人： SK hynix Inc.
发明人： Mi-Hyun Hwang , Jong-Chern Lee
IPC分类号： G11C11/00 , G11C7/00 , G11C29/02 , G11C29/00 , G11C7/10 , G11C29/24 , G11C29/44
摘要： Disclosed are a memory device and an operating method thereof, and the memory device includes a plurality of first data lines, a plurality of second data lines, a common redundant memory region coupled to at least one repair line of the second data lines, a plurality of normal memory regions coupled to the first data lines in common, and coupled in common to the remaining the second data lines excluding the repair line, and a repair circuit coupled to the first and second data lines, and suitable for replacing at least one defective memory cell in the normal memory regions with at least one redundant memory cell in the common redundant memory region by shifting some or all of the first data lines to some or all of the second data lines, based on a row address, a column address and a region address.

3. 发明授权

US11031067B2 Semiconductor memory device for securing sensing margin at cryogenic temperature 有权
公开(公告)号：US11031067B2
公开(公告)日：2021-06-08
申请号：US16683926
申请日：2019-11-14
申请人： SK hynix Inc.
发明人： Mi-Hyun Hwang
IPC分类号： G11C7/00 , G11C11/406 , G11C11/4091 , G11C7/08
摘要： A semiconductor memory device includes a controller for sequentially activating first and second control signals and activating a third control signal during an amplification period, in a pseudo cryogenic temperature, a first driver for driving a first power source line with a first voltage during an initial period of the amplification period, based on the first control signal, a second driver for driving the first power source line with a second voltage during a later period of the amplification period, based on the second control signal, a third driver for driving a second power source line with a third voltage during the amplification period, based on the third control signal, and a sense amplifier for primarily amplifying a voltage difference between a data line pair using the first and third voltages during the initial period, and secondarily amplifying the difference using the second and third voltages during the later period.

4. 发明授权

US09397642B2 Latch circuit 有权
标题翻译：锁存电路
公开(公告)号：US09397642B2
公开(公告)日：2016-07-19
申请号：US14678704
申请日：2015-04-03
申请人： SK hynix Inc.
发明人： Hae-Rang Choi , Mi-Hyun Hwang
IPC分类号： H03K3/356
CPC分类号： H03K3/356147 , H03K3/356104 , H03K3/356182
摘要： A latch circuit includes a first PMOS transistor suitable for pull-up driving a second node based on a voltage of a first node, a first NMOS transistor suitable for pull-down driving the second node based on a voltage of the first node, a second PMOS transistor suitable for pull-up driving the first node based on a voltage of the second node, a second NMOS transistor suitable for pull-down driving the first node based on a voltage of the second node, a first separation element suitable for electrically separating the first NMOS transistor from the second node when the first PMOS transistor is turned on, and a second separation element suitable for electrically separating the second NMOS transistor from the first node when the second PMOS transistor is turned on.
摘要翻译：锁存电路包括：第一PMOS晶体管，其适于基于第一节点的电压上拉驱动第二节点;第一NMOS晶体管，其适于基于第一节点的电压下拉驱动第二节点;第二NMOS晶体管， PMOS晶体管，其适于基于第二节点的电压上拉驱动第一节点;第二NMOS晶体管，适于基于第二节点的电压来下拉驱动第一节点;第一分离元件，适于电分离当第一PMOS晶体管导通时来自第二节点的第一NMOS晶体管，以及适于在第二PMOS晶体管导通时将第二NMOS晶体管与第一节点电分离的第二分离元件。

5. 发明授权

US09208850B2 Semiconductor memory device and semiconductor memory system including the same 有权
标题翻译：半导体存储器件和包括其的半导体存储器系统
公开(公告)号：US09208850B2
公开(公告)日：2015-12-08
申请号：US14470591
申请日：2014-08-27
申请人： SK hynix Inc.
发明人： Mi-Hyun Hwang
IPC分类号： G11C7/00 , G11C11/406 , G11C19/04 , G11C8/18 , G11C29/02 , G06K19/07 , G06F7/02 , G11C11/419 , G11C11/4076 , G11C11/4074
CPC分类号： G11C11/406 , G06F7/02 , G06K19/07 , G06K19/0701 , G11C8/14 , G11C8/18 , G11C11/4074 , G11C11/4076 , G11C11/408 , G11C11/4097 , G11C11/419 , G11C19/04 , G11C29/02
摘要： A semiconductor memory device includes a plurality of normal word lines and a plurality of redundancy word lines which are disposed adjacent to the normal word lines, a detection block suitable for detecting a first word line whose active history satisfies a predetermined condition and a second word line adjacent to the first word line as a target word line and a target neighboring word line, among the normal word lines and the redundancy word lines, and a control block suitable for sequentially refreshing the normal word lines and the redundancy word lines whenever a refresh command is applied, and additionally refreshing the target word line, the target neighboring word line and a normal word line adjacent to the redundancy word lines among the normal word lines.
摘要翻译：半导体存储器件包括多个正常字线和与正常字线相邻设置的多个冗余字线，适用于检测其活动历史满足预定条件的第一字线和第二字线与正常字线和冗余字线之间的作为目标字线和目标相邻字线的第一字线相邻，以及适用于每当刷新命令时依次刷新正常字线和冗余字线的控制块并且另外刷新目标字线，目标相邻字线和与正常字线中的冗余字线相邻的正常字线。

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