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1. 发明授权

US10037793B2 Semiconductor memory device and method for operating the same 有权
公开(公告)号：US10037793B2
公开(公告)日：2018-07-31
申请号：US15398884
申请日：2017-01-05
申请人： SK hynix Inc.
发明人： Sang-Ah Hyun , Jeong-Tae Hwang
IPC分类号： G11C11/406 , G11C11/408
CPC分类号： G11C11/40611 , G11C11/4082 , G11C11/4087 , G11C29/783
摘要： A semiconductor memory device includes: a high frequency signal control unit for receiving an external command address signal, removing noise and glitch from the external command address signal and outputting a first command address signal; a pulse width control unit for controlling a pulse width of the first command address signal or maintaining the pulse width of the first command address signal and outputting a second command address signal with a predetermined pulse width; a refresh operation control unit for generating a row address for a refresh operation in response to the second command address signal; and a memory cell array for performing the a refresh operation in response to the row address.

2. 发明授权

US10109362B2 Semiconductor device and method for operating the same 有权
公开(公告)号：US10109362B2
公开(公告)日：2018-10-23
申请号：US15612662
申请日：2017-06-02
申请人： SK hynix Inc.
发明人： Jeong-Tae Hwang
IPC分类号： G11C17/16 , G11C17/08 , G11C17/18
摘要： A semiconductor device includes a fuse array section suitable for performing program and read operations; a control signal generation section suitable for generating a precharge control signal and a word line control signal; a bit line control section suitable for controlling a precharge operation of a bit line in response to the precharge control signal and a source signal; and a word line control section suitable for controlling activation of a program word line and a read word line for performing the program and read operations in response to the word line control signal, wherein the control signal generation section controls the word line control signal to be activated after a predetermined time from the activation of the precharge control signal.

3. 发明授权

US09472250B1 Semiconductor device and operating method thereof 有权
标题翻译：半导体器件及其操作方法
公开(公告)号：US09472250B1
公开(公告)日：2016-10-18
申请号：US14939752
申请日：2015-11-12
申请人： SK hynix Inc.
发明人： Seung-Wook Oh , Jeong-Tae Hwang
IPC分类号： G11C7/10 , G11C7/08 , G11C29/56
CPC分类号： G11C7/109 , G11C7/22
摘要： A semiconductor device including an input unit suitable for transferring external command signals provided from an external device to an internal device and a detection unit suitable for detecting a predetermined command signal among the external command signals, and restricting the transfer of the detected command signal.
摘要翻译：一种半导体器件，包括适于将从外部设备提供的外部命令信号传送到内部设备的输入单元和适于检测外部命令信号中的预定命令信号的检测单元，并限制检测到的命令信号的传送。

4. 发明授权

US09087610B2 Semiconductor memory device, semiconductor memory module and operation methods thereof 有权
标题翻译：半导体存储器件，半导体存储器模块及其操作方法
公开(公告)号：US09087610B2
公开(公告)日：2015-07-21
申请号：US14106812
申请日：2013-12-15
申请人： SK hynix Inc.
发明人： Jeong-Tae Hwang
IPC分类号： G11C29/00 , G11C29/02 , G11C29/18
CPC分类号： G11C29/027 , G11C29/18 , G11C29/787
摘要： An operation method of a semiconductor memory device including a fuse array for storing one or more repair addresses includes latching additionally a repair address having an address value, which is not stored in the fuse array in response to an active command signal during a repair operation mode, receiving a repair entry control code from an external device in response to a first column command signal during the repair operation mode, performing a rupture operation of the repair address, which is latched, in response to a second column command signal, wherein the rupture operation is determined based on a value of a repair entry control code, and performing exit of the repair operation mode in response to a precharge command signal, which is provided after the second column command signal.
摘要翻译：包括用于存储一个或多个修复地址的熔丝阵列的半导体存储器件的操作方法包括在修复操作模式期间响应于有效命令信号另外锁存一个没有存储在熔丝阵列中的地址值的修复地址在修复操作模式期间响应于第一列命令信号从外部设备接收修复输入控制代码，响应于第二列命令信号执行锁存的修复地址的破裂操作，其中断裂基于修复进入控制代码的值确定操作，并且响应于在第二列命令信号之后提供的预充电命令信号执行修复操作模式的退出。

5. 发明授权

US08836386B1 Semiconductor device with power-up scheme 有权
标题翻译：具有上电方案的半导体器件
公开(公告)号：US08836386B1
公开(公告)日：2014-09-16
申请号：US13935989
申请日：2013-07-05
申请人： SK hynix Inc.
发明人： Jeong-Tae Hwang
IPC分类号： H03L7/00 , H03K17/22
CPC分类号： H03K17/22 , G11C5/148
摘要： A semiconductor device includes a voltage detection circuit suitable for detecting an external power supply voltage and for sequentially activating first and second power-up signals in a power-up period of the external power supply voltage, and a control circuit suitable for activating at least one first control signal for controlling an internal voltage to be generated based on the first power-up signal, and for activating at least one second control signal for controlling an operation of an internal circuit using the internal voltage when a predetermined time lapses after the first control signal is activated, based on the second power-up signal.
摘要翻译：一种半导体器件，包括适于检测外部电源电压的电压检测电路，以及用于在外部电源电压的上电期间顺序地激活第一和第二上电信号的电压检测电路，以及适用于激活至少一个第一控制信号，用于基于第一上电信号来控制要产生的内部电压，并且用于当在第一控制之后预定时间经过时，使用内部电压来激活用于控制内部电路的操作的至少一个第二控制信号信号被激活，基于第二个上电信号。

6. 发明授权

US11861000B2 Memory system 有权
公开(公告)号：US11861000B2
公开(公告)日：2024-01-02
申请号：US16842483
申请日：2020-04-07
申请人： SK hynix Inc.
发明人： Joon-Woo Choi , Jeong-Tae Hwang
IPC分类号： G06F21/00 , G06F21/55
CPC分类号： G06F21/554
摘要： A memory system includes a first memory and a second memory that share common addresses received from a memory controller, wherein the first memory includes a first scrambling circuit suitable for scrambling a common address to generate a first scrambled address designating a word line to be activated in the first memory, and the second memory includes a second scrambling circuit suitable for scrambling the common address to generate a second scrambled address designating a word line to be activated in the second memory, and the first scrambling circuit and the second scrambling circuit perform a scrambling operation in such a manner that neighboring word lines, adjacent to a word line selected by a first common address, are selected a most in one memory among the first memory and the second memory by a second common address other than the first common address.

7. 发明授权

US09934875B2 Integrated circuit and memory device performing boot-up operation 有权
公开(公告)号：US09934875B2
公开(公告)日：2018-04-03
申请号：US15170611
申请日：2016-06-01
申请人： SK hynix Inc.
发明人： Ja-Beom Koo , Jeong-Tae Hwang
IPC分类号： G11C29/00 , G11C17/16 , G11C29/44
CPC分类号： G11C29/78 , G11C17/16 , G11C2029/4402
摘要： An integrated circuit may include nonvolatile memory suitable for outputting stored data during the boot-up operation, one or more registers suitable for receiving the data output by the nonvolatile memory and storing the received data when the boot-up operation is performed, and one or more internal circuits suitable for operating using the data stored in the one or more registers. In no-update mode, although the boot-up operation is performed, a data update from the nonvolatile memory to the registers may not be performed.

8. 发明授权

US09620195B1 Memory device 有权
公开(公告)号：US09620195B1
公开(公告)日：2017-04-11
申请号：US15236267
申请日：2016-08-12
申请人： SK hynix Inc.
发明人： Sang-Ah Hyun , Jeong-Tae Hwang
IPC分类号： G11C7/00 , G11C11/406 , G11C11/408 , G11C11/4074 , G11C29/02 , G11C8/18 , G11C11/4076
CPC分类号： G11C11/40618 , G11C8/18 , G11C11/406 , G11C11/40626 , G11C11/4074 , G11C11/4076 , G11C11/4087 , G11C29/02 , G11C29/783 , G11C2211/4061
摘要： A memory device may include a plurality of memory banks; a setting circuit capable of setting at least one of an advanced refresh mode and a piled refresh mode; and a refresh control unit capable of controlling the plurality of memory banks into a plurality of groups and for activating the plurality of groups to be refreshed at different times when a refresh command is applied, wherein the refresh control unit divides the memory banks into first groups determined based on the piled refresh mode and refreshes the first groups once, while, in the advanced refresh mode, the refresh control unit divides the memory banks into second groups determined based on the piled refresh mode and additional setting information and refresh the second groups a first number of times, which is more than two and determined based on the additional setting information.

9. 发明授权

US09472308B1 Semiconductor memory device and test method thereof 有权
标题翻译：半导体存储器件及其测试方法
公开(公告)号：US09472308B1
公开(公告)日：2016-10-18
申请号：US14930174
申请日：2015-11-02
申请人： SK hynix Inc.
发明人： Jeong-Tae Hwang
IPC分类号： G11C7/00 , G11C29/00 , G11C17/16 , G11C17/18 , G11C29/04
CPC分类号： G11C29/76 , G11C17/16 , G11C17/18 , G11C29/78 , G11C2029/4402
摘要： A semiconductor memory device includes: a normal cell region having normal cells; a redundancy cell region having first redundancy cells replaced with repair target cells of the normal cells and second redundancy cells which are not replaced with the repair target cells; a fuse unit suitable for programming repair information including replacement information and one of state information and a repair address of the repair target cells; a boot-up unit suitable for outputting the repair information programmed in the fuse unit, resetting the repair information in response to a test control signal, and outputting the reset repair information; an information update unit suitable for generating the test control signal; a test control unit suitable for generating a test address during a redundancy test operation; and a test unit suitable for selectively testing the second redundancy cells in response to the test address.
摘要翻译：半导体存储器件包括：具有正常单元的正常单元区域; 具有替换为正常细胞的修复靶细胞的第一冗余细胞和不被修复靶细胞替代的第二冗余细胞的冗余细胞区域; 适用于编程包括替换信息和修复目标单元的状态信息和修复地址之一的修复信息的熔丝单元; 适于输出在熔丝单元中编程的修复信息的启动单元，响应于测试控制信号复位修复信息，并输出复位修复信息; 信息更新单元，适于生成测试控制信号; 测试控制单元，适于在冗余测试操作期间产生测试地址; 以及适于响应于测试地址选择性地测试第二冗余单元的测试单元。

10. 发明授权

US11409668B2 Memory module, operation method of memory module, memory system, and operation method of memory system 有权
公开(公告)号：US11409668B2
公开(公告)日：2022-08-09
申请号：US16728143
申请日：2019-12-27
申请人： SK hynix Inc.
发明人： Woongrae Kim , Sang-Kwon Lee , Jung-Hyun Kim , Jong-Hyun Park , Jong-Ho Son , Mi-Hyun Hwang , Jeong-Tae Hwang
IPC分类号： H04L29/06 , G06F12/14 , H04L9/08 , G06F3/06 , G06F13/16
摘要： A memory module includes: a plurality of memories, wherein each of the memories comprises: an encryption key storage circuit suitable for storing an encryption key; an address encryption circuit suitable for generating an encrypted address by encrypting an address transferred from a memory controller by using the encryption key stored in the encryption key storage circuit; and a cell array accessed by the encrypted address, wherein the encryption key storage circuits of the memories store different encryption keys.

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