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1. 发明申请

US20160226493A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE REGARDING THE DETECTION OF DEGRADATION 有权
标题翻译：关于降解检测的半导体集成电路设备
公开(公告)号：US20160226493A1
公开(公告)日：2016-08-04
申请号：US15040817
申请日：2016-02-10
申请人： SK hynix Inc.
发明人： Jeong Tae HWANG , Jin Youp CHA , Young Sik HEO
IPC分类号： H03K19/0185 , G01R31/28 , H03K17/687
CPC分类号： H03K19/018521 , G01R31/2856 , H03K17/102
摘要： A semiconductor integrated circuit device may include a target PMOS transistor, a target NMOS transistor, a first stress-applying circuit, a second stress-applying circuit, a third stress-applying circuit and a fourth stress-applying circuit. An inverter may include the target PMOS transistor and the NMOS transistor. The first stress-applying circuit may be configured to apply a first DC level to a gate of the target PMOS transistor. The second stress-applying circuit may be configured to apply a second DC level to a gate of the target NMOS transistor. The third stress-applying circuit may be configured to apply an AC voltage shape to the gate of the target NMOS transistor. The fourth stress-applying circuit may be configured to apply the AC voltage to a drain of the target NMOS transistor.
摘要翻译：半导体集成电路器件可以包括目标PMOS晶体管，目标NMOS晶体管，第一应力施加电路，第二应力施加电路，第三应力施加电路和第四应力施加电路。反相器可以包括目标PMOS晶体管和NMOS晶体管。第一应力施加电路可以被配置为将第一DC电平施加到目标PMOS晶体管的栅极。第二应力施加电路可以被配置为将第二DC电平施加到目标NMOS晶体管的栅极。第三应力施加电路可以被配置为向目标NMOS晶体管的栅极施加AC电压形状。第四应力施加电路可以被配置为将AC电压施加到目标NMOS晶体管的漏极。

2. 发明申请

US20220270672A1 SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 有权
公开(公告)号：US20220270672A1
公开(公告)日：2022-08-25
申请号：US17365462
申请日：2021-07-01
申请人： SK hynix Inc.
发明人： Woongrae KIM , Duck Hwa HONG , Jeong Tae HWANG
IPC分类号： G11C11/406 , G11C11/408
摘要： A memory system includes: a memory controller suitable for: generating a normal refresh command and a target refresh command when a number of inputs of an active command reaches a certain number, and providing the active command, the normal refresh command, the target refresh command, and an address; and a memory device including a plurality of banks and suitable for: performing a target refresh operation on one or more word lines of at least one bank in response to the target refresh command, determining a row hammer risk level per bank by counting, within a periodic interval, a number of inputs of the target refresh command per bank based on the address, and performing a hidden refresh operation corresponding to the row hammer risk level per bank in response to the normal refresh command.

3. 发明申请

US20160223609A1 SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE HAVING FUNCTION FOR DETECTING DEGRADATION OF SEMICONDUCTOR DEVICE AND METHOD OF DRIVING THE SAME 有权
标题翻译：具有用于检测半导体器件的降解的功能的半导体集成电路装置及其驱动方法
公开(公告)号：US20160223609A1
公开(公告)日：2016-08-04
申请号：US14723833
申请日：2015-05-28
申请人： SK hynix Inc.
发明人： Jeong Tae HWANG
IPC分类号： G01R31/28 , H03K19/0185
CPC分类号： G01R31/2856 , G01R31/2874 , H03K3/356104 , H03K17/102 , H03K17/145 , H03K17/18 , H03K17/6872 , H03K19/0005 , H03K19/018521
摘要： A semiconductor integrated circuit device having a function for detecting degradation of a semiconductor device and a method of driving the same are disclosed. The semiconductor integrated circuit device includes an NMOS transistor electrically coupled to a PMOS transistor and configured to constitute an inverter together with the PMOS transistor, a first stress application unit electrically coupled to the PMOS transistor and configured to apply stress to the PMOS transistor, and a second stress application unit electrically coupled to the NMOS transistor and configured to apply the stress to the NMOS transistor.
摘要翻译：公开了具有检测半导体装置的劣化的功能的半导体集成电路装置及其驱动方法。半导体集成电路器件包括电耦合到PMOS晶体管并被配置为与PMOS晶体管一起构成反相器的NMOS晶体管，电耦合到PMOS晶体管并被配置为向PMOS晶体管施加应力的第一应力施加单元，以及电耦合到所述NMOS晶体管并且被配置为将所述应力施加到所述NMOS晶体管的第二应力施加单元。

4. 发明申请

US20140298071A1 SEMICONDUCTOR DEVICES AND SEMICONDUCTOR SYSTEMS INCLUDING THE SAME 有权
标题翻译：半导体器件和半导体系统，包括它们
公开(公告)号：US20140298071A1
公开(公告)日：2014-10-02
申请号：US14041563
申请日：2013-09-30
申请人： SK hynix Inc.
发明人： Jeong Tae HWANG
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , G11C5/147 , G11C7/22 , G11C16/10
摘要： A semiconductor device including an internal command generator and a bias generator is provided. The internal command generator generates first to fourth internal command signals sequentially enabled in synchronization with pulses of an external program signal. The first internal command signal controls a read operation for reading out data stored in memory cells, and the second and third internal command signals control a program operation for programming the memory cells. The bias generator generates a read bias signal for controlling a level of an output voltage signal, which is applied to an internal circuit, in response to the first and fourth internal command signals.
摘要翻译：提供了包括内部命令发生器和偏置发生器的半导体器件。内部命令发生器产生与外部程序信号的脉冲同步地顺序使能的第一至第四内部命令信号。第一内部命令信号控制用于读出存储在存储单元中的数据的读取操作，第二和第三内部命令信号控制用于编程存储器单元的程序操作。偏置发生器响应于第一和第四内部命令信号产生用于控制施加到内部电路的输出电压信号的电平的读偏置信号。

5. 发明申请

US20220188015A1 APPARATUS AND METHOD FOR PERFORMING TARGET REFRESH OPERATION 有权
公开(公告)号：US20220188015A1
公开(公告)日：2022-06-16
申请号：US17549671
申请日：2021-12-13
申请人： SK hynix Inc.
发明人： Woongrae KIM , Kwi Dong KIM , Chul Moon JUNG , Jeong Tae HWANG
IPC分类号： G06F3/06
摘要： A semiconductor memory device comprises: first storage logic configured to store, as first addresses, ‘K’ addresses having different values among input addresses applied during the enable period of a reference signal, second storage logic configured to store, as second addresses, ‘L’ addresses corresponding to a time point at which the enable period of the reference signal is ended among the input addresses, an order controller configured to determine a first output order of each of the first addresses based on a number of times each of the first addresses is repeatedly input, and to determine a second output order for outputting mixed addresses obtained by mixing the first addresses based on the first output order and the second addresses together, and refresh operation logic configured to apply the mixed addresses according to the second output order, to a target refresh operation.

6. 发明申请

US20170084321A1 SEMICONDUCTOR DEVICE AND SEMICONDUCTOR SYSTEM 有权
公开(公告)号：US20170084321A1
公开(公告)日：2017-03-23
申请号：US14951852
申请日：2015-11-25
申请人： SK hynix Inc.
发明人： Chul Moon JUNG , Mun Phil PARK , Seok Cheol YOON , Jeong Tae HWANG
IPC分类号： G11C8/18 , G11C8/10
CPC分类号： G11C8/18 , G11C8/10 , G11C8/12
摘要： A semiconductor system may include a command processor configured to decode a command to generate an active pulse and a delayed active pulse, and a bank active signal generation circuit configured to generate a bank active signal for performing an active operation for a bank accessed by an address. The bank active signal may be disabled in synchronization with the active pulse and is enabled in synchronization with the delayed active pulse.

7. 发明申请

US20160308532A1 SEMICONDUCTOR APPARATUS 有权
公开(公告)号：US20160308532A1
公开(公告)日：2016-10-20
申请号：US14847653
申请日：2015-09-08
申请人： SK hynix Inc.
发明人： Ja Beom KOO , Jeong Tae HWANG
IPC分类号： H03K19/0175
CPC分类号： H03K19/017509 , G11C5/147 , G11C11/2297 , G11C13/0038 , G11C29/021 , G11C29/028 , G11C29/12005
摘要： A semiconductor apparatus may include an internal voltage level controller configured to output either a normal trimming code or a test voltage code as a voltage control code in response to a test mode signal, a specific operation start signal, and a specific operation end signal. The semiconductor apparatus may include an internal voltage generator configured to generate an internal voltage and control a voltage level of the internal voltage in response to the voltage control code.
摘要翻译：半导体装置可以包括内部电压电平控制器，其被配置为响应于测试模式信号，特定操作开始信号和特定操作结束信号而输出正常修整代码或测试电压代码作为电压控制代码。半导体装置可以包括被配置为产生内部电压并且响应于电压控制代码来控制内部电压的电压电平的内部电压发生器。

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