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1. 发明申请

US20150380060A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20150380060A1
公开(公告)日：2015-12-31
申请号：US14520435
申请日：2014-10-22
申请人： SK hynix Inc.
发明人： Duck Hwa HONG , Sang Il PARK
IPC分类号： G11C5/02 , G11C7/12 , G11C7/14 , G11C7/06 , G11C7/10
CPC分类号： G11C7/1048 , G11C7/12 , G11C7/14 , G11C7/18 , G11C11/4097 , G11C11/4099 , G11C2207/005
摘要： A semiconductor device includes a first cell array region disposed adjacent to a second cell array region; a dummy cell region disposed between the first cell array region and the second cell array region, and configured to distinguish the first cell array region from the second cell array region by dummy bit lines; first group segment input/output lines disposed to correspond to the first cell array region when viewed in terms of the dummy bit lines; and second group segment input/output lines disposed to correspond to the second cell to array region when viewed in terms of the dummy bit lines.
摘要翻译：半导体器件包括邻近第二单元阵列区域设置的第一单元阵列区域; 设置在第一单元阵列区域和第二单元阵列区域之间的虚拟单元区域，并且被配置为通过虚拟位线将第一单元阵列区域与第二单元阵列区域区分开; 第一组段输入/输出线，其设置为当根据虚拟位线观看时对应于第一单元阵列区域; 以及第二组段输入/输出线，其被设置为当根据虚拟位线观看时对应于第二单元到阵列区域。

2. 发明申请

US20220270672A1 SEMICONDUCTOR MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME 有权
公开(公告)号：US20220270672A1
公开(公告)日：2022-08-25
申请号：US17365462
申请日：2021-07-01
申请人： SK hynix Inc.
发明人： Woongrae KIM , Duck Hwa HONG , Jeong Tae HWANG
IPC分类号： G11C11/406 , G11C11/408
摘要： A memory system includes: a memory controller suitable for: generating a normal refresh command and a target refresh command when a number of inputs of an active command reaches a certain number, and providing the active command, the normal refresh command, the target refresh command, and an address; and a memory device including a plurality of banks and suitable for: performing a target refresh operation on one or more word lines of at least one bank in response to the target refresh command, determining a row hammer risk level per bank by counting, within a periodic interval, a number of inputs of the target refresh command per bank based on the address, and performing a hidden refresh operation corresponding to the row hammer risk level per bank in response to the normal refresh command.

3. 发明申请

US20220189534A1 ELECTRONIC DEVICE FOR PERFORMING SMART REFRESH OPERATION 有权
公开(公告)号：US20220189534A1
公开(公告)日：2022-06-16
申请号：US17521331
申请日：2021-11-08
申请人： SK hynix Inc.
发明人： Jeong Jin HWANG , Sung Nyou YU , Duck Hwa HONG , Sang Ah HYUN , Soo Hwan KIM
IPC分类号： G11C11/406 , G11C11/408
摘要： An electronic device includes a target address generation circuit configured to generate a counting signal by counting the number of times each logic level combination of an address is input by performing an internal read operation and an internal write operation during an active operation, configured to store the counting signal as the storage counting signal when the counting signal is counted more than a storage counting signal that is stored therein, and configured to store the address, corresponding to the counting signal, as a target address; and a refresh control circuit configured to control a smart refresh operation on the target address.

4. 发明申请

US20220230667A1 WORD LINE CONTROL CIRCUIT AND SEMICONDCUTOR APPARATUS INCLUDING THE SAME 有权
公开(公告)号：US20220230667A1
公开(公告)日：2022-07-21
申请号：US17336591
申请日：2021-06-02
申请人： SK hynix Inc.
发明人： Chul Moon JUNG , Duck Hwa HONG
IPC分类号： G11C8/08
摘要： Disclosed is a word line control circuit including a first driving unit configured to apply a first power supply voltage or a second power supply voltage to a word line according to a first word line control signal; a second driving unit configured to drop a voltage level of the word line to a first target level during a first period by using a third power supply voltage according to output of the first driving unit and a second word line control signal; and a third driving unit configured to maintain the voltage level of the word line at substantially the first target level during a second period according to a third word line control signal, and to drop the voltage level of the word line to a second target level during a third period by using a fourth power supply voltage.

5. 发明申请

US20160086649A1 SMART REFRESH DEVICE 有权
标题翻译：智能刷新设备
公开(公告)号：US20160086649A1
公开(公告)日：2016-03-24
申请号：US14574900
申请日：2014-12-18
申请人： SK hynix Inc.
发明人： Duck Hwa HONG , Sang Il PARK
IPC分类号： G11C11/406 , G11C17/16 , G11C11/408
CPC分类号： G11C11/406 , G11C11/408 , G11C29/783
摘要： A smart refresh device includes an address control block configured to determine whether a specific row address is a row hammer address, and invert a first row hammer address and perform an addition/subtraction of an address; a repair control block configured to determine whether the row hammer address is a repaired address and output a stored repair address as a second repair control signal; a repair address storage block configured to store an output address of the address control block and output a stored address as a latch address; a fuse block configured to output a repair signal representing information on a repair address to the repair control block, and output a decoding signal according to the latch address; and an operator configured to add and subtract the decoding signal according to an addition signal and a subtraction signal.
摘要翻译：智能刷新装置包括地址控制块，其被配置为确定特定行地址是否是行锤地址，并且反转第一行锤地址并执行地址的加/减; 修复控制块，被配置为确定行锤地址是否是修复地址，并将存储的修复地址输出作为第二修复控制信号; 修复地址存储块，被配置为存储地址控制块的输出地址，并将存储的地址作为锁存地址输出; 熔断器块，被配置为向维修控制块输出表示修复地址信息的修复信号，并根据锁存地址输出解码信号; 以及操作器，被配置为根据加法信号和减法信号来对所述解码信号进行加减。

6. 发明申请

US20150380070A1 LATCH CIRCUIT AND INPUT/OUTPUT DEVICE INCLUDING THE SAME 审中-公开
标题翻译：锁定电路和输入/输出装置，包括它们
公开(公告)号：US20150380070A1
公开(公告)日：2015-12-31
申请号：US14517277
申请日：2014-10-17
申请人： SK hynix Inc.
发明人： Duck Hwa HONG , Sang Il PARK
IPC分类号： G11C8/06 , G11C8/18
CPC分类号： G11C8/06 , G11C8/18
摘要： A latch circuit includes an input block configured to latch first group input addresses and second group input addresses and output first group internal addresses, according to states of select signals; and a latch block configured to latch the first group internal addresses corresponding to a first active command when a first active control signal is activated, and output the first group internal addresses and second group internal addresses as row addresses corresponding to a second active command when a second active control signal is activated.
摘要翻译：锁存电路包括：输入块，被配置为根据选择信号的状态来锁存第一组输入地址和第二组输入地址并输出第一组内部地址; 以及锁存块，被配置为当第一主动控制信号被激活时，锁存与第一主动命令对应的第一组内部地址，并且当第一主动控制信号被激活时，将第一组内部地址和第二组内部地址作为行地址输出第二主动控制信号被激活。

7. 发明申请

US20150043297A1 ACTIVE CONTROL DEVICE AND SEMICONDUCTOR DEVICE INCLUDING THE SAME 有权
标题翻译：主动控制装置和包括其的半导体装置
公开(公告)号：US20150043297A1
公开(公告)日：2015-02-12
申请号：US14074933
申请日：2013-11-08
申请人： SK hynix Inc.
发明人： Duck Hwa HONG
IPC分类号： G11C8/10 , G11C8/16
CPC分类号： G11C8/10 , G11C8/06 , G11C8/18
摘要： An active control device and a semiconductor device including the same are disclosed, which can control an active command in response to a pin change of a command address. The active control device includes: a bank decoding unit configured to decode a bank address to output a bank selection signal; an active controller configured to output a first active control signal, a second active control signal, and an active delay signal to control an active operation of a bank in response to the bank selection signal, a first active signal, and a second active signal; an address latch unit configured to latch a row address to output an address delay signal; and an address output unit configured to output an address corresponding to the address delay signal.
摘要翻译：公开了一种主动控制装置和包括该控制装置的半导体装置，其可以响应于命令地址的引脚改变而控制有效命令。主动控制装置包括：组解码单元，被配置为解码存储体地址以输出存储体选择信号; 主动控制器，被配置为输出第一有效控制信号，第二有效控制信号和有效延迟信号，以响应于存储体选择信号，第一有效信号和第二有效信号来控制存储体的有效操作; 地址锁存单元，被配置为锁存行地址以输出地址延迟信号; 以及地址输出单元，被配置为输出与地址延迟信号相对应的地址。

8. 发明公开

US20240312503A1 MEMORY DEVICE PERFORMING PRECHARGE OPERATION, AND OPERATING METHOD THEREOF 审中-公开
公开(公告)号：US20240312503A1
公开(公告)日：2024-09-19
申请号：US18358026
申请日：2023-07-25
申请人： SK hynix Inc.
发明人： Sang Hyun KU , Do Hong KIM , Duck Hwa HONG , Min Ho SEOK , So Yoon KIM
IPC分类号： G11C8/08
CPC分类号： G11C8/08
摘要： A memory device includes a plurality of word lines; and a row control circuit configured to: drive, in response to a precharge command, a selected word line of the word lines such that a voltage level of the selected word line decreases from a first voltage level to a second voltage level during a first section, stays at the second voltage level during a second section and decreases from the second voltage level to a third voltage level during a third section, and keep the second section at a preset time amount, or change the second section to a time amount defined by an input of an active command according to a mode control signal.

9. 发明公开

US20240112718A1 ELECTRONIC DEVICE FOR PERFORMING SMART REFRESH OPERATION 审中-公开
公开(公告)号：US20240112718A1
公开(公告)日：2024-04-04
申请号：US18535647
申请日：2023-12-11
申请人： SK hynix Inc.
发明人： Jeong Jin HWANG , Sung Nyou YU , Duck Hwa HONG , Sang Ah HYUN , Soo Hwan KIM
IPC分类号： G11C11/406 , G11C11/408
CPC分类号： G11C11/40615 , G11C11/40603 , G11C11/4085 , G11C11/406 , G11C11/40618
摘要： An electronic device includes a target address generation circuit configured to generate a counting signal by counting the number of times each logic level combination of an address is input by performing an internal read operation and an internal write operation during an active operation, configured to store the counting signal as the storage counting signal when the counting signal is counted more than a storage counting signal that is stored therein, and configured to store the address, corresponding to the counting signal, as a target address; and a refresh control circuit configured to control a smart refresh operation on the target address.

10. 发明申请

US20220406367A1 ELECTRONIC DEVICE FOR ADJUSTING REFRESH OPERATION PERIOD 有权
公开(公告)号：US20220406367A1
公开(公告)日：2022-12-22
申请号：US17480832
申请日：2021-09-21
申请人： SK hynix Inc.
发明人： Hyun Seung KIM , Ho Uk SONG , Tae Kyun SHIN , Min Jun CHOI , Duck Hwa HONG
IPC分类号： G11C11/406 , G11C11/4076
摘要： An electronic device includes an intelligent refresh control circuit generating an intelligent refresh pulse with a pulse that has a generation period that is adjusted based on the number of generations of an auto refresh signal during an intelligent refresh operation, and an internal refresh signal generation circuit outputting one of a self-refresh pulse including a pulse that is periodically generated by an enable signal during a self-refresh operation and the intelligent refresh pulse as an internal refresh signal.

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