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1. 发明申请

US20110110150A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20110110150A1
公开(公告)日：2011-05-12
申请号：US13008893
申请日：2011-01-18
申请人： SATORU HANZAWA , Hitoshi Kume , Motoyasu Terao , Tomonori Sekiguchi , Makoto Sean
发明人： SATORU HANZAWA , Hitoshi Kume , Motoyasu Terao , Tomonori Sekiguchi , Makoto Sean
IPC分类号： G11C11/00
CPC分类号： G01R31/31715 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , G11C2213/71 , G11C2213/72 , Y10T29/49169
摘要： A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.
摘要翻译：实现了高度可靠的大容量相变存储器模块。根据本发明的半导体器件包括具有堆叠使用硫属化物材料的存储层和由二极管构成的存储单元的结构的存储器阵列，并且根据层来改变初始化条件和重写条件其中所选择的存储器单元被定位。根据操作选择电流镜电路，并且同时根据电压选择中的复位电流的控制机构的操作来改变初始化条件和重写条件（这里为复位条件）电路和电流镜电路。

2. 发明申请

US20110292722A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20110292722A1
公开(公告)日：2011-12-01
申请号：US13207611
申请日：2011-08-11
申请人： SATORU HANZAWA , Hitoshi Kume , Motoyasu Terao , Tomonori Sekiguchi , Makoto Saen
发明人： SATORU HANZAWA , Hitoshi Kume , Motoyasu Terao , Tomonori Sekiguchi , Makoto Saen
IPC分类号： G11C11/00
CPC分类号： G01R31/31715 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , G11C2213/71 , G11C2213/72 , Y10T29/49169
摘要： A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogcnidc material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.
摘要翻译：实现了高度可靠的大容量相变存储器模块。根据本发明的半导体器件包括存储阵列，该存储器阵列具有堆叠使用了电阻元件的存储层和由二极管构成的存储单元的结构，并且根据层来改变初始化条件和重写条件其中所选择的存储器单元被定位。根据操作选择电流镜电路，并且同时根据电压选择中的复位电流的控制机构的操作来改变初始化条件和重写条件（这里为复位条件）电路和电流镜电路。

3. 发明申请

US20120135548A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20120135548A1
公开(公告)日：2012-05-31
申请号：US13366329
申请日：2012-02-05
申请人： SATORU HANZAWA , Hitoshi Kume , Motoyasu Terao , Tomonori Sekiguchi , Makoto Saen
发明人： SATORU HANZAWA , Hitoshi Kume , Motoyasu Terao , Tomonori Sekiguchi , Makoto Saen
IPC分类号： H01L21/66
CPC分类号： G01R31/31715 , G11C13/0004 , G11C13/0069 , G11C2013/0083 , G11C2213/71 , G11C2213/72 , Y10T29/49169
摘要： A highly reliable large capacity phase change memory module is realized. A semiconductor device according to the present invention includes a memory array having a structure in which a storage layer using a chalcogenide material and a memory cell constituted of a diode are stacked, and an initialization condition and a rewriting condition are changed in accordance with the layer where a selected memory cell is located. A current mirror circuit is selected in accordance with an operation, and at the same time, the initialization condition and the rewriting condition (here, reset condition) are changed in accordance with the operation by a control mechanism of the reset current in a voltage selection circuit and a current mirror circuit.
摘要翻译：实现了高度可靠的大容量相变存储器模块。根据本发明的半导体器件包括具有堆叠使用硫属化物材料的存储层和由二极管构成的存储单元的结构的存储器阵列，并且根据层来改变初始化条件和重写条件其中所选择的存储器单元被定位。根据操作选择电流镜电路，并且同时根据电压选择中的复位电流的控制机构的操作来改变初始化条件和重写条件（这里为复位条件）电路和电流镜电路。

4. 发明申请

US20090116309A1 SEMICONDUCTOR DEVICE 审中-公开
标题翻译：半导体器件
公开(公告)号：US20090116309A1
公开(公告)日：2009-05-07
申请号：US12348306
申请日：2009-01-04
申请人： SATORU HANZAWA , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Kazuhiko Kajigaya
发明人： SATORU HANZAWA , Tomonori Sekiguchi , Riichiro Takemura , Satoru Akiyama , Kazuhiko Kajigaya
IPC分类号： G11C7/00
CPC分类号： G11C7/1027 , G11C7/1012 , G11C7/1048 , G11C7/1051 , G11C7/1066 , G11C7/1069 , G11C7/1072 , G11C7/1078 , G11C7/1096 , G11C7/12 , G11C7/22 , G11C11/4076 , G11C11/4091 , G11C11/4093 , G11C11/4094 , G11C11/4096 , G11C29/028 , G11C2207/002
摘要： A column circuit that amplifies signals read from a sense amplifier array SAA to local input/output lines LIO in sub-amplifiers SAMP to transfer the amplified signals to main input/output lines MIO is provided. A current control circuit IC that can set one of two kinds of currents according to read enable signals RD1, RD2 is provided in each sub-amplifier SAMP. The read enable signals RD1, RD2 are generated at timings corresponding to the number of cycles in burst read operation under control of the timing controller. Current in the current control circuit IC is set to be large by the RD1 in burst read operation cycle just after activation of a memory bank, while current in the current control circuit IC is set to be small by the RD2 in the next and subsequent burst read cycles. Accordingly, expansion of an operation margin or reduction of power consumption can be realized in a semiconductor device including a semiconductor memory such as a DRAM.
摘要翻译：提供了一种列电路，其将从读出放大器阵列SAA读取的信号放大到子放大器SAMP中的本地输入/输出线LIO，以将放大的信号传送到主输入/输出线MIO。在每个子放大器SAMP中提供可以根据读使能信号RD1，RD2设置两种电流之一的电流控制电路IC。在定时控制器的控制下，在脉冲串读取操作中的周期数对应的定时产生读使能信号RD1，RD2。电流控制电路IC中的电流在刚刚激活存储体之后的脉冲串读取操作周期中的RD1被设置为较大，而当前控制电路IC中的电流在下一个和随后的脉冲串中被RD2设置得较小读周期。因此，可以在包括诸如DRAM的半导体存储器的半导体器件中实现操作余量的扩大或功率消耗的降低。

5. 发明申请

US20090150604A1 Semiconductor Device 有权
标题翻译：半导体器件
公开(公告)号：US20090150604A1
公开(公告)日：2009-06-11
申请号：US12367108
申请日：2009-02-06
申请人： SATORU HANZAWA , Takeshi Sakata , Kazuhiko Kajigaya
发明人： SATORU HANZAWA , Takeshi Sakata , Kazuhiko Kajigaya
IPC分类号： G06F12/00
CPC分类号： G11C15/04 , G11C15/043
摘要： The range-specified IP addresses are effectively stored to reduce the number of necessary entries thereby the memory capacity of TCAM is improved. The representative means of the present invention is that: the storage information (entry) and the input information (comparison information or search key) are the common block code such that any bit must be the logical value ‘1’; Match-lines are hierarchically structured and memory cells are arranged at the intersecting points of a plurality of sub-match lines and a plurality of search lines; Further the sub-match lines are connected to main-match lines through the sub-match detectors, respectively and main-match detectors are arranged on the main-match lines.
摘要翻译：有效存储范围指定的IP地址，以减少必要条目的数量，从而提高TCAM的存储容量。本发明的代表性手段是：存储信息（条目）和输入信息（比较信息或搜索关键字）是公共块码，使得任何位必须是逻辑值“1”; 匹配线是分层结构的，并且存储器单元被布置在多个子匹配线和多条搜索线的交叉点处; 此外，子匹配线分别通过子匹配检测器连接到主匹配线，并且主匹配检测器被布置在主匹配线上。

6. 发明申请

US20120287697A1 SEMICONDUCTOR STORAGE DEVICE 有权
标题翻译：半导体存储设备
公开(公告)号：US20120287697A1
公开(公告)日：2012-11-15
申请号：US13466866
申请日：2012-05-08
申请人： SATORU HANZAWA , Hiroyuki Minemura
发明人： SATORU HANZAWA , Hiroyuki Minemura
IPC分类号： G11C11/00
CPC分类号： H01L27/2454 , G11C13/0004 , G11C13/0061 , G11C13/0069 , G11C2213/18 , G11C2213/71 , G11C2213/75 , H01L27/2481 , H01L45/06 , H01L45/124 , H01L45/144
摘要： A semiconductor storage device crystallizes variable resistive element material layers arranged on side surfaces of multiple semiconductor layers in a stacked structure concurrently by applying a first current to any one of semiconductor layers in the stacked structure, and thereafter applies a second current to semiconductor layers other than a semiconductor layer to which the first current was applied.
摘要翻译：半导体存储装置通过向堆叠结构中的任一个半导体层施加第一电流，同时以层叠结构使配置在多个半导体层的侧面上的可变电阻元件材料层结晶化，然后向第二电流施加除了施加了第一电流的半导体层。

7. 发明申请

US20120268981A1 SEMICONDUCTOR DEVICE AND ITS MANUFACTURING METHOD 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120268981A1
公开(公告)日：2012-10-25
申请号：US13456195
申请日：2012-04-25
申请人： SATORU HANZAWA , Fumihiko Nitta , Nozomu Matsuzaki , Toshihiro Tanaka
发明人： SATORU HANZAWA , Fumihiko Nitta , Nozomu Matsuzaki , Toshihiro Tanaka
IPC分类号： G11C11/21
CPC分类号： G11C5/06 , G11C13/0004 , G11C13/003 , G11C13/0069 , G11C2213/74 , G11C2213/79 , H01L27/2436 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/141 , H01L45/144
摘要： In a semiconductor device including a memory cell array formed of memory cells using a storage element by a variable resistor and a select transistor, a buffer cell is arranged between a sense amplifier and the memory cell array and between a word driver and the memory cell array. The resistive storage element in the memory cell is connected to a bit-line via a contact formed above the resistive storage element. Meanwhile, in the buffer cell, the contact is not formed above the resistive storage element, and a state of being covered with an insulator is kept upon processing the contact in the memory cell. By such a processing method, exposure and sublimation of a chalcogenide film used in the resistive storage element can be avoided.
摘要翻译：在包括由可变电阻器使用存储元件的存储器单元和选择晶体管形成的存储单元阵列的半导体器件中，缓冲单元布置在读出放大器和存储单元阵列之间以及字驱动器和存储单元阵列之间。存储单元中的电阻存储元件通过形成在电阻存储元件上方的触点连接到位线。同时，在缓冲单元中，电阻性存储元件之上不形成接触，并且在处理存储单元中的接触时保持被绝缘体覆盖的状态。通过这种处理方法，可以避免在电阻存储元件中使用的硫族化物膜的曝光和升华。

8. 发明申请

US20110103142A1 SEMICONDUCTOR DEVICE 失效
标题翻译：半导体器件
公开(公告)号：US20110103142A1
公开(公告)日：2011-05-05
申请号：US12986178
申请日：2011-01-07
申请人： SATORU HANZAWA , Yoshikazu Iida
发明人： SATORU HANZAWA , Yoshikazu Iida
IPC分类号： G11C11/00
CPC分类号： G11C13/0069 , G11C13/0004 , G11C13/004 , G11C2213/79
摘要： In a memory array MCA which includes memory cells MC each having a variable-resistance-based memory device RQ and a select transistor MQ, an object is to receive a fixed quantity of storage data for a short time, and to realize writing operation to the memory cell, with suppressed peak current. In order to achieve the object, the data bus occupation time in rewriting operation is shortened by using plural sense amplifiers and storing storage data temporarily, and plural programming circuits are provided and activated using the control signals with different phases. By the above, the phase change memory system with low current consumption can be realized, without causing degradation of the utilization ratio of the data bus.
摘要翻译：在包括具有可变电阻的存储器件RQ和选择晶体管MQ的存储单元MC的存储器阵列MCA中，目的是在短时间内接收固定量的存储数据，并且实现对存储单元，具有抑制的峰值电流。为了实现该目的，通过使用多个读出放大器和临时存储存储数据来缩短重写操作中的数据总线占用时间，并且使用具有不同相位的控制信号来提供和激活多个编程电路。通过上述，可以实现具有低电流消耗的相变存储器系统，而不会降低数据总线的利用率。

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