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1. 发明授权

US09530790B1 Three-dimensional memory device containing CMOS devices over memory stack structures 有权
标题翻译：在存储器堆叠结构中包含CMOS器件的三维存储器件
公开(公告)号：US09530790B1
公开(公告)日：2016-12-27
申请号：US14757572
申请日：2015-12-24
申请人： SANDISK TECHNOLOGIES INC.
发明人： Zhenyu Lu , Andrew Lin , Johann Alsmeier , Peter Rabkin , Wei Zhao , Wenguang Stephen Shi , Henry Chien , Jian Chen
IPC分类号： H01L29/78 , H01L27/115 , H01L23/528 , H01L29/08 , H01L29/417 , G11C16/24 , G11C16/08 , H01L23/522 , H01L29/04 , H01L29/786 , H01L29/788 , H01L21/768 , H01L21/02 , H01L21/28
CPC分类号： H01L27/11582 , H01L27/0688 , H01L27/11565 , H01L27/1157 , H01L27/11573 , H01L27/11575 , H01L29/78672 , H01L29/7883
摘要： Peripheral devices for a three-dimensional memory device can be formed over an array of memory stack structures to increase areal efficiency of a semiconductor chip. First contact via structures and first metal lines are formed over an array of memory stack structures and an alternating stack of insulating layers and electrically conductive layers. A semiconductor material layer including a single crystalline semiconductor material or a polycrystalline semiconductor material is formed over first metal lines. After formation of semiconductor devices on or in the semiconductor material layer, metal interconnect structures including second metal lines and additional conductive via structures are formed to electrically connect nodes of the semiconductor devices to respective first metal lines and to memory devices underneath.
摘要翻译：用于三维存储器件的外围器件可以形成在存储器堆叠结构的阵列上，以增加半导体芯片的面积效率。通过结构和第一金属线的第一接触形成在存储器堆叠结构的阵列和绝缘层和导电层的交替堆叠之上。在第一金属线上形成包括单晶半导体材料或多晶半导体材料的半导体材料层。在半导体材料层上或半导体材料层中形成半导体器件之后，形成包括第二金属线和附加导电通路结构的金属互连结构，以将半导体器件的节点电连接到相应的第一金属线和下面的存储器件。

2. 发明授权

US09530785B1 Three-dimensional memory devices having a single layer channel and methods of making thereof 有权
标题翻译：具有单层通道的三维存储器件及其制造方法
公开(公告)号：US09530785B1
公开(公告)日：2016-12-27
申请号：US14804564
申请日：2015-07-21
申请人： SanDisk Technologies, Inc.
发明人： Sateesh Koka , Zhenyu Lu , Wei Zhao , Ching-Huang Lu , Henry Chien , Yingda Dong , Raghuveer S. Makala , Somesh Peri , Rahul Sharangpani , George Matamis , Yuichi Ikezono , Hiroyuki Ogawa
IPC分类号： H01L29/76 , H01L27/115
CPC分类号： H01L27/1157 , H01L21/28282 , H01L27/0688 , H01L27/11524 , H01L27/11556 , H01L27/11582
摘要： A memory stack structure for a three-dimensional device includes an alternating stack of insulator layers and spacer material layers. A memory opening is formed through the alternating stack. A memory material layer, a tunneling dielectric layer, and a silicon oxide liner are formed in the memory opening. A sacrificial liner is subsequently formed over the tunneling dielectric layer. The layer stack is anisotropically etched to physically expose a semiconductor surface of the substrate underneath the memory opening. The sacrificial liner may be removed prior to, or after, the anisotropic etch. The silicon oxide liner is removed after the anisotropic etch. A semiconductor channel layer can be deposited directly on the tunneling dielectric layer as a single material layer without any interface therein.
摘要翻译：用于三维器件的存储器堆叠结构包括交替堆叠的绝缘体层和间隔物材料层。通过交替堆叠形成存储器开口。在存储器开口中形成记忆材料层，隧道介电层和氧化硅衬垫。随后在隧道电介质层上形成牺牲衬垫。层叠堆叠被各向异性蚀刻以物理地暴露存储器开口下方的衬底的半导体表面。可以在各向异性蚀刻之前或之后去除牺牲衬垫。在各向异性蚀刻之后去除氧化硅衬垫。可以将半导体沟道层直接沉积在隧道电介质层上作为单个材料层而没有任何界面。

3. 发明授权

US09378832B1 Method to recover cycling damage and improve long term data retention 有权
标题翻译：恢复循环损伤并改善长期数据保留的方法
公开(公告)号：US09378832B1
公开(公告)日：2016-06-28
申请号：US14565729
申请日：2014-12-10
申请人： SanDisk Technologies Inc.
发明人： Ching-Huang Lu , Zhengyi Zhang , Wei Zhao , Yingda Dong , Jian Chen
IPC分类号： G11C16/16 , G11C16/34 , G11C16/04 , G11C16/32
CPC分类号： G11C16/16 , G11C16/0466 , G11C16/0483 , G11C16/32 , G11C16/3431 , G11C16/3459 , G11C16/349 , G11C16/3495
摘要： Techniques for reversing damage caused by program-erase cycles in charge-trapping memory to improve long term data retention. A recovery process improves the data retention of a block of memory cells by programming the memory cells to a relatively high threshold voltage and enforcing a time period of several minutes or hours in which the memory cells are inactive and remain at the relatively high Vth levels. Damage such as traps in the memory cells is essentially healed or annealed out during this inactive period. All of the memory cells can be healed at the same time and by relatively equal amounts. At the conclusion of the recovery process, the block is returned to a pool of available blocks. In one approach, an amount of recovery is measured and the period of inactivity is continued for an amount of time which is based on the amount of recovery.
摘要翻译：用于在电荷捕获存储器中逆转由编程擦除周期引起的损坏以改善长期数据保持的技术。恢复过程通过将存储器单元编程到相对较高的阈值电压并且执行存储器单元不活动并保持在相对高的Vth电平的几分钟或数小时的时间段来改善存储器单元块的数据保持。在这个不活跃的时期，诸如记忆单元中的陷阱的损伤基本上被愈合或退火。所有的记忆细胞可以同时和相对相等的量治愈。在恢复过程结束时，块将返回到可用块池。在一种方法中，测量恢复量，并且基于回收量，持续不活动的时间持续一段时间。

4. 发明授权

US09305849B1 Method of making a three dimensional NAND device 有权
标题翻译：制造三维NAND器件的方法
公开(公告)号：US09305849B1
公开(公告)日：2016-04-05
申请号：US14539372
申请日：2014-11-12
申请人： SanDisk Technologies, Inc.
发明人： Masanori Tsutsumi , Shigehiro Fujino , Sateesh Koka , Senaka Kanakamedala , Yanli Zhang , Raghuveer S. Makala , Rahul Sharangpani , George Matamis , Wei Zhao
IPC分类号： H01L21/76 , H01L21/28 , H01L21/8239 , H01L21/283 , H01L27/115 , H01L21/822
CPC分类号： H01L21/8239 , H01L21/28282 , H01L21/8221 , H01L27/11551 , H01L27/1157 , H01L27/11575 , H01L27/11582
摘要： A monolithic three dimensional NAND string includes a semiconductor channel, an end part of the semiconductor channel extending substantially perpendicular to a major surface of a substrate, a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate, a charge storage material layer located between the plurality of control gate electrodes and the semiconductor channel, a tunnel dielectric located between the charge storage material layer and the semiconductor channel, and a blocking dielectric containing a plurality of clam-shaped portions each having two horizontal portions connected by a vertical portion. Each of the plurality of control gate electrodes are located at least partially in an opening in the clam-shaped blocking dielectric, and a plurality of discrete cover oxide segments embedded in part of a thickness of the charge storage material layer and located between the blocking dielectric and the charge storage material layer.
摘要翻译：单片三维NAND串包括半导体通道，半导体通道的基本垂直于基板的主表面延伸的端部，基本上平行于基板的主表面延伸的多个控制栅电极，电荷存储材料位于多个控制栅电极和半导体沟道之间的层，位于电荷存储材料层和半导体沟道之间的隧道电介质，以及包含多个蛤状部分的阻挡电介质，每个具有两个水平部分的垂直部分一部分。多个控制栅电极中的每一个至少部分地位于蛤状阻挡电介质中的开口中，以及多个分立的覆盖氧化物段，其嵌入部分电荷存储材料层的厚度并位于阻挡电介质和电荷存储材料层。

5. 发明申请

US20160172044A1 Method To Recover Cycling Damage And Improve Long Term Data Retention 有权
标题翻译：恢复循环伤害并改善长期数据保留的方法
公开(公告)号：US20160172044A1
公开(公告)日：2016-06-16
申请号：US14565729
申请日：2014-12-10
申请人： SanDisk Technologies Inc.
发明人： Ching-Huang Lu , Zhengyi Zhang , Wei Zhao , Yingda Dong , Jian Chen
IPC分类号： G11C16/16 , G11C16/04 , G11C16/32 , G11C16/34
CPC分类号： G11C16/16 , G11C16/0466 , G11C16/0483 , G11C16/32 , G11C16/3431 , G11C16/3459 , G11C16/349 , G11C16/3495
摘要： Techniques for reversing damage caused by program-erase cycles in charge-trapping memory to improve long term data retention. A recovery process improves the data retention of a block of memory cells by programming the memory cells to a relatively high threshold voltage and enforcing a time period of several minutes or hours in which the memory cells are inactive and remain at the relatively high Vth levels. Damage such as traps in the memory cells is essentially healed or annealed out during this inactive period. All of the memory cells can be healed at the same time and by relatively equal amounts. At the conclusion of the recovery process, the block is returned to a pool of available blocks. In one approach, an amount of recovery is measured and the period of inactivity is continued for an amount of time which is based on the amount of recovery.
摘要翻译：用于在电荷捕获存储器中逆转由编程擦除周期引起的损坏以改善长期数据保持的技术。恢复过程通过将存储器单元编程到相对较高的阈值电压并且执行存储器单元不活动并保持在相对高的Vth电平的几分钟或数小时的时间段来改善存储器单元块的数据保持。在这个不活跃的时期，诸如记忆单元中的陷阱的损伤基本上被愈合或退火。所有的记忆细胞可以同时和相对相等的量治愈。在恢复过程结束时，块将返回到可用块池。在一种方法中，测量恢复量，并且基于回收量，持续不活动的时间持续一段时间。

6. 发明授权

US09312010B1 Programming of drain side word line to reduce program disturb and charge loss 有权
标题翻译：编程漏极字线，减少程序干扰和电荷损失
公开(公告)号：US09312010B1
公开(公告)日：2016-04-12
申请号：US14508164
申请日：2014-10-07
申请人： SanDisk Technologies Inc.
发明人： Jiahui Yuan , Yingda Dong , Ching-Huang Lu , Wei Zhao
IPC分类号： G11C16/04 , G11C16/10 , G11C16/34
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0466 , G11C16/0483 , G11C16/3427 , G11C16/3459 , G11C2211/5621 , G11C2211/5648
摘要： Techniques are provided for programming the memory cells of a drain-side edge word line of a set of word lines before programming memory cells of any other word line of the set. Pass voltages applied to the other word lines act as stress pulses which redistribute holes in the charge-trapping material of the memory cells of the other word lines to reduce short-term charge loss and downshifting of the threshold voltage. Additionally, one or more initial program voltages used for the drain-side edge word line are relatively low and also act as stress pulses. The memory cells of the drain-side edge word line are programmed to a narrower Vth window than the memory cells of the other word lines. This compensates for a higher level of program disturb of erased state memory cells of the drain-side edge word line due to reduced channel boosting.
摘要翻译：提供了在编程集合的任何其他字线的存储器单元之前对一组字线集合的漏极边缘字线的存储器单元进行编程的技术。施加到其它字线的通过电压作为应力脉冲，其重新分配其它字线的存储单元的电荷捕获材料中的空穴，以减少阈值电压的短期电荷损耗和降档。此外，用于漏极侧边缘字线的一个或多个初始编程电压相对较低并且还用作应力脉冲。漏极侧边缘字线的存储单元被编程到比其它字线的存储单元窄的Vth窗口。这由于减少的信道增强而补偿了漏极侧边缘字线的擦除状态存储单元的编程干扰的较高水平。

7. 发明授权

US09515079B2 Three dimensional memory device with blocking dielectric having enhanced protection against fluorine attack 有权
标题翻译：具有阻塞电介质的三维存储器件具有增强的防止氟侵蚀的保护
公开(公告)号：US09515079B2
公开(公告)日：2016-12-06
申请号：US14751922
申请日：2015-06-26
申请人： SanDisk Technologies, Inc.
发明人： Sateesh Koka , Raghuveer S. Makala , Somesh Peri , Rahul Sharangpani , Yao-Sheng Lee , George Matamis , Wei Zhao
IPC分类号： H01L27/115 , H01L21/223 , H01L21/02 , H01L29/788 , H01L29/792
CPC分类号： H01L27/11524 , H01L21/02164 , H01L21/02178 , H01L21/02332 , H01L21/02337 , H01L21/0234 , H01L21/02356 , H01L21/2236 , H01L27/11556 , H01L27/11565 , H01L27/1157 , H01L27/11582 , H01L29/7883 , H01L29/792
摘要： Blocking dielectric structures and/or thicker barrier metal films for preventing or reducing fluorine diffusion are provided. A blocking dielectric layer can be formed as an outer layer of a memory film in a memory stack structure extending through electrically insulating layers and sacrificial material layers. After formation of backside recesses by removal of the sacrificial material layers, dopants can be introduced into physically exposed portions of the blocking dielectric layer, for example, by plasma treatment or thermal treatment, to form silicon oxynitride regions which can reduce or prevent fluorine diffusion. Alternatively or additionally, a set of metal oxide blocking dielectric material portions can be formed in the backside recesses to retard or prevent fluorine diffusion. To minimize adverse impact on the electrically conductive layers formed in the backside recesses, the blocking dielectric material portions can be laterally recessed from a trench employed to form the backside recesses.
摘要翻译：提供了用于阻止或减少氟扩散的阻挡电介质结构和/或较厚的阻挡金属膜。可以在延伸穿过电绝缘层和牺牲材料层的存储器堆叠结构中形成隔离电介质层作为存储膜的外层。在通过去除牺牲材料层形成背面凹槽之后，可以例如通过等离子体处理或热处理将掺杂剂引入到阻挡介电层的物理暴露部分中，以形成可以减少或防止氟扩散的氮氧化硅区域。或者或另外，可以在背面凹部中形成一组金属氧化物阻挡介电材料部分，以延迟或防止氟扩散。为了最小化对形成在背面凹槽中的导电层的不利影响，阻挡电介质材料部分可以从用于形成背面凹槽的沟槽侧向凹入。

8. 发明授权

US09406391B1 Method of reducing hot electron injection type of read disturb in dummy memory cells 有权
标题翻译：在虚拟存储器单元中减少热电子注入类型的读取干扰的方法
公开(公告)号：US09406391B1
公开(公告)日：2016-08-02
申请号：US14924379
申请日：2015-10-27
申请人： SanDisk Technologies Inc.
发明人： Hong-Yan Chen , Yingda Dong , Wei Zhao
IPC分类号： G11C16/04 , G11C16/28 , G11C16/08 , G11C16/34 , G11C7/10
CPC分类号： G11C16/28 , G11C7/1051 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/3427
摘要： Read disturb is reduced for dummy memory cells in a charge-trapping memory device such as a 3D memory device. The memory device includes a selected NAND string and an unselected NAND string. In the unselected NAND string, a dummy memory cell is adjacent to a select gate transistor. During a read operation involving the selected NAND string, a voltage of the dummy memory cell is increased in two steps to minimize a gradient in a channel of the unselected NAND string between the dummy memory cell and the select gate transistor. During the first step, the select gate transistor is conductive so that the channel is connected to a driven bit line. During the second step, the select gate transistor is non-conductive. Voltages on unselected word lines can also be increased in two steps to set a desired channel boosting level in the unselected NAND string.
摘要翻译：对于诸如3D存储器装置的电荷俘获存储器件中的虚拟存储器单元，读取干扰被减少。存储器件包括所选择的NAND串和未选择的NAND串。在未选择的NAND串中，虚拟存储单元与选择栅极晶体管相邻。在涉及所选择的NAND串的读取操作期间，两个步骤增加了虚拟存储单元的电压，以最小化虚拟存储单元和选择栅极晶体管之间未被选择的NAND串的通道中的梯度。在第一步骤期间，选择栅极晶体管导通，使得沟道连接到从动位线。在第二步骤期间，选择栅极晶体管是非导通的。未选择字线上的电压也可以分两步增加，以在未选择的NAND串中设置所需的通道升压电平。

9. 发明授权

US09336891B2 Look ahead read method for non-volatile memory 有权
标题翻译：展望非易失性存储器的读取方法
公开(公告)号：US09336891B2
公开(公告)日：2016-05-10
申请号：US14322055
申请日：2014-07-02
申请人： SanDisk Technologies Inc.
发明人： Jiahui Yuan , Yingda Dong , Wei Zhao
IPC分类号： G11C16/34 , G11C16/26 , G11C11/56 , H01L27/115
CPC分类号： G11C16/34 , G11C11/5642 , G11C16/26 , G11C16/3427 , G11C2211/5648 , H01L27/1157 , H01L27/11582
摘要： A read operation for selected memory cell on a selected word line compensates for program disturb which is a nonlinear function of the data state of an adjacent memory cell on an adjacent word line. When a command to perform a read operation for the selected memory cell is received, a read operation is first performed on the adjacent memory cell to determine its data state, or to classify the adjacent memory cell into a threshold voltage range which includes one or more data states, or a portion of a data state. The selected memory cell is then read using a baseline control gate voltage which does not provide compensation, and one or more elevated control gate voltages which provide compensation, to distinguish between two adjacent data states. An optimal sensing result is selected based on the data state or threshold voltage range of the adjacent memory cell.
摘要翻译：对所选择的字线上的所选存储单元的读操作补偿作为相邻字线上相邻存储单元的数据状态的非线性函数的程序干扰。当接收到对所选择的存储单元执行读取操作的命令时，首先对相邻的存储器单元执行读取操作以确定其数据状态，或将相邻的存储器单元分类为包括一个或多个数据状态或数据状态的一部分。然后使用不提供补偿的基线控制栅极电压以及提供补偿的一个或多个升高的控制栅极电压来读取所选择的存储器单元，以区分两个相邻的数据状态。基于相邻存储单元的数据状态或阈值电压范围来选择最佳感测结果。

10. 发明授权

US09236396B1 Three dimensional NAND device and method of making thereof 有权
标题翻译：三维NAND器件及其制造方法
公开(公告)号：US09236396B1
公开(公告)日：2016-01-12
申请号：US14539307
申请日：2014-11-12
申请人： SanDisk Technologies, Inc.
发明人： Sateesh Koka , Senaka Kanakamedala , Yanli Zhang , Raghuveer S. Makala , Rahul Sharangpani , George Matamis , Wei Zhao
IPC分类号： H01L29/788 , H01L27/115 , H01L21/28 , H01L21/02 , H01L29/51 , H01L29/49
CPC分类号： H01L27/11582 , H01L21/02164 , H01L21/0217 , H01L21/02238 , H01L21/02532 , H01L21/02592 , H01L21/02595 , H01L21/28273 , H01L21/28282 , H01L27/11556 , H01L29/495 , H01L29/517 , H01L29/7883
摘要： A monolithic three dimensional NAND string includes a semiconductor channel, at least one end part of the semiconductor channel extending substantially perpendicular to a major surface of a substrate and a plurality of control gate electrodes extending substantially parallel to the major surface of the substrate. The NAND string also includes a memory film located between the semiconductor channel and the plurality of control gate electrodes and a blocking dielectric containing a plurality of clam-shaped portions each having two horizontal portions connected by a vertical portion. The NAND string also includes a plurality of discrete cover silicon oxide segments located between the memory film and each respective clam-shaped portion of the blocking dielectric containing a respective control gate electrode. Each of the plurality of cover silicon oxide segments has curved upper and lower sides and substantially straight vertical sidewalls.
摘要翻译：单片三维NAND串包括半导体沟道，半导体沟道的至少一个端部基本上垂直于衬底的主表面延伸，以及基本上平行于衬底的主表面延伸的多个控制栅电极。 NAND串还包括位于半导体通道和多个控制栅极电极之间的记忆膜，以及包含多个蛤状部分的阻挡电介质，每个蛤状部分具有通过垂直部分连接的两个水平部分。 NAND串还包括位于存储器膜和阻挡电介质的每个相应蛤状部分之间的多个分立的覆盖氧化硅段，其包含相应的控制栅电极。多个覆盖氧化硅段中的每一个具有弯曲的上侧和下侧以及基本上直的垂直侧壁。

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