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1. 发明授权

US09728551B1 Multi-tier replacement memory stack structure integration scheme 有权
公开(公告)号：US09728551B1
公开(公告)日：2017-08-08
申请号：US15015190
申请日：2016-02-04
申请人： SANDISK TECHNOLOGIES INC.
发明人： Ching-Huang Lu , Zhenyu Lu , Jixin Yu , Daxin Mao , Johann Alsmeier , Wenguang Stephen Shi , Henry Chien
IPC分类号： H01L29/74 , H01L29/80 , H01L29/792 , H01L21/00 , H01L21/336 , H01L27/11582 , H01L27/11556 , H01L27/11519 , H01L27/11565 , H01L23/528 , H01L23/522 , H01L29/788 , H01L29/04 , H01L21/28 , H01L21/225 , H01L21/30 , H01L21/02 , H01L27/11524 , H01L27/1157
CPC分类号： H01L27/11582 , H01L21/02164 , H01L21/0217 , H01L21/02236 , H01L21/2251 , H01L21/3003 , H01L23/5226 , H01L23/528 , H01L27/1157
摘要： A memory opening can be formed through a multiple tier structure. Each tier structure includes an alternating stack of sacrificial material layers and insulating layers. After formation of a dielectric oxide layer, the memory opening is filled with a sacrificial memory opening fill structure. The sacrificial material layers are removed selective to the insulating layers and the dielectric oxide layer to form backside recesses. Physically exposed portions of the dielectric oxide layer are removed. A backside blocking dielectric and electrically conductive layers are formed in the backside recesses. Subsequently, the sacrificial memory opening fill structure is replaced with a memory stack structure including a plurality of charge storage regions and a semiconductor channel. Hydrogen or deuterium from a dielectric core may then be outdiffused into the semiconductor channel.

2. 发明授权

US09530785B1 Three-dimensional memory devices having a single layer channel and methods of making thereof 有权
标题翻译：具有单层通道的三维存储器件及其制造方法
公开(公告)号：US09530785B1
公开(公告)日：2016-12-27
申请号：US14804564
申请日：2015-07-21
申请人： SanDisk Technologies, Inc.
发明人： Sateesh Koka , Zhenyu Lu , Wei Zhao , Ching-Huang Lu , Henry Chien , Yingda Dong , Raghuveer S. Makala , Somesh Peri , Rahul Sharangpani , George Matamis , Yuichi Ikezono , Hiroyuki Ogawa
IPC分类号： H01L29/76 , H01L27/115
CPC分类号： H01L27/1157 , H01L21/28282 , H01L27/0688 , H01L27/11524 , H01L27/11556 , H01L27/11582
摘要： A memory stack structure for a three-dimensional device includes an alternating stack of insulator layers and spacer material layers. A memory opening is formed through the alternating stack. A memory material layer, a tunneling dielectric layer, and a silicon oxide liner are formed in the memory opening. A sacrificial liner is subsequently formed over the tunneling dielectric layer. The layer stack is anisotropically etched to physically expose a semiconductor surface of the substrate underneath the memory opening. The sacrificial liner may be removed prior to, or after, the anisotropic etch. The silicon oxide liner is removed after the anisotropic etch. A semiconductor channel layer can be deposited directly on the tunneling dielectric layer as a single material layer without any interface therein.
摘要翻译：用于三维器件的存储器堆叠结构包括交替堆叠的绝缘体层和间隔物材料层。通过交替堆叠形成存储器开口。在存储器开口中形成记忆材料层，隧道介电层和氧化硅衬垫。随后在隧道电介质层上形成牺牲衬垫。层叠堆叠被各向异性蚀刻以物理地暴露存储器开口下方的衬底的半导体表面。可以在各向异性蚀刻之前或之后去除牺牲衬垫。在各向异性蚀刻之后去除氧化硅衬垫。可以将半导体沟道层直接沉积在隧道电介质层上作为单个材料层而没有任何界面。

3. 发明授权

US09437305B2 Programming memory with reduced short-term charge loss 有权
公开(公告)号：US09437305B2
公开(公告)日：2016-09-06
申请号：US14925473
申请日：2015-10-28
申请人： SanDisk Technologies Inc.
发明人： Ching-Huang Lu , Yingda Dong , Liang Pang , Tien-Chien Kuo
IPC分类号： G11C16/10 , G11C16/34 , G11C16/04 , G11C11/56
CPC分类号： G11C16/10 , G11C11/5628 , G11C11/5671 , G11C16/0466 , G11C16/3404 , G11C16/3459
摘要： Techniques are provided for reducing the effects of short-term charge loss while programming charge-trapping memory cells. Short-term charge loss can result in a downshift and widening of a threshold voltage distribution. A programming operation includes a rough programming pass in which memory cells are programmed close to a final threshold voltage distribution, for each target data state. Subsequently, a negative voltage is applied to control gates of the memory cells. Subsequently, a final programming pass is performed in which the memory cells are programmed to the final threshold voltage distribution. Since the negative voltage accelerates charge loss, there is reduced charge loss after the final programming pass. The rough programming pass can use incremental step pulse programming for the lowest target data state to obtain information regarding programming speed. An initial program voltage in the final programming pass can be set based on the programming speed.

4. 发明授权

US09406387B2 Charge redistribution during erase in charge trapping memory 有权
标题翻译：在电荷捕获存储器中的擦除期间的电荷再分配
公开(公告)号：US09406387B2
公开(公告)日：2016-08-02
申请号：US14851639
申请日：2015-09-11
申请人： SanDisk Technologies Inc.
发明人： Jiahui Yuan , Ching-Huang Lu , Yingda Dong
IPC分类号： G11C16/04 , G11C16/14 , G11C16/34 , G11C16/16 , G11C11/56 , G11C16/26 , H01L27/115
CPC分类号： G11C16/14 , G11C11/5635 , G11C11/5671 , G11C16/0466 , G11C16/0483 , G11C16/16 , G11C16/26 , G11C16/3418 , G11C16/344 , G11C16/3445 , G11C2211/5621 , H01L27/11582
摘要： Techniques are provided to accelerate the redistribution of the holes in connection with an erase operation, so that there will be a reduced amount of redistribution of the holes after programming. As a result, short-term charge loss after programming is reduced. In one aspect, a positive control gate voltage is applied to a set of memory cells after erase and before programming. The positive control gate voltage has a relatively low amplitude and a long duration, compared to a programming voltage. The positive control gate voltage can be adjusted based on the erase depth of the memory cells and factors such as a count of program-erase cycles, a count of erase-verify iterations, sensing of a position of the lower tail, and a cross-sectional width of a vertical pillar of a memory hole.
摘要翻译：提供了技术来加速与擦除操作相关的孔的再分配，使得在编程之后孔将再次分配。因此，编程后的短期电荷损失减少。在一个方面，在擦除和编程之前，将一个正的控制栅极电压施加到一组存储器单元。与编程电压相比，正控制栅极电压具有相对较低的幅度和长的持续时间。可以基于存储器单元的擦除深度和诸如编程擦除周期的计数，擦除验证迭代的计数，下部尾部的位置的感测以及交叉点的位移等因素来调整正控制栅极电压。存储孔的垂直柱的截面宽度。

5. 发明授权

US09378832B1 Method to recover cycling damage and improve long term data retention 有权
标题翻译：恢复循环损伤并改善长期数据保留的方法
公开(公告)号：US09378832B1
公开(公告)日：2016-06-28
申请号：US14565729
申请日：2014-12-10
申请人： SanDisk Technologies Inc.
发明人： Ching-Huang Lu , Zhengyi Zhang , Wei Zhao , Yingda Dong , Jian Chen
IPC分类号： G11C16/16 , G11C16/34 , G11C16/04 , G11C16/32
CPC分类号： G11C16/16 , G11C16/0466 , G11C16/0483 , G11C16/32 , G11C16/3431 , G11C16/3459 , G11C16/349 , G11C16/3495
摘要： Techniques for reversing damage caused by program-erase cycles in charge-trapping memory to improve long term data retention. A recovery process improves the data retention of a block of memory cells by programming the memory cells to a relatively high threshold voltage and enforcing a time period of several minutes or hours in which the memory cells are inactive and remain at the relatively high Vth levels. Damage such as traps in the memory cells is essentially healed or annealed out during this inactive period. All of the memory cells can be healed at the same time and by relatively equal amounts. At the conclusion of the recovery process, the block is returned to a pool of available blocks. In one approach, an amount of recovery is measured and the period of inactivity is continued for an amount of time which is based on the amount of recovery.
摘要翻译：用于在电荷捕获存储器中逆转由编程擦除周期引起的损坏以改善长期数据保持的技术。恢复过程通过将存储器单元编程到相对较高的阈值电压并且执行存储器单元不活动并保持在相对高的Vth电平的几分钟或数小时的时间段来改善存储器单元块的数据保持。在这个不活跃的时期，诸如记忆单元中的陷阱的损伤基本上被愈合或退火。所有的记忆细胞可以同时和相对相等的量治愈。在恢复过程结束时，块将返回到可用块池。在一种方法中，测量恢复量，并且基于回收量，持续不活动的时间持续一段时间。

6. 发明授权

US09324439B1 Weak erase after programming to improve data retention in charge-trapping memory 有权
标题翻译：程序设计后擦除弱，以提高电荷俘获存储器中的数据保留
公开(公告)号：US09324439B1
公开(公告)日：2016-04-26
申请号：US14518340
申请日：2014-10-20
申请人： SanDisk Technologies Inc.
发明人： Hong-Yan Chen , Yingda Dong , Ching-Huang Lu
IPC分类号： G11C16/34 , G11C16/14 , G11C16/04
CPC分类号： G11C16/14 , G11C11/5671 , G11C16/0466 , G11C16/0483 , G11C16/3404 , G11C16/3409 , G11C16/3413
摘要： Techniques are provided to improve long term data retention in a charge-trapping memory device. In addition to a primary charge-trapping layer in which most charges are stored, the memory device may include a tunneling layer comprising an engineered tunneling barrier such as oxide-nitride-oxide. The nitride in the tunneling layer may also store some charges after programming. After the programming, a data retention operation is performed which de-traps some electrons from the tunneling layer, in addition to injecting holes into the tunneling layer which form neutral electron-hole dipoles in place of electrons. These mechanisms tend to lower threshold voltage. Additionally, the data retention operation redistributes the electrons and the holes inside the charge-trapping layer, resulting in an increase in threshold voltage which roughly cancels out the decrease when the data retention operation is optimized.
摘要翻译：提供技术来改善电荷俘获存储器件中的长期数据保持。除了存储大多数电荷的主电荷捕获层之外，存储器件可以包括隧道层，其包括工程化隧道势垒，例如氧化物 - 氮化物 - 氧化物。在编程之后，隧道层中的氮化物也可能存储一些电荷。在编程之后，除了将空穴注入到形成中性电子 - 空穴偶极子的隧道层中以代替电子之外，还执行了从隧道层去除一些电子的数据保留操作。这些机制倾向于降低阈值电压。此外，数据保持操作将电荷和空穴重新分布在电荷俘获层内部，导致阈值电压的增加，这在数据保持操作优化时大致抵消了减少。

7. 发明申请

US20160064090A1 Charge Redistribution During Erase In Charge Trapping Memory 有权
公开(公告)号：US20160064090A1
公开(公告)日：2016-03-03
申请号：US14851639
申请日：2015-09-11
申请人： SanDisk Technologies Inc.
发明人： Jiahui Yuan , Ching-Huang Lu , Yingda Dong
IPC分类号： G11C16/14 , G11C16/26 , G11C16/34 , G11C16/04
CPC分类号： G11C16/14 , G11C11/5635 , G11C11/5671 , G11C16/0466 , G11C16/0483 , G11C16/16 , G11C16/26 , G11C16/3418 , G11C16/344 , G11C16/3445 , G11C2211/5621 , H01L27/11582
摘要： Techniques are provided to accelerate the redistribution of the holes in connection with an erase operation, so that there will be a reduced amount of redistribution of the holes after programming. As a result, short-term charge loss after programming is reduced. In one aspect, a positive control gate voltage is applied to a set of memory cells after erase and before programming. The positive control gate voltage has a relatively low amplitude and a long duration, compared to a programming voltage. The positive control gate voltage can be adjusted based on the erase depth of the memory cells and factors such as a count of program-erase cycles, a count of erase-verify iterations, sensing of a position of the lower tail, and a cross-sectional width of a vertical pillar of a memory hole.

8. 发明授权

US09852803B2 Dummy word line control scheme for non-volatile memory 有权
公开(公告)号：US09852803B2
公开(公告)日：2017-12-26
申请号：US15151951
申请日：2016-05-11
申请人： SANDISK TECHNOLOGIES INC.
发明人： Vinh Quang Diep , Liang Pang , Ching-Huang Lu , Yingda Dong
IPC分类号： G11C16/04 , G11C16/34 , G11C16/28 , G11C16/16 , G11C16/10 , G11C16/08
CPC分类号： G11C16/3431 , G11C7/04 , G11C7/14 , G11C8/08 , G11C11/5628 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/16 , G11C16/28
摘要： A memory system includes blocks (or other groupings) of memory cells including data memory cells and dummy memory cells. In order to mitigate program disturb or other issues, the memory system applies a gate voltage based on temperature to all or a subset of the dummy memory cells as part of a memory operation.

9. 发明申请

US20160099058A1 Programming Of Drain Side Word Line To Reduce Program Disturb And Charge Loss 有权
标题翻译：排水侧字线的编程可减少程序扰乱和充电损失
公开(公告)号：US20160099058A1
公开(公告)日：2016-04-07
申请号：US14508164
申请日：2014-10-07
申请人： SanDisk Technologies Inc.
发明人： Jiahui Yuan , Yingda Dong , Ching-Huang Lu , Wei Zhao
IPC分类号： G11C16/10 , G11C16/34 , G11C16/04
CPC分类号： G11C16/10 , G11C11/5671 , G11C16/0466 , G11C16/0483 , G11C16/3427 , G11C16/3459 , G11C2211/5621 , G11C2211/5648
摘要： Techniques are provided for programming the memory cells of a drain-side edge word line of a set of word lines before programming memory cells of any other word line of the set. Pass voltages applied to the other word lines act as stress pulses which redistribute holes in the charge-trapping material of the memory cells of the other word lines to reduce short-term charge loss and downshifting of the threshold voltage. Additionally, one or more initial program voltages used for the drain-side edge word line are relatively low and also act as stress pulses. The memory cells of the drain-side edge word line are programmed to a narrower Vth window than the memory cells of the other word lines. This compensates for a higher level of program disturb of erased state memory cells of the drain-side edge word line due to reduced channel boosting.
摘要翻译：提供了在编程集合的任何其他字线的存储器单元之前对一组字线集合的漏极边缘字线的存储器单元进行编程的技术。施加到其它字线的通过电压作为应力脉冲，其重新分配其它字线的存储单元的电荷捕获材料中的空穴，以减少阈值电压的短期电荷损耗和降档。此外，用于漏极侧边缘字线的一个或多个初始编程电压相对较低并且还用作应力脉冲。漏极侧边缘字线的存储单元被编程到比其它字线的存储单元窄的Vth窗口。这由于减少的信道增强而补偿了漏极侧边缘字线的擦除状态存储单元的编程干扰的较高水平。

10. 发明申请

US20160064087A1 Charge Redistribution During Erase In Charge Trapping Memory 有权
标题翻译：在擦除充电陷阱存储器期间的电荷再分配
公开(公告)号：US20160064087A1
公开(公告)日：2016-03-03
申请号：US14472889
申请日：2014-08-29
申请人： SanDisk Technologies Inc.
发明人： Jiahui Yuan , Ching-Huang Lu , Yingda Dong
IPC分类号： G11C16/14 , G11C16/26 , G11C16/34 , G11C16/04
CPC分类号： G11C16/14 , G11C11/5635 , G11C11/5671 , G11C16/0466 , G11C16/0483 , G11C16/16 , G11C16/26 , G11C16/3418 , G11C16/344 , G11C16/3445 , G11C2211/5621 , H01L27/11582
摘要： Techniques are provided to accelerate the redistribution of the holes in connection with an erase operation, so that there will be a reduced amount of redistribution of the holes after programming. As a result, short-term charge loss after programming is reduced. In one aspect, a positive control gate voltage is applied to a set of memory cells after erase and before programming. The positive control gate voltage has a relatively low amplitude and a long duration, compared to a programming voltage. The positive control gate voltage can be adjusted based on the erase depth of the memory cells and factors such as a count of program-erase cycles, a count of erase-verify iterations, sensing of a position of the lower tail, and a cross-sectional width of a vertical pillar of a memory hole.
摘要翻译：提供了技术来加速与擦除操作相关的孔的再分配，使得在编程之后孔将再次分配。因此，编程后的短期电荷损失减少。在一个方面，在擦除和编程之前，将一个正的控制栅极电压施加到一组存储器单元。与编程电压相比，正控制栅极电压具有相对较低的幅度和长的持续时间。可以基于存储器单元的擦除深度和诸如编程擦除周期的计数，擦除验证迭代的计数，下部尾部的位置的感测以及交叉点的位移等因素来调整正控制栅极电压。存储孔的垂直柱的截面宽度。

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