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1. 发明授权

US09620238B2 Methods and systems that selectively inhibit and enable programming of non-volatile storage elements 有权
公开(公告)号：US09620238B2
公开(公告)日：2017-04-11
申请号：US14493039
申请日：2014-09-22
申请人： SanDisk Technologies Inc.
发明人： Anubhav Khandelwal , Dana Lee , Henry Chin , LanLan Gu
IPC分类号： G11C11/34 , G11C16/34 , G11C11/56
CPC分类号： G11C16/3459 , G11C11/5628
摘要： Non-volatile storage systems, and methods for programming non-volatile storage elements of non-volatile storage systems, are described herein. A method for programming a non-volatile storage element, wherein a loop number is incremented with each program-verify iteration includes performing a plurality of program-verify iterations for the non-volatile storage element. This includes inhibiting programming of the non-volatile storage element when the loop number is less than a loop number threshold corresponding to a target data state that the storage element is being programmed to. This also includes enabling programming of the non-volatile storage element when the the loop number is greater than or equal to the loop number threshold corresponding to the target data state that the storage element is being programmed to. Inhibiting programming of the non-volatile storage element causes boosting of a channel voltage of the storage element, which speeds up programming of one or more further non-volatile storage elements neighboring the boosted storage element, compared to if there were no such boosting.

2. 发明授权

US09269444B2 Adaptive initial program voltage for non-volatile memory 有权
公开(公告)号：US09269444B2
公开(公告)日：2016-02-23
申请号：US14600588
申请日：2015-01-20
申请人： SANDISK TECHNOLOGIES INC.
发明人： Henry Chin , Dana Lee
IPC分类号： G11C16/04 , G11C16/10 , G06F12/02 , G11C11/56 , G11C16/34
CPC分类号： G11C16/10 , G06F12/0246 , G11C11/5628 , G11C16/3486
摘要： When programming a set of non-volatile storage elements using a multi-stage programming process, a series of programming pulses are used for each stage. The magnitude of the initial program pulse for the current stage being performed is dynamically set as a function of the number of program pulses used for the same stage of the multi-stage programming process when programming non-volatile storage elements connected to on one or more previously programmed word lines.

3. 发明授权

US08971128B2 Adaptive initial program voltage for non-volatile memory 有权
标题翻译：用于非易失性存储器的自适应初始编程电压
公开(公告)号：US08971128B2
公开(公告)日：2015-03-03
申请号：US13756387
申请日：2013-01-31
申请人： Sandisk Technologies, Inc.
发明人： Henry Chin , Dana Lee
IPC分类号： G11C16/04 , G06F12/02 , G11C16/34 , G11C16/10 , G11C11/56
CPC分类号： G11C16/10 , G06F12/0246 , G11C11/5628 , G11C16/3486
摘要： When programming a set of non-volatile storage elements using a multi-stage programming process, a series of programming pulses are used for each stage. The magnitude of the initial program pulse for the current stage being performed is dynamically set as a function of the number of program pulses used for the same stage of the multi-stage programming process when programming non-volatile storage elements connected to on one or more previously programmed word lines.
摘要翻译：当使用多级编程处理对一组非易失性存储元件进行编程时，每个级使用一系列编程脉冲。正在执行的当前级的初始编程脉冲的幅度被动态地设置为当编程连接到一个或多个的非易失性存储元件时用于多级编程处理的相同阶段的编程脉冲的数量的函数以前编程的字线。

4. 发明授权

US08928061B2 Three dimensional NAND device with silicide containing floating gates 有权
标题翻译：具有含有浮动栅极的硅化物的三维NAND器件
公开(公告)号：US08928061B2
公开(公告)日：2015-01-06
申请号：US14190974
申请日：2014-02-26
申请人： SanDisk Technologies Inc.
发明人： Henry Chien , Johann Alsmeier , George Samachisa , Henry Chin , George Matamis , Yuan Zhang , James Kai , Vinod Purayath , Donovan Lee
IPC分类号： H01L29/788
CPC分类号： H01L27/11556 , H01L21/28273 , H01L21/32053 , H01L27/11551 , H01L27/11578 , H01L27/11582 , H01L29/4925 , H01L29/495 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： A monolithic three dimensional NAND string includes a semiconductor channel located over a substrate, a plurality of control gates extending substantially parallel to the major surface of the substrate including a first control gate located in a first device level and a second control gate located in a second device level located over the substrate and below the first device level, a charge storage material including a silicide layer located in the first device level and in the second device level, a blocking dielectric located between the charge storage material and the plurality of control gates, and a tunnel dielectric located between the charge storage material and the semiconductor channel. The tunnel dielectric has a straight sidewall, portions of the blocking dielectric have a clam shape, and each of the plurality of control gates is located at least partially in an opening in the clam-shaped portion of the blocking dielectric.
摘要翻译：单片三维NAND串包括位于基板上方的半导体通道，基本上平行于基板的主表面延伸的多个控制栅极，包括位于第一器件级的第一控制栅极和位于第二器件级的第二控制栅极器件级位于衬底上并低于第一器件级，电荷存储材料包括位于第一器件级和第二器件级的硅化物层，位于电荷存储材料和多个控制栅之间的阻挡电介质，以及位于电荷存储材料和半导体沟道之间的隧道电介质。隧道电介质具有直的侧壁，阻挡电介质的部分具有蛤形，并且多个控制栅极中的每一个至少部分地位于阻挡电介质的蛤状部分的开口中。

5. 发明授权

US08644075B2 Ramping pass voltage to enhance channel boost in memory device 有权
标题翻译：缓存通过电压以增强存储器件中的通道升压
公开(公告)号：US08644075B2
公开(公告)日：2014-02-04
申请号：US13955597
申请日：2013-07-31
申请人： SanDisk Technologies Inc.
发明人： Gerrit Jan Hemink , Shih-Chung Lee , Anubhav Khandelwal , Henry Chin , Guirong Liang , Dana Lee
IPC分类号： G11C11/34
CPC分类号： G11C16/3427 , G11C16/10
摘要： In a non-volatile storage system, first and second substrate channel regions for an unselected NAND string are boosted during programming to inhibit program disturb. The first and second substrate channel regions are created on either side of an isolation word line. During a program pulse time period in which a program pulse is applied to a selected word line, a voltage applied to an unselected word line which extends directly over the second channel region is stepped up to a respective pre-program pulse voltage, at a faster rate at which a voltage applied to an unselected word line which extends directly over the first channel region is stepped up to a respective pre-program pulse voltage. This helps improve the isolation between the channel regions.
摘要翻译：在非易失性存储系统中，用于未选择的NAND串的第一和第二衬底沟道区在编程期间被增强以抑制编程干扰。第一和第二衬底沟道区域在隔离字线的任一侧上产生。在将编程脉冲施加到所选字线的编程脉冲时间段期间，施加到直接在第二通道区域上延伸的未选择字线的电压以更快的速度升高到相应的预编程脉冲电压施加到直接在第一通道区域上延伸的未选择字线的电压的速率被升高到相应的预编程脉冲电压。这有助于改善通道区域之间的隔离。

6. 发明授权

US09455038B2 Storage module and method for using healing effects of a quarantine process 有权
标题翻译：使用隔离过程的治疗效果的存储模块和方法
公开(公告)号：US09455038B2
公开(公告)日：2016-09-27
申请号：US14510945
申请日：2014-10-09
申请人： SanDisk Technologies Inc.
发明人： Daniel E. Tuers , Dana Lee , Henry Chin , Abhijeet Manohar
IPC分类号： G11C27/00 , G11C16/04 , G11C11/56 , G11C29/44 , G11C16/34
CPC分类号： G11C16/0466 , G11C11/5671 , G11C16/3404 , G11C16/3418 , G11C16/349 , G11C29/4401
摘要： A storage module and method are provided for using healing effects of a quarantine process. In one embodiment, a storage module is provided comprising a controller and a memory. The controller is configured to identify a set of memory cells in the memory that contains a bit error rate above a threshold, wherein the bit error rate is above the threshold due to trapped charge in dielectrics of the memory cells. The controller is also configured to quarantine the set of memory cells for a period of time, wherein while the set of memory cells is quarantined, heat generated by the storage module anneals the set of memory cells to at least partially remove the trapped charge.
摘要翻译：提供了一种使用隔离过程的治疗效果的存储模块和方法。在一个实施例中，提供了包括控制器和存储器的存储模块。控制器被配置为识别存储器中的一组存储器单元，其中存储器单元包含高于阈值的误码率，其中由于存储器单元的电介质中的俘获电荷，误码率高于阈值。控制器还被配置为隔离一段时间的存储器单元，其中当存储器单元组被隔离时，由存储模块产生的热量使该组存储器单元退回至少部分地去除被捕获的电荷。

7. 发明申请

US20160172045A1 Partial Block Erase For Open Block Reading In Non-Volatile Memory 有权
标题翻译：非易失性存储器中的块读取部分块擦除
公开(公告)号：US20160172045A1
公开(公告)日：2016-06-16
申请号：US14794242
申请日：2015-07-08
申请人： SanDisk Technologies Inc.
发明人： Pitamber Shukla , Henry Chin , Dana Lee , Cynthia Hsu
IPC分类号： G11C16/16 , G11C16/26 , G11C16/34 , G11C16/04
CPC分类号： G11C16/16 , G11C11/5628 , G11C16/0483 , G11C16/26 , G11C16/3431 , G11C16/3445 , G11C2211/5644
摘要： A non-volatile memory system mitigates the effects of open block reading by analyzing the un-programmed region of a block before programming to determine a potential for read disturbance. The system may determine a read count value associated with open block reading of the memory block and/or perform partial block erase verification. To mitigate the effects of open block read disturbance, the system performs partial block erase for the un-programmed region of the memory block and/or limits programming in the un-programmed region.
摘要翻译：非易失性存储器系统通过在编程之前分析块的未编程区域来确定读取干扰的可能性来缓解开放块读取的影响。系统可以确定与存储块的开放块读取相关联的读取计数值和/或执行部分块擦除验证。为了减轻开放块读取干扰的影响，系统对存储器块的未编程区域执行部分块擦除和/或限制非编程区域中的编程。

8. 发明申请

US20160141046A1 Techniques for Reducing Read Disturb in Partially Written Blocks of Non-Volatile Memory 有权
标题翻译：减少非易失性存储器部分写入块中的读取干扰的技术
公开(公告)号：US20160141046A1
公开(公告)日：2016-05-19
申请号：US14543660
申请日：2014-11-17
申请人： SanDisk Technologies, Inc.
发明人： Anubhav Khandelwal , Dana Lee , Abhijeet Manohar , Henry Chin , Gautam Dusija , Daniel Tuers , Chris Avila , Cynthia Hsu
IPC分类号： G11C16/34 , G11C11/56
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/26 , G11C16/32 , G11C16/3418
摘要： Techniques are presented to reduce the amount of read disturb on partially written blocks of NAND type non-volatile memory, both for when determining the last written word line in a block and also for data read. In both cases, non-selected word lines that are unwritten or, in the case of finding the last written word line, may be unwritten are biased with a lower read-pass voltage then is typically used. The result of such reads can also be applied to an algorithm for finding the last written word by skipping a varying number of word lines. Performance in a last written page determination can also be improved by use of shorter bit line settling times than for a standard read.
摘要翻译：呈现技术以减少部分写入的NAND型非易失性存储器块的读取干扰量，这两者都用于当确定块中的最后写入字线以及数据读取时。在这两种情况下，通常使用未被写入的未选择字线，或者在找到最后写入的字线的情况下，可能未被写入的低通读出电压被偏置。这种读取的结果也可以应用于通过跳过不同数量的字线来找到最后写入的字的算法。通过使用比标准读取更短的位线建立时间，也可以改善最后写入的页面确定中的性能。

9. 发明申请

US20160054937A1 TEMPERATURE ACCELERATED STRESS TIME 有权
标题翻译：温度加速应力时间
公开(公告)号：US20160054937A1
公开(公告)日：2016-02-25
申请号：US14510771
申请日：2014-10-09
申请人： SanDisk Technologies Inc.
发明人： Daniel E. Tuers , Dana Lee , Henry Chin , Abhijeet Manohar
IPC分类号： G06F3/06
CPC分类号： G11C16/3495 , G11C7/04
摘要： A memory system or flash card may be exposed to elapsed time or increased temperature conditions which may degrade the memory. For example, extended time periods or high temperature conditions may hinder data retention in a memory device. An estimate of elapsed time and temperature conditions may be useful for memory management. An algorithm that periodically identifies one or more sentinel blocks in the memory device and measures the data retention shift in those sentinel blocks can calculate a scalar value that approximates the combined effect of elapsed time and/or temperature conditions.
摘要翻译：存储器系统或闪存卡可能暴露于经过时间或升高的温度条件，这可能降低存储器。例如，延长的时间段或高温条件可能阻碍存储器设备中的数据保留。经过的时间和温度条件的估计可能对于存储器管理是有用的。周期性地识别存储器设备中的一个或多个前哨块并且测量那些哨兵块中的数据保持位移的算法可以计算近似经过的时间和/或温度条件的组合效应的标量值。

10. 发明授权

US09224494B2 Erase speed adjustment for endurance of non-volatile storage 有权
标题翻译：擦除非易失性存储的耐久性的速度调整
公开(公告)号：US09224494B2
公开(公告)日：2015-12-29
申请号：US14152834
申请日：2014-01-10
申请人： SanDisk Technologies Inc.
发明人： Henry Chin , Dana Lee
IPC分类号： G11C11/34 , G11C16/34 , G11C16/04 , G11C13/00 , G11C16/14 , G11C16/00 , G11C16/16
CPC分类号： G11C16/3454 , G11C13/0097 , G11C16/00 , G11C16/0483 , G11C16/14 , G11C16/16 , G11C16/3445
摘要： Techniques are disclosed herein for erasing non-volatile storage. The erase has two or more phases. The first phase includes erasing a group of non-volatile storage elements at a first speed until the group of non-volatile storage elements pass a first verify level. The second phase is performed after the group of non-volatile storage elements pass the first verify level. The second phase includes erasing the group of non-volatile storage elements at a second speed that is less than the first speed until the group of non-volatile storage elements pass a second verify level that is lower than the first verify level. Erasing at the first speed results in a fast erase without significant risk of over-erasing the storage elements. Erasing at the second speed during the second phase prevents or reduces over-erasure which could damage the storage elements.
摘要翻译：本文公开了用于擦除非易失性存储器的技术。擦除有两个或多个阶段。第一阶段包括以第一速度擦除一组非易失性存储元件，直到非易失性存储元件组通过第一验证电平。在非易失性存储元件组通过第一验证级别之后执行第二阶段。第二阶段包括以小于第一速度的第二速度擦除非易失性存储元件组，直到非易失性存储元件组通过低于第一验证电平的第二验证电平。以第一速度擦除会导致快速擦除，而不会有过度擦除存储元件的重大风险。在第二阶段以第二速度擦除可防止或减少可能损坏存储元件的过度擦除。

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