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1. 发明申请

US20150137208A1 NAND STRING CONTAINING SELF-ALIGNED CONTROL GATE SIDEWALL CLADDING 有权
公开(公告)号：US20150137208A1
公开(公告)日：2015-05-21
申请号：US14607339
申请日：2015-01-28
申请人： SANDISK TECHNOLOGIES INC.
发明人： Donovan Lee , Vinod Purayath , James Kai , George Matamis
IPC分类号： H01L27/115 , H01L29/423
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/11517 , H01L27/11524 , H01L29/42324 , H01L29/42328
摘要： A method of making a NAND string includes forming a tunnel dielectric over a semiconductor channel, forming a charge storage layer over the tunnel dielectric, forming a blocking dielectric over the charge storage layer, and forming a control gate layer over the blocking dielectric. The method also includes patterning the control gate layer to form a plurality of control gates separated by trenches, and reacting a first material with exposed sidewalls of the plurality of control gates to form self aligned metal-first material compound sidewall spacers on the exposed sidewalls of the plurality of control gates.

2. 发明申请

US20150072488A1 THREE DIMENSIONAL NAND DEVICE WITH SILICIDE CONTAINING FLOATING GATES AND METHOD OF MAKING THEREOF 有权
标题翻译：具有含硅浮选闸门的三维NAND器件及其制造方法
公开(公告)号：US20150072488A1
公开(公告)日：2015-03-12
申请号：US14539811
申请日：2014-11-12
申请人： SANDISK TECHNOLOGIES INC.
发明人： Henry Chien , Johann Alsmeier , George Samachisa , Henry Chin , George Matamis , Yuan Zhang , James Kai , Vinod Purayath , Donovan Lee
IPC分类号： H01L27/115 , H01L21/28 , H01L21/3205 , H01L29/49
CPC分类号： H01L27/11556 , H01L21/28273 , H01L21/32053 , H01L27/11551 , H01L27/11578 , H01L27/11582 , H01L29/4925 , H01L29/495 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： A method of making a monolithic three dimensional NAND string, including providing a stack of alternating first material layers and second material layers different from the first material layer over a substrate, the stack comprising at least one opening containing a charge storage material comprising a silicide layer, a tunnel dielectric on the charge storage material in the at least one opening, and a semiconductor channel on the tunnel dielectric in the at least one opening, selectively removing the second material layers without removing the first material layers from the stack and forming control gates between the first material layers.
摘要翻译：一种制造单片三维NAND串的方法，包括在衬底上提供交替的第一材料层和不同于第一材料层的第二材料层的堆叠，所述堆叠包括至少一个开口，其包含电荷存储材料，该电荷存储材料包括硅化物层在所述至少一个开口中的所述电荷存储材料上的隧道电介质，以及在所述至少一个开口中的所述隧道电介质上的半导体沟道，选择性地移除所述第二材料层而不从所述堆叠中移除所述第一材料层并形成控制栅极在第一材料层之间。

3. 发明授权

US09548311B2 Non-volatile storage element with suspended charge storage region 有权
标题翻译：具有悬浮电荷存储区域的非易失性存储元件
公开(公告)号：US09548311B2
公开(公告)日：2017-01-17
申请号：US15138615
申请日：2016-04-26
申请人： SanDisk Technologies Inc.
发明人： Donovan Lee , Vinod R Purayath , James Kai
IPC分类号： H01L29/00 , H01L27/115 , H01L21/311 , H01L29/66 , H01L29/423
CPC分类号： H01L27/11521 , H01L21/28273 , H01L21/31111 , H01L21/31144 , H01L21/76224 , H01L27/11517 , H01L27/11526 , H01L27/11529 , H01L29/42324 , H01L29/6653 , H01L29/6656 , H01L29/7881
摘要： Suspended charge storage regions are utilized for non-volatile storage to decrease parasitic interferences and increase charge retention in memory devices. Charge storage regions are suspended from an overlying intermediate dielectric material. The charge storage regions include an upper surface and a lower surface that extend in the row and column directions. The upper surface of the charge storage region is coupled to the overlying intermediate dielectric material. The lower surface faces the substrate surface and is separated from the substrate surface by a void. The charge storage region includes a first vertical sidewall and a second vertical sidewall that extend in the column direction and a third vertical sidewall and fourth vertical sidewall that extend in the row direction. The first, second, third, and fourth vertical sidewall are separated from neighboring features of the non-volatile memory by the void. The void may include a vacuum, air, gas, or a liquid.
摘要翻译：悬浮电荷存储区域用于非易失性存储以减少寄生干扰并增加存储器件中的电荷保持。电荷存储区域从上覆的中间介电材料悬浮。电荷存储区域包括在行和列方向上延伸的上表面和下表面。电荷存储区域的上表面与上覆的中间介电材料耦合。下表面面向基板表面，并通过空隙与基板表面分离。电荷存储区域包括在列方向上延伸的第一垂直侧壁和第二垂直侧壁以及沿行方向延伸的第三垂直侧壁和第四垂直侧壁。第一，第二，第三和第四垂直侧壁通过空隙与非易失性存储器的相邻特征分离。空隙可以包括真空，空气，气体或液体。

4. 发明授权

US09543139B2 In-situ support structure for line collapse robustness in memory arrays 有权
标题翻译：存储阵列线路崩溃鲁棒性的原位支持结构
公开(公告)号：US09543139B2
公开(公告)日：2017-01-10
申请号：US14246656
申请日：2014-04-07
申请人： SANDISK TECHNOLOGIES INC.
发明人： Akira Matsudaira , Donovan Lee
IPC分类号： H01L21/82 , H01L21/02 , H01L21/28 , H01L29/788 , H01L27/02 , H01L27/115
CPC分类号： H01L21/02164 , H01L21/28273 , H01L27/0207 , H01L27/11519 , H01L27/11524 , H01L29/7883
摘要： Methods for preventing line collapse during the fabrication of NAND flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be used to provide lateral support between closely spaced device structures to prevent collapsing of the closely spaced device structures during an etching process (e.g., during a word line etch). In one example, during fabrication of a NAND flash memory, one or more mechanical support structures may be in place prior to performing a high aspect ratio word line etch or may be formed during the word line etch. In some cases, the one or more mechanical support structures may comprise portions of an inter-poly dielectric (IPD) layer that were in place prior to performing the word line etch.
摘要翻译：描述了在制造NAND闪速存储器和利用具有高纵横比的紧密间隔的器件结构的其它微电子器件时防止线塌陷的方法。在一些实施例中，可以使用一个或多个机械支撑结构来在紧密间隔开的装置结构之间提供横向支撑，以防止在蚀刻过程（例如，在字线蚀刻期间）紧密间隔开的装置结构的折叠。在一个示例中，在NAND快闪存储器的制造过程中，在执行高宽比字线蚀刻之前，一个或多个机械支撑结构可以就位，或者可以在字线蚀刻期间形成。在一些情况下，一个或多个机械支撑结构可以包括在执行字线蚀刻之前就位的多晶硅间电介质（IPD）层的部分。

5. 发明授权

US09252151B2 Three dimensional NAND device with birds beak containing floating gates and method of making thereof 有权
公开(公告)号：US09252151B2
公开(公告)日：2016-02-02
申请号：US14183152
申请日：2014-02-18
申请人： SANDISK TECHNOLOGIES INC.
发明人： Henry Chien , Donovan Lee , Vinod R. Purayath , Yuan Zhang , James K. Kai , George Matamis
IPC分类号： H01L27/115 , H01L27/06 , H01L29/788 , H01L29/792 , H01L29/66
CPC分类号： H01L27/11556 , H01L27/0688 , H01L27/11551 , H01L27/1157 , H01L27/11582 , H01L29/66825 , H01L29/7889 , H01L29/7926
摘要： A method of making a monolithic three dimensional NAND string including forming a stack of alternating layers of a first material and a second material over a substrate. The first material comprises an electrically insulating material and the second material comprises a semiconductor or conductor material. The method also includes etching the stack to form a front side opening in the stack, forming a blocking dielectric layer over the stack of alternating layers of a first material and a second material exposed in the front side opening, forming a semiconductor or metal charge storage layer over the blocking dielectric, forming a tunnel dielectric layer over the charge storage layer, forming a semiconductor channel layer over the tunnel dielectric layer, etching the stack to form a back side opening in the stack, removing at least a portion of the first material layers and portions of the blocking dielectric layer.

6. 发明申请

US20150318295A1 VERTICAL FLOATING GATE NAND WITH OFFSET DUAL CONTROL GATES 审中-公开
标题翻译：垂直浮动门NAND与偏移双控制门
公开(公告)号：US20150318295A1
公开(公告)日：2015-11-05
申请号：US14265733
申请日：2014-04-30
申请人： SanDisk Technologies, Inc.
发明人： James Kai , Vinod Purayath , Donovan Lee , Akira Matsudaira
IPC分类号： H01L27/115 , H01L21/285 , H01L21/28 , H01L21/02 , H01L29/423 , H01L29/788
CPC分类号： H01L27/11556 , H01L27/11524
摘要： A method of making a monolithic three dimensional NAND string includes providing a stack of alternating insulating layers and control gate films over a major surface of a substrate. Each of the control gate films includes a middle layer located between a first control gate layer and a second control gate layer, the middle layer being a different material from the first and second control gate layers and from the insulating layers. The method also includes forming a front side opening in the stack, and forming a blocking dielectric, at least one charge storage region, a tunnel dielectric and a semiconductor channel in the front side opening in the stack.
摘要翻译：制造单片三维NAND串的方法包括在衬底的主表面上提供交替绝缘层和控制栅极膜的堆叠。每个控制栅膜包括位于第一控制栅极层和第二控制栅极层之间的中间层，中间层是与第一和第二控制栅极层以及绝缘层不同的材料。该方法还包括在堆叠中形成前侧开口，并且在堆叠中的前侧开口中形成阻挡电介质，至少一个电荷存储区，隧道电介质和半导体沟道。

7. 发明申请

US20140239365A1 METHOD FOR USING NANOPARTICLES TO MAKE UNIFORM DISCRETE FLOATING GATE LAYER 有权
标题翻译：使用纳米粒子制作均匀分离浮选盖层的方法
公开(公告)号：US20140239365A1
公开(公告)日：2014-08-28
申请号：US13781066
申请日：2013-02-28
申请人： SANDISK TECHNOLOGIES INC.
发明人： Donovan Lee , James Kai , Vinod Purayath , George Matamis , Steven J. Radigan
IPC分类号： H01L29/66 , H01L29/788
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/11524 , H01L29/42332 , H01L29/7881
摘要： A memory cell including a control gate located over a floating gate region. The floating gate region includes discrete doped semiconducting or conducting regions separated by an insulator and the discrete doped semiconducting or conducting regions have a generally cylindrical shape or a quasi-cylindrical shape.
摘要翻译：存储单元，包括位于浮动栅极区域上方的控制栅极。浮置栅极区域包括由绝缘体隔开的离散掺杂半导体或导电区域，并且离散掺杂的半导体或导电区域具有大致圆柱形或准圆柱形形状。

8. 发明授权

US09230971B2 NAND string containing self-aligned control gate sidewall cladding 有权
公开(公告)号：US09230971B2
公开(公告)日：2016-01-05
申请号：US14607339
申请日：2015-01-28
申请人： SANDISK TECHNOLOGIES INC.
发明人： Donovan Lee , Vinod Purayath , James Kai , George Matamis
IPC分类号： H01L29/423 , H01L27/115 , H01L21/28
CPC分类号： H01L27/11521 , H01L21/28273 , H01L27/11517 , H01L27/11524 , H01L29/42324 , H01L29/42328
摘要： A method of making a NAND string includes forming a tunnel dielectric over a semiconductor channel, forming a charge storage layer over the tunnel dielectric, forming a blocking dielectric over the charge storage layer, and forming a control gate layer over the blocking dielectric. The method also includes patterning the control gate layer to form a plurality of control gates separated by trenches, and reacting a first material with exposed sidewalls of the plurality of control gates to form self aligned metal-first material compound sidewall spacers on the exposed sidewalls of the plurality of control gates.

9. 发明申请

US20150287733A1 IN-SITU SUPPORT STRUCTURE FOR LINE COLLAPSE ROBUSTNESS IN MEMORY ARRAYS 有权
标题翻译：存储器阵列中线性逼真的现场支持结构
公开(公告)号：US20150287733A1
公开(公告)日：2015-10-08
申请号：US14246656
申请日：2014-04-07
申请人： SANDISK TECHNOLOGIES INC.
发明人： Akira Matsudaira , Donovan Lee
IPC分类号： H01L27/115 , H01L21/02 , H01L21/311 , H01L21/3213 , H01L21/28 , H01L29/788
CPC分类号： H01L21/02164 , H01L21/28273 , H01L27/0207 , H01L27/11519 , H01L27/11524 , H01L29/7883
摘要： Methods for preventing line collapse during the fabrication of NAND flash memory and other microelectronic devices that utilize closely spaced device structures with high aspect ratios are described. In some embodiments, one or more mechanical support structures may be used to provide lateral support between closely spaced device structures to prevent collapsing of the closely spaced device structures during an etching process (e.g., during a word line etch). In one example, during fabrication of a NAND flash memory, one or more mechanical support structures may be in place prior to performing a high aspect ratio word line etch or may be formed during the word line etch. In some cases, the one or more mechanical support structures may comprise portions of an inter-poly dielectric (IPD) layer that were in place prior to performing the word line etch.
摘要翻译：描述了在制造NAND闪速存储器和利用具有高纵横比的紧密间隔的器件结构的其它微电子器件时防止线塌陷的方法。在一些实施例中，可以使用一个或多个机械支撑结构来在紧密间隔开的装置结构之间提供横向支撑，以防止在蚀刻过程（例如，在字线蚀刻期间）紧密间隔开的装置结构的折叠。在一个示例中，在NAND快闪存储器的制造过程中，在执行高宽比字线蚀刻之前，一个或多个机械支撑结构可以就位，或者可以在字线蚀刻期间形成。在一些情况下，一个或多个机械支撑结构可以包括在执行字线蚀刻之前就位的多晶硅间电介质（IPD）层的部分。

10. 发明授权

US08987802B2 Method for using nanoparticles to make uniform discrete floating gate layer 有权
标题翻译：使用纳米粒子制造均匀离散浮栅层的方法
公开(公告)号：US08987802B2
公开(公告)日：2015-03-24
申请号：US13781066
申请日：2013-02-28
申请人： SanDisk Technologies Inc.
发明人： Donovan Lee , James Kai , Vinod Purayath , George Matamis , Steven J. Radigan
IPC分类号： H01L29/423 , H01L29/66 , H01L29/788 , H01L21/28 , H01L27/115
CPC分类号： H01L29/66825 , H01L21/28273 , H01L27/11524 , H01L29/42332 , H01L29/7881
摘要： A memory cell including a control gate located over a floating gate region. The floating gate region includes discrete doped semiconducting or conducting regions separated by an insulator and the discrete doped semiconducting or conducting regions have a generally cylindrical shape or a quasi-cylindrical shape.
摘要翻译：存储单元，包括位于浮动栅极区域上方的控制栅极。浮置栅极区域包括由绝缘体隔开的离散掺杂半导体或导电区域，并且离散掺杂的半导体或导电区域具有大致圆柱形或准圆柱形形状。

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