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1. 发明申请

US20130187203A1 FORMATION OF THE DIELECTRIC CAP LAYER FOR A REPLACEMENT GATE STRUCTURE 有权
标题翻译：形成替代盖结构的电介质层
公开(公告)号：US20130187203A1
公开(公告)日：2013-07-25
申请号：US13353708
申请日：2012-01-19
申请人： Ruilong XIE , Balasubramanian Pranatharthi Haran , David V. Horak , Su Chen Fan
发明人： Ruilong XIE , Balasubramanian Pranatharthi Haran , David V. Horak , Su Chen Fan
IPC分类号： H01L29/772 , H01L21/28
CPC分类号： H01L29/42376 , H01L21/28088 , H01L29/4966 , H01L29/66545 , H01L29/78
摘要： Gate to contact shorts are reduced by forming dielectric caps in replaced gate structures. Embodiments include forming a replaced gate structure on a substrate, the replaced gate structure including an ILD having a cavity, a first metal on a top surface of the ILD and lining the cavity, and a second metal on the first metal and filling the cavity, planarizing the first and second metals, forming an oxide on the second metal, removing the oxide, recessing the first and second metals in the cavity, forming a recess, and filling the recess with a dielectric material. Embodiments further include dielectric caps having vertical sidewalls, a trapezoidal shape, a T-shape, or a Y-shape.
摘要翻译：通过在更换的栅极结构中形成电介质盖来减少接触短路的栅极。实施例包括在衬底上形成替代的栅极结构，所述替换的栅极结构包括具有空腔的ILD，在ILD的顶表面上的第一金属和衬里的空腔，以及在第一金属上填充空腔的第二金属，平面化第一和第二金属，在第二金属上形成氧化物，去除氧化物，使空腔中的第一和第二金属凹陷，形成凹陷，并用电介质材料填充凹槽。实施例还包括具有垂直侧壁，梯形形状，T形或Y形的电介质盖。

2. 发明授权

US08772168B2 Formation of the dielectric cap layer for a replacement gate structure 有权
标题翻译：用于替代栅极结构的电介质盖层的形成
公开(公告)号：US08772168B2
公开(公告)日：2014-07-08
申请号：US13353708
申请日：2012-01-19
申请人： Ruilong Xie , Balasubramanian Pranatharthi Haran , David V. Horak , Su Chen Fan
发明人： Ruilong Xie , Balasubramanian Pranatharthi Haran , David V. Horak , Su Chen Fan
IPC分类号： H01L21/311
CPC分类号： H01L29/42376 , H01L21/28088 , H01L29/4966 , H01L29/66545 , H01L29/78
摘要： Gate to contact shorts are reduced by forming dielectric caps in replaced gate structures. Embodiments include forming a replaced gate structure on a substrate, the replaced gate structure including an ILD having a cavity, a first metal on a top surface of the ILD and lining the cavity, and a second metal on the first metal and filling the cavity, planarizing the first and second metals, forming an oxide on the second metal, removing the oxide, recessing the first and second metals in the cavity, forming a recess, and filling the recess with a dielectric material. Embodiments further include dielectric caps having vertical sidewalls, a trapezoidal shape, a T-shape, or a Y-shape.
摘要翻译：通过在更换的栅极结构中形成电介质盖来减少接触短路的栅极。实施例包括在衬底上形成替代的栅极结构，所述替换的栅极结构包括具有空腔的ILD，在ILD的顶表面上的第一金属和衬里的空腔，以及在第一金属上填充空腔的第二金属，平面化第一和第二金属，在第二金属上形成氧化物，去除氧化物，使空腔中的第一和第二金属凹陷，形成凹陷，并用电介质材料填充凹槽。实施例还包括具有垂直侧壁，梯形形状，T形或Y形的电介质盖。

3. 发明申请

US20130328111A1 RECESSING AND CAPPING OF GATE STRUCTURES WITH VARYING METAL COMPOSITIONS 有权
标题翻译：具有不同金属组成的门结构的吸附和封盖
公开(公告)号：US20130328111A1
公开(公告)日：2013-12-12
申请号：US13491857
申请日：2012-06-08
申请人： Ruilong Xie , David V. Horak , Su Chen Fan , Pranatharthiharan Haran Balasubramanian
发明人： Ruilong Xie , David V. Horak , Su Chen Fan , Pranatharthiharan Haran Balasubramanian
IPC分类号： H01L21/28 , H01L29/78
CPC分类号： H01L29/78 , H01L21/28 , H01L21/28132 , H01L21/28247 , H01L21/76897 , H01L29/401 , H01L29/4236 , H01L29/42372 , H01L29/66545 , H01L29/66553
摘要： A method for recessing and capping metal gate structures is disclosed. Embodiments include: forming a dummy gate electrode on a substrate; forming a hard mask over the dummy gate electrode; forming spacers on opposite sides of the dummy gate electrode and the hard mask; forming an interlayer dielectric (ILD) over the substrate adjacent the spacers; forming a first trench in the ILD down to the dummy gate electrode; removing the dummy gate electrode to form a second trench below the first trench; forming a metal gate structure in the first and second trenches; and forming a gate cap over the metal gate structure.
摘要翻译：公开了一种用于凹陷和封盖金属栅极结构的方法。实施例包括：在基板上形成虚拟栅电极; 在虚拟栅电极上形成硬掩模; 在虚拟栅电极和硬掩模的相对侧上形成间隔物; 在邻近所述间隔物的衬底上形成层间电介质（ILD）; 在所述ILD中形成第一沟槽至所述伪栅电极; 去除所述伪栅电极以在所述第一沟槽下方形成第二沟槽; 在所述第一和第二沟槽中形成金属栅极结构; 以及在所述金属栅极结构上形成栅极盖。

4. 发明授权

US08679909B2 Recessing and capping of gate structures with varying metal compositions 有权
标题翻译：具有不同金属成分的门结构的凹陷和封盖
公开(公告)号：US08679909B2
公开(公告)日：2014-03-25
申请号：US13491857
申请日：2012-06-08
申请人： Ruilong Xie , David V. Horak , Su Chen Fan , Pranatharthiharan Haran Balasubramanian
发明人： Ruilong Xie , David V. Horak , Su Chen Fan , Pranatharthiharan Haran Balasubramanian
IPC分类号： H01L21/338
CPC分类号： H01L29/78 , H01L21/28 , H01L21/28132 , H01L21/28247 , H01L21/76897 , H01L29/401 , H01L29/4236 , H01L29/42372 , H01L29/66545 , H01L29/66553
摘要： A method for recessing and capping metal gate structures is disclosed. Embodiments include: forming a dummy gate electrode on a substrate; forming a hard mask over the dummy gate electrode; forming spacers on opposite sides of the dummy gate electrode and the hard mask; forming an interlayer dielectric (ILD) over the substrate adjacent the spacers; forming a first trench in the ILD down to the dummy gate electrode; removing the dummy gate electrode to form a second trench below the first trench; forming a metal gate structure in the first and second trenches; and forming a gate cap over the metal gate structure.
摘要翻译：公开了一种用于凹陷和封盖金属栅极结构的方法。实施例包括：在基板上形成虚拟栅电极; 在虚拟栅电极上形成硬掩模; 在虚拟栅电极和硬掩模的相对侧上形成间隔物; 在邻近所述间隔物的衬底上形成层间电介质（ILD）; 在所述ILD中形成第一沟槽至所述伪栅电极; 去除所述伪栅电极以在所述第一沟槽下方形成第二沟槽; 在所述第一和第二沟槽中形成金属栅极结构; 以及在所述金属栅极结构上形成栅极帽。

5. 发明授权

US08853076B2 Self-aligned contacts 有权
标题翻译：自对准接触
公开(公告)号：US08853076B2
公开(公告)日：2014-10-07
申请号：US13607856
申请日：2012-09-10
申请人： Su Chen Fan , David V. Horak , Shom Ponoth , David L. Rath , Muthumanickam Sankarapandian
发明人： Su Chen Fan , David V. Horak , Shom Ponoth , David L. Rath , Muthumanickam Sankarapandian
IPC分类号： H01L21/44
CPC分类号： H01L21/28088 , H01L21/76897 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： Self-aligned contacts in a metal gate structure and methods of manufacture are disclosed herein. The method includes forming a metal gate structure having a sidewall structure. The method further includes recessing the metal gate structure and forming a masking material within the recess. The method further includes forming a borderless contact adjacent to the metal gate structure, overlapping the masking material and the sidewall structure.
摘要翻译：本文公开了金属栅极结构中的自对准触点和制造方法。该方法包括形成具有侧壁结构的金属栅极结构。该方法还包括使金属栅极结构凹陷并在凹槽内形成掩模材料。该方法还包括在金属栅极结构附近形成无边界接触，与掩模材料和侧壁结构重叠。

6. 发明申请

US20130320411A1 BORDERLESS CONTACTS FOR METAL GATES THROUGH SELECTIVE CAP DEPOSITION 审中-公开
公开(公告)号：US20130320411A1
公开(公告)日：2013-12-05
申请号：US13488581
申请日：2012-06-05
申请人： Su-Chen Fan , Balasubramanian S. Haran , David V. Horak , Shom Ponoth , Chih-Chao Yang
发明人： Su-Chen Fan , Balasubramanian S. Haran , David V. Horak , Shom Ponoth , Chih-Chao Yang
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/78 , H01L21/28247 , H01L21/76834 , H01L21/76897 , H01L29/66545
摘要： A semiconductor device including a gate structure present on a channel portion of a substrate, in which the gate structure includes at least one high-k gate dielectric layer and at least one metal gate conductor. A source region and a drain region is present on opposing sides of the channel portion of the substrate. A metal oxide gate cap is present on an upper surface of the metal gate conductor. The metal oxide composition of the metal oxide gate cap may be zirconium oxide, aluminum oxide, magnesium oxide, hafnium oxide or a combination thereof. Contacts may extend through an intralevel dielectric layer into contact with at least one of the source region and the drain region.

7. 发明授权

US08383490B2 Borderless contact for ultra-thin body devices 有权
公开(公告)号：US08383490B2
公开(公告)日：2013-02-26
申请号：US13191540
申请日：2011-07-27
申请人： Su Chen Fan , Balasubramanian S. Haran , David V. Horak
发明人： Su Chen Fan , Balasubramanian S. Haran , David V. Horak
IPC分类号： H01L21/76
CPC分类号： H01L29/0653 , H01L21/76283 , H01L21/76832 , H01L21/76834 , H01L21/76897 , H01L21/84 , H01L27/1203 , H01L29/41783 , H01L29/665 , H01L29/66628 , H01L29/7841 , H01L29/7843 , H01L29/78609
摘要： After formation of a semiconductor device on a semiconductor-on-insulator (SOI) layer, a first dielectric layer is formed over a recessed top surface of a shallow trench isolation structure. A second dielectric layer that can be etched selective to the first dielectric layer is deposited over the first dielectric layer. A contact via hole for a device component located in or on a top semiconductor layer is formed by an etch. During the etch, the second dielectric layer is removed selective to the first dielectric layer, thereby limiting overetch into the first dielectric layer. Due to the etch selectivity, a sufficient amount of the first dielectric layer is present between the bottom of the contact via hole and a bottom semiconductor layer, thus providing electrical isolation for the ETSOI device from the bottom semiconductor layer.

8. 发明申请

US20130023115A1 Borderless Contacts in Semiconductor Devices 有权
公开(公告)号：US20130023115A1
公开(公告)日：2013-01-24
申请号：US13605144
申请日：2012-09-06
申请人： Su Chen Fan , David V. Horak , Sivananda K. Kanakasabapathy
发明人： Su Chen Fan , David V. Horak , Sivananda K. Kanakasabapathy
IPC分类号： H01L21/28
CPC分类号： H01L21/28 , H01L21/76816 , H01L21/76895 , H01L21/76897 , H01L21/823475 , H01L27/0207 , H01L29/78
摘要： A method includes depositing a dummy fill material over exposed portions of a substrate and a gate stack disposed on the substrate, removing portions of the dummy fill material to expose portions of the substrate, forming a layer of spacer material over the exposed portions of the substrate, the dummy fill material and the gate stack, removing portions of the layer of spacer material to expose portions of the substrate and the dummy fill material, depositing a dielectric layer over the exposed portions of the spacer material, the substrate, and the gate stack, removing portions of the dielectric layer to expose portions of the spacer material, removing exposed portions of the spacer material to expose portions of the substrate and define at least one cavity in the dielectric layer, and depositing a conductive material in the at least one cavity.

9. 发明申请

US20140070282A1 SELF-ALIGNED CONTACTS 有权
标题翻译：自对准联系人
公开(公告)号：US20140070282A1
公开(公告)日：2014-03-13
申请号：US13607856
申请日：2012-09-10
申请人： Su Chen Fan , David V. Horak , Shom Ponoth , David L. Rath , Muthumanickam Sankarapandian
发明人： Su Chen Fan , David V. Horak , Shom Ponoth , David L. Rath , Muthumanickam Sankarapandian
IPC分类号： H01L21/28 , H01L29/78
CPC分类号： H01L21/28088 , H01L21/76897 , H01L29/4966 , H01L29/517 , H01L29/66545
摘要： Self-aligned contacts in a metal gate structure and methods of manufacture are disclosed herein. The method includes forming a metal gate structure having a sidewall structure. The method further includes recessing the metal gate structure and forming a masking material within the recess. The method further includes forming a borderless contact adjacent to the metal gate structure, overlapping the masking material and the sidewall structure.
摘要翻译：本文公开了金属栅极结构中的自对准触点和制造方法。该方法包括形成具有侧壁结构的金属栅极结构。该方法还包括使金属栅极结构凹陷并在凹槽内形成掩模材料。该方法还包括在金属栅极结构附近形成无边界接触，与掩模材料和侧壁结构重叠。

10. 发明授权

US08084311B1 Method of forming replacement metal gate with borderless contact and structure thereof 有权
标题翻译：用无边界接触形成替换金属门的方法及其结构
公开(公告)号：US08084311B1
公开(公告)日：2011-12-27
申请号：US12948246
申请日：2010-11-17
申请人： David V. Horak , Su Chen Fan , Theodorus E. Standaert
发明人： David V. Horak , Su Chen Fan , Theodorus E. Standaert
IPC分类号： H01L21/338 , H01L21/336
CPC分类号： H01L21/76897 , H01L29/66545 , Y10S438/926
摘要： Embodiments of the present invention provide a method of forming borderless contact for transistor in a replacement metal gate process. The method includes forming a gate on top of a substrate and forming spacers adjacent to sidewalls of the gate; lowering height of the spacers to expose a top portion of the sidewalls of the gate; depositing an etch-stop layer covering the spacers and the upper portion of the sidewalls of the gate; making an opening at a level that is above the spacers and in the upper portion of the sidewalls to expose the gate; and replacing material of the gate from the opening with a new gate material thereby forming a replacement gate. The method further creates a via opening in an inter-level dielectric layer surrounding the gate and spacers, with the via opening exposing the etch-stop layer; removing the etch-stop layer and fill the via opening with a metal material to form borderless contact.
摘要翻译：本发明的实施例提供了在替换金属栅极工艺中形成晶体管的无边界接触的方法。该方法包括在衬底的顶部上形成栅极并且形成与栅极的侧壁相邻的间隔物; 降低间隔件的高度以暴露门的侧壁的顶部; 沉积覆盖所述间隔物和所述栅极侧壁的上部的蚀刻停止层; 在间隔物上方和在侧壁的上部中的水平面处开口以暴露门; 并用新的栅极材料从开口替换栅极的材料，从而形成替换栅极。该方法还在围绕栅极和间隔物的层间电介质层中形成通孔，通孔开口露出蚀刻停止层; 去除蚀刻停止层并用金属材料填充通孔开口以形成无边界接触。

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