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    • 1. 发明授权
    • Programmable voltage regulator configurable for double power density and reverse blocking
    • 可编程稳压器可配置双功率密度和反向阻塞
    • US07071664B1
    • 2006-07-04
    • US11017177
    • 2004-12-20
    • Ross E. TeggatzSanmukh M. PatelRex M. TeggatzSuribhotla V. RajasekharValerian Mayega
    • Ross E. TeggatzSanmukh M. PatelRex M. TeggatzSuribhotla V. RajasekharValerian Mayega
    • G05F1/44
    • H02J7/0063
    • A programmable voltage regulator configurable for reverse blocking and double power density is disclosed herein. The programmable voltage regulator includes an error amplifier that couples to receive a reference voltage. A first NMOS pass transistor connects between an auxiliary voltage input node and the output terminal of the voltage regulator, wherein the first NMOS pass transistor is biased by the output of the error amplifier. Connected between the source of the first NMOS pass transistor and the second input of the error amplifier, a feedback network provides feedback for the voltage regulator. A second NMOS pass transistor connects between the first power supply and the auxiliary voltage input node. Furthermore, an independent node control circuit biases the second NMOS pass transistor such that in a first mode of operation, a first control signal input is operable to receive a signal for controlling the second NMOS pass transistor during reverse battery condition. In a second mode of operation, independent node control circuit includes a second control signal input that is operable to couple to the output terminal of the error amplifier while simultaneously the first power supply rail is operable to couple to the output terminal of the voltage regulator to provide double power density.
    • 本文公开了可配置用于反向阻塞和双功率密度的可编程电压调节器。 可编程电压调节器包括耦合以接收参考电压的误差放大器。 第一NMOS传输晶体管连接在辅助电压输入节点和电压调节器的输出端之间,其中第一NMOS传输晶体管被误差放大器的输出偏置。 连接在第一NMOS传输晶体管的源极和误差放大器的第二输入端之间,反馈网络为电压调节器提供反馈。 第二NMOS传输晶体管连接在第一电源和辅助电压输入节点之间。 此外,独立节点控制电路偏置第二NMOS传输晶体管,使得在第一操作模式中,第一控制信号输入可操作以在反向电池状态期间接收用于控制第二NMOS传输晶体管的信号。 在第二操作模式中,独立节点控制电路包括第二控制信号输入,其可操作以耦合到误差放大器的输出端,同时第一电源轨可操作以耦合到电压调节器的输出端, 提供双倍功率密度。
    • 7. 再颁专利
    • Preventing drain to body forward bias in a MOS transistor
    • 防止在MOS晶体管中排出体内正向偏置
    • USRE42494E1
    • 2011-06-28
    • US11800071
    • 2007-05-03
    • Ross E. Teggatz
    • Ross E. Teggatz
    • H03K5/003
    • H03K5/003
    • A voltage level shifting circuit (FIG. 4) has a plurality of PMOS transistors M1, M2, M3 connected in parallel for respectively driving a capacitive load CL with a selected different voltage level V1, V2 or V3. Transistors M1, M2, M3 are controlled so that one of them is placed in the ON condition, with the others in the OFF condition, to connect one of the voltages V1, V2 or V3 to charge the load CL. The largest voltage transistor M3 has its body connected to its source. The lower voltage transistors M1, M2 have their bodies respectively connected to switches S1, S2, which connect the bodies to the sources when the transistors are placed in the ON condition and connect the bodies to the highest voltage V3 when the transistors are placed in the OFF condition.
    • 电压电平移动电路(图4)具有并联连接的多个PMOS晶体管M1,M2,M3,分别驱动具有所选择的不同电压电平V1,V2或V3的电容性负载CL。 控制晶体管M1,M2,M3,使其中的一个被置于ON状态,其他的处于OFF状态,以连接电压V1,V2或V3中的一个来对负载CL充电。 最大的电压晶体管M3的主体连接到其源极。 低电压晶体管M1,M2的主体分别连接到开关S1,S2,开关S1,S2将晶体管置于ON状态时将主体连接到源极,并将晶体管放置在 OFF状态。
    • 9. 发明授权
    • Oscillator and method
    • 振荡器和方法
    • US06373343B1
    • 2002-04-16
    • US09649367
    • 2000-08-28
    • David J. BaldwinChristopher M. CooperJoseph A. DevoreRoss E. Teggatz
    • David J. BaldwinChristopher M. CooperJoseph A. DevoreRoss E. Teggatz
    • H03B524
    • H03K3/0231
    • An integrated circuit (10) is disclosed comprising a fundamental frequency oscillator comprising a reference node (32) whose voltage varies between a high threshold and a low threshold. The fundamental frequency oscillator is operable to generate a first output at the fundamental frequency on a first output node (36). The integrated circuit (10) also comprises a circuit (C2) coupled to the reference node. The circuit (C2) is operable to sense the voltage at the reference node (32), to determine when the voltage exceeds an intermediate threshold between the high threshold and the low threshold, and to generate a second output in response to the determination. The integrated circuit (10) also comprises logic (40) coupled to the circuit (C2) and load circuitry (50) coupled to the logic (40). The logic (40) is operable to generate an output signal at an output frequency greater than the fundamental frequency in response to the second output and the first output.
    • 公开了一种集成电路(10),其包括基频振荡器,其包括其电压在高阈值和低阈值之间变化的参考节点(32)。 基频振荡器可操作以在第一输出节点(36)上产生基频处的第一输出。 集成电路(10)还包括耦合到参考节点的电路(C2)。 电路(C2)可操作以感测参考节点(32)处的电压,以确定电压何时超过高阈值和低阈值之间的中间阈值,并响应于该确定产生第二输出。 集成电路(10)还包括耦合到电路(C2)的逻辑(40)和耦合到逻辑(40)的负载电路(50)。 逻辑(40)可操作以响应于第二输出和第一输出而以大于基频的输出频率产生输出信号。