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1. 发明授权

US09343988B2 Current mode regulator 有权
标题翻译：电流模式调节器
公开(公告)号：US09343988B2
公开(公告)日：2016-05-17
申请号：US13567039
申请日：2012-08-04
申请人： Ross E. Teggatz , David D. Briggs , Amer H. Atrash , Wayne T. Chen
发明人： Ross E. Teggatz , David D. Briggs , Amer H. Atrash , Wayne T. Chen
IPC分类号： H02M3/24 , H02M3/338 , H02M1/42 , H02M1/00
CPC分类号： H02M3/33507 , H02M1/08 , H02M1/14 , H02M1/42 , H02M1/4225 , H02M3/3387 , H02M2001/0006 , H02M2001/0009 , H02M2001/0032 , H05B33/0815 , H05B33/0851 , Y02B70/126 , Y02B70/16
摘要： Circuits, systems, and methods of current mode regulation include a primary side for receiving an input signal and a secondary for outputting an output signal. A regulator spans the primary and secondary sides in a configuration by which the input signal may be rectified and thereafter provided to the output node as an output signal. A current monitor is provided at the output node for comparing the output signal to a reference. A communication link is included for providing feedback to the primary side of the regulator for use in regulating the signal.
摘要翻译：电流模式调节的电路，系统和方法包括用于接收输入信号的初级侧和用于输出输出信号的次级。调节器跨越主要和次要侧面，通过该配置可以对输入信号进行整流，此后将其提供给输出节点作为输出信号。在输出节点处提供电流监视器，用于将输出信号与参考值进行比较。包括通信链路，用于向调节器的初级侧提供反馈信号以用于调节信号。

2. 发明授权

US06784493B2 Line self protecting multiple output power IC architecture 有权
标题翻译：线路自保护多输出电源IC架构
公开(公告)号：US06784493B2
公开(公告)日：2004-08-31
申请号：US10166956
申请日：2002-06-11
申请人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Dale Skelton , David D. Briggs , Chin-Yu Tsai
发明人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Dale Skelton , David D. Briggs , Chin-Yu Tsai
IPC分类号： H01L2900
CPC分类号： H01L29/7835 , H01L21/761 , H01L21/765 , H01L29/1045 , H01L29/1083
摘要： A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region (56) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring (16) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays (90) partitioned by at least one deep n-type region (16), which deep n-type region forms a guardring about the respective transistor array. The guardring isolates minority carriers in one transistor array from another transistor array, and facilitates the collection of the minority carriers therethrough.
摘要翻译：一种功率集成电路架构（10），其具有插入在控制电路（152）和低侧晶体管（100）之间的高侧晶体管（100），以降低所述低侧晶体管对所述控制电路的操作的影响。低侧晶体管具有高p掺杂区域（56），其被设计为减少少数载流子寿命并改善少数载流子收集以减少少数载流子扰乱控制电路。低侧晶体管具有被连接到模拟地的保护（16），由此将控制电路连接到数字地，使得将少数载流子收集到模拟地中不会干扰控制电路的操作。低侧晶体管包括由至少一个深n型区域（16）分隔的多个晶体管阵列（90），该深n型区域围绕相应的晶体管阵列形成保护。防护器将一个晶体管阵列中的少数载流子与另一晶体管阵列隔离，并且便于通过其中的少数载流子的收集。

3. 发明授权

US06710427B2 Distributed power device with dual function minority carrier reduction 有权
标题翻译：具有双功能少数载波减少的分布式功率器件
公开(公告)号：US06710427B2
公开(公告)日：2004-03-23
申请号：US10167136
申请日：2002-06-11
申请人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Chin-Yu Tsai , David D. Briggs , Dale Skelton
发明人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Chin-Yu Tsai , David D. Briggs , Dale Skelton
IPC分类号： H01L2900
CPC分类号： H01L29/1083 , H01L21/761 , H01L21/765 , H01L29/1045 , H01L29/7835
摘要： A distributed power device (100) including a plurality of tank regions (90) separated from one another by a deep n-type region (16), and having formed in each tank region a plurality of transistors (50). The plurality of transistors (50) in each tank region are interconnected to transistors in other tank regions to form a large power FET, whereby the deep n-type regions isolate the tank regions from one another. A first parasitic diode (D5) is defined from each tank region to a buried layer, and a second parasitic diode (D4) is defined between the buried layer and a substrate. The deep n-type regions distribute the first and second parasitic diodes with respect to the plurality of tank regions, preferably comprised of a P-epi tank. The deep n-type regions also distribute the resistance of an NBL layer (14) formed under the tank regions. The distributed parasitic diodes and resistance of the NBL layer advantageously provides that the parasitic diode (D4) between the NBL layer and the substrate will never be forward biased. In addition, each of the tank regions has a heavily doped p-type region (56) reducing the minority carrier lifetime to provide increased switching speed of the large power FET.
摘要翻译：一种分布式功率器件（100），包括通过深n型区域（16）彼此分离的多个槽区（90），并且在每个槽区中形成有多个晶体管（50）。每个槽区中的多个晶体管（50）与其它罐区中的晶体管相互连接以形成大功率FET，由此深n型区域将罐区彼此隔离。第一寄生二极管（D5）从每个槽区限定到埋层，并且在掩埋层和衬底之间限定第二寄生二极管（D4）。深n型区域相对于多个罐区域分布第一和第二寄生二极管，优选地由P-epi罐组成。深n型区域还分布形成在罐区域下方的NBL层（14）的电阻。分布式寄生二极管和NBL层的电阻有利地提供NBL层和衬底之间的寄生二极管（D4）将永远不会被正向偏置。此外，每个槽区具有重掺杂的p型区（56），减少了少量载流子寿命，以提供大功率FET的提高的开关速度。

4. 发明授权

US06661216B1 Apparatus and method for controlling startup of a precharged switching regulator 有权
标题翻译：用于控制预充电开关调节器启动的装置和方法
公开(公告)号：US06661216B1
公开(公告)日：2003-12-09
申请号：US10227942
申请日：2002-08-26
申请人： David A. Grant , David D. Briggs , Ayesha I. Mayhugh
发明人： David A. Grant , David D. Briggs , Ayesha I. Mayhugh
IPC分类号： G05F158
CPC分类号： H02M1/36 , Y10S323/901
摘要： An apparatus for presenting a regulated output at an output locus established at a precharge level includes: (a) an error indicator generating an error signal indicating difference between a reference signal and a sensed signal; (b) a pulse indicator coupled with the error indicator generating a pulse signal indicating difference between the error signal and a periodic signal; (c) a switching device responding to the pulse signal effecting coupling of the output locus with a first terminal or a second terminal depending upon whether the pulse signal is at a first level or a second level; and (d) a driver controller coupled with the pulse indicator and the switching device that provides a control signal to the switching device indicating at least one characteristic of the pulse signal. The switching device is operative or inoperative depending upon whether the control signal is in a first state or a second state.
摘要翻译：在预充电电平处建立的输出轨迹处呈现稳压输出的装置包括：（a）产生指示参考信号和感测信号之间差异的误差信号的误差指示器; （b）与误差指示器耦合的脉冲指示器，产生指示误差信号和周期信号之间的差异的脉冲信号; （c）根据所述脉冲信号是处于第一电平还是第二电平，响应于所述脉冲信号响应所述输出轨迹与第一端子或第二端子的耦合的开关装置; 以及（d）与所述脉冲指示器和所述开关装置耦合的驱动器控制器，其向所述开关装置提供指示所述脉冲信号的至少一个特性的控制信号。根据控制信号是处于第一状态还是第二状态，开关装置可操作或不起作用。

5. 发明授权

US06432753B1 Method of minimizing package-shift effects in integrated circuits by using a thick metallic overcoat 有权
公开(公告)号：US06432753B1
公开(公告)日：2002-08-13
申请号：US09840246
申请日：2001-04-23
申请人： Buddhika J. Abesingha , Gabriel A. Rincon-Mora , David D. Briggs , Roy Alan Hastings
发明人： Buddhika J. Abesingha , Gabriel A. Rincon-Mora , David D. Briggs , Roy Alan Hastings
IPC分类号： H01L2144
CPC分类号： H01L23/562 , H01L23/295 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： A structure and method of minimizing package-shift effects in integrated circuits is implemented by using a thick metallic overcoat applied after the deposition and patterning of the conventional insulating protective overcoat. The metallic overcoat most preferably comprises a layer of electrolytically deposited copper approximately 15 &mgr;m thick that is patterned to provide for electrically independent regions; but an unbroken area of the metallic overcoat is left over any sensitive analog circuitry, such as a bandgap reference circuit. The thick metallic coating, in addition to minimizing package-shift effects, is also useful as a low-resistance routing layer. The metallic overcoat is sufficiently thin to allow low-profile packaging. The method employs a conductive overcoat that is significantly thin compared to conventional insulating conformal overcoats.

6. 发明授权

US5537067A Signal driver circuit operable to control signal rise and fall times 失效
标题翻译：信号驱动电路可操作来控制信号上升和下降时间
公开(公告)号：US5537067A
公开(公告)日：1996-07-16
申请号：US209858
申请日：1994-03-11
申请人： Fernando D. Carvajal , David D. Briggs
发明人： Fernando D. Carvajal , David D. Briggs
IPC分类号： H03K17/16 , H03K17/687 , H03K3/00
CPC分类号： H03K17/162
摘要： A signal driver circuit (10) is provided that comprises a first inverter comprising a P-FET (14), an N-FET (16) and a resistor (18). A second inverter comprises a P-FET (20) and an N-FET (22). Resistor (18) and capacitors (24) and (26) limit the transition times of the output driving signal to control electromagnetic radiation caused by rapid transition times in the output signal. Circuit (10) is independent of the amount of capacitive load (28) driven by the circuit.
摘要翻译：提供了一种信号驱动电路（10），它包括一个包括一个P-FET（14），一个N-FET（16）和一个电阻（18）的第一个反相器。第二反相器包括P-FET（20）和N-FET（22）。电阻器（18）和电容器（24）和（26）限制输出驱动信号的转换时间，以控制由输出信号中的快速转换时间引起的电磁辐射。电路（10）与由电路驱动的容性负载（28）的数量无关。

7. 发明授权

US06750553B2 Semiconductor device which minimizes package-shift effects in integrated circuits by using a thick metallic overcoat 有权
标题翻译：半导体器件通过使用厚的金属外涂层使集成电路中的封装切换效应最小化
公开(公告)号：US06750553B2
公开(公告)日：2004-06-15
申请号：US09925983
申请日：2001-08-09
申请人： Buddhika J. Abesingha , Gabriel A. Rincon-Mora , David D. Briggs , Roy Alan Hastings
发明人： Buddhika J. Abesingha , Gabriel A. Rincon-Mora , David D. Briggs , Roy Alan Hastings
IPC分类号： H01L2328
CPC分类号： H01L23/562 , H01L23/295 , H01L2924/0002 , H01L2924/13091 , H01L2924/00
摘要： A structure and method of minimizing package-shift effects in integrated circuits is implemented by using a thick metallic overcoat applied after the deposition and patterning of the conventional insulating protective overcoat. The metallic overcoat most preferably comprises a layer of electrolytically deposited copper approximately 15 &mgr;m thick that is patterned to provide for electrically independent regions; but an unbroken area of the metallic overcoat is left over any sensitive analog circuitry, such as a bandgap reference circuit. The thick metallic coating, in addition to minimizing package-shift effects, is also useful as a low-resistance routing layer. The metallic overcoat is sufficiently thin to allow low-profile packaging. The method employs a conductive overcoat that is significantly thin compared to conventional insulating conformal overcoats.
摘要翻译：通过使用在常规绝缘保护外涂层的沉积和图案化之后施加的厚金属外涂层来实现集成电路中的封装切换效应最小化的结构和方法。金属外涂层最优选包括电解沉积的大约15μm厚的铜层，其被图案化以提供电独立的区域; 但是任何敏感的模拟电路（例如带隙参考电路）都会留下金属外涂层的未断裂区域。厚金属涂层除了最小化封装切换效应之外，也可用作低电阻布线层。金属外涂层足够薄以允许低调包装。该方法采用与常规绝缘保形外涂层相比显着薄的导电外涂层。

8. 发明授权

US06734705B2 Technique for improving propagation delay of low voltage to high voltage level shifters 有权
标题翻译：改善低压至高压电平转换器传播延迟的技术
公开(公告)号：US06734705B2
公开(公告)日：2004-05-11
申请号：US10217249
申请日：2002-08-12
申请人： Mark Pulkin , David D. Briggs
发明人： Mark Pulkin , David D. Briggs
IPC分类号： H03K19175
CPC分类号： H03K3/356113 , H03K17/063 , H03K17/102
摘要： The low voltage to high voltage level shifter has falling-edge 1-shot circuits 34 and 36 coupled to the outputs OUT and OUT_B of cross gate-connected transistors 24 and 26 and pull-down transistors 20 and 22. The falling-edge 1-shot circuits 34 and 36 output a narrow pulse when the outputs OUT and OUT_B transition from a high state to a low state. These pulses are used to set and reset a flip-flop 38. The flip flop 38 provides an output that is only dependent on the very fast fall times of the outputs OUT and OUT_B. This allows the level shifter to be designed for optimal transitional performance without the sacrifice of a potentially long propagation delay on the output nodes.
摘要翻译：低电压至高电平电平移位器具有下降沿触发电路34和36，其耦合到交叉栅极连接的晶体管24和26以及下拉晶体管20和22的输出OUT和OUT_B。下降沿1- 当输出OUT和OUT_B从高状态转变到低状态时，触发电路34和36输出窄脉冲。这些脉冲用于设置和复位触发器38.触发器38提供仅依赖于输出OUT和OUT_B的非常快的下降时间的输出。这允许将电平移位器设计成最佳的过渡性能，而不会牺牲输出节点上潜在的长传播延迟。

9. 发明授权

US06709900B2 Method of fabricating integrated system on a chip protection circuit 有权
标题翻译：在芯片保护电路上制造集成系统的方法
公开(公告)号：US06709900B2
公开(公告)日：2004-03-23
申请号：US10166964
申请日：2002-06-11
申请人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Dale Skelton , David D. Briggs , Chin-Yu Tsai
发明人： Taylor R. Efland , David A. Grant , Ramanathan Ramani , Dale Skelton , David D. Briggs , Chin-Yu Tsai
IPC分类号： H01L21332
CPC分类号： H01L29/1083 , H01L21/761 , H01L21/765 , H01L29/1045 , H01L29/7835
摘要： A power integrated circuit architecture (10) having a high side transistor (100) interposed between a control circuit (152) and a low side transistor (100) to reduce the effects of the low side transistor on the operation of the control circuit. The low side transistor has a heavily p-doped region (56) designed to reduce minority carrier lifetime and improve minority carrier collection to reduce the minority carriers from disturbing the control circuit. The low side transistor has a guardring (16) tied to an analog ground, whereby the control circuit is tied to a digital ground, such that the collection of the minority carriers into the analog ground does not disturb the operation of the control circuit. The low side transistor is comprised of multiple transistor arrays (90) partitioned by at least one deep n-type region (16), which deep n-type region forms a guardring about the respective transistor array. The guardring isolates minority carriers in one transistor array from another transistor array, and facilitates the collection of the minority carriers therethrough.
摘要翻译：一种功率集成电路架构（10），其具有插入在控制电路（152）和低侧晶体管（100）之间的高侧晶体管（100），以降低所述低侧晶体管对所述控制电路的操作的影响。低侧晶体管具有高p掺杂区域（56），其被设计为减少少数载流子寿命并改善少数载流子收集以减少少数载流子扰乱控制电路。低侧晶体管具有被连接到模拟地的保护（16），由此将控制电路连接到数字地，使得将少数载流子收集到模拟地中不会干扰控制电路的操作。低侧晶体管包括由至少一个深n型区域（16）分隔的多个晶体管阵列（90），该深n型区域围绕相应的晶体管阵列形成保护。防护器将一个晶体管阵列中的少数载流子与另一晶体管阵列隔离，并且便于通过其中的少数载流子的收集。

10. 发明授权

US6087852A Multiplexing a single output node with multiple output circuits with varying output voltages 有权
标题翻译：将具有输出电压变化的多个输出电路的单个输出节点复用
公开(公告)号：US6087852A
公开(公告)日：2000-07-11
申请号：US206871
申请日：1998-12-08
申请人： David D. Briggs , Fernando D. Carvajal , Chao-Chih Chiu
发明人： David D. Briggs , Fernando D. Carvajal , Chao-Chih Chiu
IPC分类号： H03K3/356 , H03K17/00 , H03K17/10 , H03K19/0175 , H03L5/00
CPC分类号： H03K17/102 , H03K17/005 , H03K3/356113
摘要： The invention is a multiplex circuit for outputing two or more signals of different levels to a common output pad where a first output driver (D.sub.h) is powered from a voltage rail having a higher voltage than at least one second output driver (D.sub.1) power by a lower voltage rail. An interface circuit (IFC) and level shift circuit provides two output signals base on a single input signal, one signal being equivalent to the voltage of the higher voltage (V.sub.High) and the other being based on the lower voltage (V.sub.low). PMOS device connected to the output pad has its back gate connected to V.sub.high to prevent leakage current through the PMOS device when the output to the output pad (P.sub.1) is equivalent to V.sub.High.
摘要翻译：本发明是用于向公共输出焊盘输出不同电平的两个或更多个信号的多路复用电路，其中第一输出驱动器（Dh）由具有比至少一个第二输出驱动器（D1）功率更高的电压的电压轨被供电，由一个较低的电压轨。接口电路（IFC）和电平移位电路基于单个输入信号提供两个输出信号，一个信号等于较高电压（VHigh）的电压，另一个信号基于较低电压（Vlow）。连接到输出焊盘的PMOS器件的背栅极连接到Vhigh，以防止当输出到输出焊盘（P1）的输出相当于VHigh时通过PMOS器件的漏电流。

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