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1. 发明授权

US06407457B1 Contact-bumpless chip contacting method and an electronic circuit produced by said method 有权
标题翻译：接触不平坦的芯片接触方法和通过所述方法制造的电子电路
公开(公告)号：US06407457B1
公开(公告)日：2002-06-18
申请号：US09704131
申请日：2000-11-01
申请人： Rolf Aschenbrenner , Elke Zakel , Hans-Hermann Oppermann , Ghassem Azdasht
发明人： Rolf Aschenbrenner , Elke Zakel , Hans-Hermann Oppermann , Ghassem Azdasht
IPC分类号： H01L2348
CPC分类号： H01L21/563 , H01L24/29 , H01L2224/73203 , H01L2224/83192 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01043 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/07802 , H01L2924/14 , H01L2924/3512 , H01L2924/00
摘要： An electronic contacting method for contacting a chip having a plurality of conductive contact areas, which are not provided with an additional metallization layer, a carrier substrate is provided, which has a first surface having arranged thereon a plurality of conductive connecting sections. A non-conductive adhesive layer is arranged on the first surface of the carrier substrate and subsequently, the carrier substrate is aligned with a chip to be contacted in such away that a plurality of conductive contact areas on said chip to be contacted is in alignment with the connecting sections on the first surface of said carrier substrate. Then the carrier substrate is connected to the chip to be contacted by means of the adhesive layer in such a way that the connecting sections of the carrier substrate and the contact areas of the chip abut on one another by means of pressure contact, without any intermetallic connection being established.
摘要翻译：提供一种电子接触方法，用于接触具有多个不具有附加金属化层的导电接触区域的芯片，载体基板，其具有布置有多个导电连接部分的第一表面。在载体基板的第一表面上布置非导电粘合剂层，随后将载体基板与待接触的芯片对准，使得待接触的所述芯片上的多个导电接触区域与所述载体基板的第一表面上的连接部分。然后，载体衬底通过粘合剂层连接到芯片上以使得载体衬底的连接部分和芯片的接触区域通过压力接触彼此抵接，而没有任何金属间化合物建立连接。

2. 发明授权

US6107118A Chip-contacting method requiring no contact bumps, and electronic circuit produced in this way 失效
标题翻译：不需要接触凸块的芯片接触方法和以这种方式制造的电子电路
公开(公告)号：US6107118A
公开(公告)日：2000-08-22
申请号：US11570
申请日：1998-05-18
申请人： Rolf Aschenbrenner , Elke Zakel , Hans-Hermann Oppermann , Ghassem Azdasht
发明人： Rolf Aschenbrenner , Elke Zakel , Hans-Hermann Oppermann , Ghassem Azdasht
IPC分类号： H01L21/58 , H01L21/60 , H01L21/44 , H01L21/48 , H01L21/50
CPC分类号： H01L24/83 , H01L24/29 , H01L24/81 , H01L2224/16225 , H01L2224/32225 , H01L2224/73204 , H01L2224/81801 , H01L2224/83192 , H01L2224/8385 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01043 , H01L2924/0105 , H01L2924/01079 , H01L2924/01082 , H01L2924/01327 , H01L2924/014 , H01L2924/07802 , H01L2924/14
摘要： In a contact-bumpless chip contacting method for contacting a chip having a plurality of conductive contact areas, which are not provided with an additional metallization layer, a carrier substrate is provided, which has a first surface having arranged thereon a plurality of conductive connecting sections. A non-conductive adhesive layer is arranged on the first surface of the carrier substrate and subsequently, the carrier substrate is aligned with the chip to be contacted such that a plurality of conductive contact areas on the chip to be contacted is in alignment with the connecting sections on the first surface of the carrier substrate. Then the carrier substrate is connected to the chip to be contacted by means of the adhesive layer in such a way that the connecting sections of the carrier substrate and the contact areas of the chip abut on one another by means of pressure contact, without any intermetallic connection being established.
摘要翻译： PCT No.PCT / EP96 / 03351 Sec。 371日期1998年5月18日 102（e）日期1998年5月18日PCT提交1996年7月30日PCT公布。公开号WO97 / 06557 日期：1997年2月20日在接触不牢度的芯片接触方法中，用于接触具有多个不具有附加金属化层的导电接触区域的芯片，提供载体基板，其具有布置在其上的第一表面多个导电连接部。在载体基板的第一表面上布置非导电粘合剂层，随后将载体基板与要接触的芯片对准，使得要接触的芯片上的多个导电接触区域与连接载体基板的第一表面上的部分。然后，载体衬底通过粘合剂层连接到芯片上以使得载体衬底的连接部分和芯片的接触区域通过压力接触彼此抵接，而没有任何金属间化合物建立连接。

3. 发明授权

US06284639B1 Method for forming a structured metallization on a semiconductor wafer 有权
标题翻译：在半导体晶片上形成结构化金属化的方法
公开(公告)号：US06284639B1
公开(公告)日：2001-09-04
申请号：US09367462
申请日：1999-10-25
申请人： Rolf Aschenbrenner , Ghassem Azdasht , Elke Zakel , Andreas Ostmann , Gerald Motulla
发明人： Rolf Aschenbrenner , Ghassem Azdasht , Elke Zakel , Andreas Ostmann , Gerald Motulla
IPC分类号： H01L2144
CPC分类号： H01L24/13 , H01L23/522 , H01L24/11 , H01L2224/0231 , H01L2224/0401 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/0101 , H01L2924/01013 , H01L2924/0102 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01057 , H01L2924/01061 , H01L2924/01068 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/00014
摘要： The present invention relates to a method of forming a structured metallization on a semiconductor wafer, wherein a main surface of the wafer has a passivation layer applied thereto, which is structured so as to determine at least one bond pad. Initially, a metal bump is produced on the at least one bond pad. An activated dielectric is then produced on the areas of the passivation layer on which the structured metallization is to be formed. Finally, metal is chemically deposited directly on the activated dielectric and on the metal bump in such a way that the structured metallization formed on the activated dielectric and the metal chemically deposited on the metal bump are electro-conductively joined.
摘要翻译：本发明涉及一种在半导体晶片上形成结构化金属化的方法，其中晶片的主表面具有施加到其上的钝化层，其被构造成确定至少一个焊盘。最初，在至少一个接合焊盘上产生金属凸块。然后在其上将形成结构化金属化的钝化层的区域上产生活化的电介质。最后，将金属直接化学沉积在活化的电介质和金属凸块上，使得形成在活化的电介质上的结构化金属化物和化学沉积在金属凸块上的金属被电导接合。

4. 发明授权

US5928458A Flip chip bonding with non conductive adhesive 失效
标题翻译：用非导电粘合剂倒装芯片接合
公开(公告)号：US5928458A
公开(公告)日：1999-07-27
申请号：US776936
申请日：1997-04-10
申请人： Rolf Aschenbrenner , Jorg Gwiasda , Elke Zakel , Joachim Eldring
发明人： Rolf Aschenbrenner , Jorg Gwiasda , Elke Zakel , Joachim Eldring
IPC分类号： H01L21/56 , H01L21/58 , H01L21/60 , H01L23/485 , H05K13/04
CPC分类号： H01L24/29 , H01L21/563 , H01L24/11 , H01L24/13 , H01L2224/11 , H01L2224/1134 , H01L2224/13 , H01L2224/13144 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2224/83192 , H01L2924/00013 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01029 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01087 , H01L2924/0132 , H01L2924/014 , H01L2924/07802
摘要： The invention concerns flip chip technology using non-conductive adhesives and gold ball bumps or connectors. The concept is to simultaneously attach and interconnect bare chips with gold ball bumps to organic substrates. The chip is fixed by cooling the insulative adhesive. Environmental testing has demonstrated that performance characteristics were acceptable after 1000 hours of continuous exposure to humidity, and were excellent after 1000 temperature cycles. Such stable interconnections can only be realized by the compliance of the flip chip joint. This stability, can be achieved by precise control of the bonding parameters such as temperature and pressure. This bonding technique allows quality attachment of bare chips on low cost organic substrates.
摘要翻译： PCT No.PCT / EP95 / 01388 Sec。 371日期1997年04月10日 102（e）日期1997年4月10日PCT提交1995年4月13日PCT公布。出版物WO96 / 05614 日期1996年2月22日本发明涉及使用非导电粘合剂和金球凸块或连接器的倒装芯片技术。该概念是同时将裸芯片与金球凸点连接并连接到有机基板。通过冷却绝缘胶来固定芯片。环境试验表明，连续暴露于湿度1000小时后性能特征可以接受，并且在1000个温度循环后是优异的。这种稳定的互连只能通过倒装芯片接头的顺应性来实现。这种稳定性可以通过精确控制粘合参数如温度和压力来实现。这种焊接技术允许裸芯片在低成本有机衬底上的质量附着。

5. 发明授权

US06277660B1 Method and apparatus for testing chips 有权
公开(公告)号：US06277660B1
公开(公告)日：2001-08-21
申请号：US09497437
申请日：2000-02-03
申请人： Elke Zakel , Frank Ansorge , Paul Kasulke , Andreas Ostmann , Rolf Aschenbrenner , Lothar Dietrich
发明人： Elke Zakel , Frank Ansorge , Paul Kasulke , Andreas Ostmann , Rolf Aschenbrenner , Lothar Dietrich
IPC分类号： H01L2126
CPC分类号： G01R1/07307 , H01L21/4853 , H01L2224/05568 , H01L2224/05573 , H01L2224/11003 , H01L2224/16225 , H01L2924/01322 , H01L2924/15173
摘要： Method and apparatus for the testing of substrates which are provided with a wiring structure, in particular, chips (21), in conjunction with which, by means of a solder-deposit carrier (25) which is provided with a structured, electrically conductive coating (12) with bond pads (17) for the arranging of solder deposits (28) and their transfer to correspondingly arranged bond pads (22) of a substrate (21), an electrical check of the wiring structure of the substrate (21) takes place during the transfer of the solder deposits (28).

6. 发明授权

US06211571B1 Method and apparatus for testing chips 失效
标题翻译：测试芯片的方法和设备
公开(公告)号：US06211571B1
公开(公告)日：2001-04-03
申请号：US08709344
申请日：1996-09-06
申请人： Elke Zakel , Frank Ansorge , Paul Kasulke , Andreas Ostmann , Rolf Aschenbrenner , Lothar Dietrich
发明人： Elke Zakel , Frank Ansorge , Paul Kasulke , Andreas Ostmann , Rolf Aschenbrenner , Lothar Dietrich
IPC分类号： H01L21331
CPC分类号： G01R1/07307 , H01L21/4853 , H01L2224/05568 , H01L2224/05573 , H01L2224/11003 , H01L2224/16225 , H01L2924/01322 , H01L2924/15173
摘要： Method and apparatus for the testing of substrates which are provided with a wiring structure, in particular, chips (21), in conjunction with which, by means of a solder-deposit carrier (25) which is provided with a structured, electrically conductive coating (12) with bond pads (17) for the arranging of solder deposits (28) and their transfer to correspondingly arranged bond pads (22) of a substrate (21), an electrical check of the wiring structure of the substrate (21) takes place during the transfer of the solder deposits (28).
摘要翻译：用于测试衬底的方法和装置，其具有布线结构，特别是芯片（21），借助于焊料沉积载体（25），其配备有结构化的导电涂层（12）具有用于布置焊料沉积物（28）的接合焊盘（17）和它们转移到基板（21）的相应布置的焊盘（22），基板（21）的布线结构的电检查在焊料沉积物转移过程中的位置（28）。

7. 发明授权

US06651891B1 Method for producing contactless chip cards and corresponding contactless chip card 失效
标题翻译：非接触式芯片卡及相应的非接触式芯片卡的制造方法
公开(公告)号：US06651891B1
公开(公告)日：2003-11-25
申请号：US09530339
申请日：2000-06-28
申请人： Elke Zakel , Rolf Aschenbrenner , Frank Ansorge , Paul Kasulke
发明人： Elke Zakel , Rolf Aschenbrenner , Frank Ansorge , Paul Kasulke
IPC分类号： G06K1900
CPC分类号： G06K19/0775 , G06K19/07749 , G06K19/07779 , G06K19/07783 , H01L2224/16225 , H01L2224/16227
摘要： The present invention relates to a method of producing a contactless chip card. In a first step of the method, a card body with one or a plurality of recesses on one card body side is produced from a theremoplastic material, preferably by injection moulding. Bumps being formed on the base surface of the recesses. Subsequently, conductor tracks corresponding to a coil as a conductor track pattern are impressed directly onto surface areas of the card body side including the recesses using a hot impressing technique. The conductor tracks are impressed especially also onto surface areas inside the recesses such that same extends across the bumps. One or a plurality of chips are then aligned in the recesses and contacted with the conductor tracks in the recesses which extend across the bumps. The method according to the present invention is advantageous insofar as it permits a simple production of a chip card, which requires only a few method steps and is therefore also economical. Furthermore, such a chip card is both mechanically stable and reliable, since it comprises very few individual layers and since the conductor tracks of the coil are applied directly to the card body.
摘要翻译：本发明涉及无接触芯片卡的制造方法。在该方法的第一步中，优选地通过注射成型从一个塑料材料制造具有一个卡体侧上的一个或多个凹部的卡体。凸起形成在凹部的基面上。随后，使用热压技术将对应于作为导体轨迹图案的线圈的导体轨迹直接印刷到包括凹部的卡体侧的表面区域上。导体轨迹特别地也压在凹槽内的表面区域上，使得它们延伸穿过凸块。然后将一个或多个芯片对准凹槽，并与延伸穿过凸块的凹槽中的导体轨迹相接触。根据本发明的方法是有利的，只要它允许简单地生产芯片卡，这仅需要少量的方法步骤，因此也是经济的。此外，这样的芯片卡机械稳定和可靠，因为它包括非常少的单独的层，并且由于线圈的导体轨迹直接施加到卡体。

8. 发明授权

US5989993A Method for galvanic forming of bonding pads 失效
标题翻译：焊接电镀形成方法
公开(公告)号：US5989993A
公开(公告)日：1999-11-23
申请号：US636163
申请日：1996-04-22
申请人： Elke Zakel , Rolf Aschenbrenner , Andreas Ostmann , Paul Kasulke
发明人： Elke Zakel , Rolf Aschenbrenner , Andreas Ostmann , Paul Kasulke
IPC分类号： H01L21/48 , H01L21/60 , H01L21/288
CPC分类号： H01L24/11 , H01L21/4853 , H01L2224/0401 , H01L2224/05027 , H01L2224/05568 , H01L2224/1147 , H01L2224/13023 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01032 , H01L2924/01042 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/351
摘要： Method for the preparation of electrodeposited or galvanically deposited bumps for the bonding of integrated circuits, characterized by two subsequent metal depositions, deposited without an external current source (chemical metal deposition) on a metallization 1, the first deposition being thicker than the second and the second deposition being more even or more regular throughout a large area than the first one.
摘要翻译：用于制备用于结合集成电路的电沉积或电沉积凸块的方法，其特征在于在金属化层1上沉积无外部电流源（化学金属沉积）的两个随后的金属沉积，第一沉积比第二沉积或第二沉积第二沉积在比第一沉积物大的区域中更均匀或更规则。

9. 发明授权

US5906312A Solder bump for flip chip assembly and method of its fabrication 失效
标题翻译：用于倒装芯片组装的焊接凸块及其制造方法
公开(公告)号：US5906312A
公开(公告)日：1999-05-25
申请号：US849035
申请日：1997-07-02
申请人： Elke Zakel , Rolf Aschenbrenner
发明人： Elke Zakel , Rolf Aschenbrenner
IPC分类号： H01L21/60 , H01L23/12 , H01L23/485 , H01R4/02
CPC分类号： H01L24/12 , H01L24/11 , H01L2224/1134 , H01L2224/13099 , H01L2224/13144 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/0102 , H01L2924/01033 , H01L2924/01046 , H01L2924/01076 , H01L2924/01079 , H01L2924/01082 , H01L2924/01322 , H01L2924/01327 , H01L2924/014 , H01L2924/10253 , H01L2924/19043 , H01L2924/351 , H01R4/02
摘要： The invention relates to a solder bump for flip-chip assembly and consist of a core containing a high proportion of a soft and electrically well conducting metal, particularly gold, and a diffusion barrier layer deposited on the solder bump core. As is known, the diffusion barrier layer functions to prevent intermetallic compounds between the gold of the solder bump core and the solder material, especially tin-lead solder material, which would otherwise reduce the mechanical stability of the solder connection. A pre-treatment with a cleaning solvent or in a nucleation bath has hitherto been necessary. to provide a good bond between the diffusion barrier layer, usually nickel, and the solder bump core. With the invention, this pretreatment process step is no longer necessary, since small amounts of a material are added to the solder bump core which acts as a nucleation material for the diffusion barrier layer. Such solder bump cores may, for instance, very easily and cost-efficiently be fabricated mechanically as ball bumps (with 98% of gold and 2% of palladium).
摘要翻译： PCT No.PCT / DE95 / 01590 Sec。 371日期1997年7月2日 102（e）日期1997年7月2日PCT提交1995年11月10日PCT公布。出版物WO96 / 17382 日期1996年6月6日本发明涉及一种用于倒装芯片组装的焊料凸块，其由包含高比例的导电软导电金属，特别是金的芯体和沉积在焊料凸点芯上的扩散阻挡层组成。众所周知，扩散阻挡层的作用是防止焊料凸起芯的金和焊料材料（尤其是锡铅焊料）之间的金属间化合物，否则会降低焊料连接的机械稳定性。迄今为止，用清洁溶剂或成核浴进行预处理是必要的。以在扩散阻挡层（通常为镍）和焊料凸点芯之间提供良好的结合。利用本发明，由于少量的材料被添加到作为扩散阻挡层的成核材料的焊料凸块中，因此不再需要该预处理工艺步骤。例如，这种焊料凸点芯可以非常容易且经济高效地机械地制造为球凸点（具有98％的金和2％的钯）。

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