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1. 发明授权

US06284639B1 Method for forming a structured metallization on a semiconductor wafer 有权
标题翻译：在半导体晶片上形成结构化金属化的方法
公开(公告)号：US06284639B1
公开(公告)日：2001-09-04
申请号：US09367462
申请日：1999-10-25
申请人： Rolf Aschenbrenner , Ghassem Azdasht , Elke Zakel , Andreas Ostmann , Gerald Motulla
发明人： Rolf Aschenbrenner , Ghassem Azdasht , Elke Zakel , Andreas Ostmann , Gerald Motulla
IPC分类号： H01L2144
CPC分类号： H01L24/13 , H01L23/522 , H01L24/11 , H01L2224/0231 , H01L2224/0401 , H01L2224/13099 , H01L2224/131 , H01L2924/0001 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/0101 , H01L2924/01013 , H01L2924/0102 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01057 , H01L2924/01061 , H01L2924/01068 , H01L2924/01079 , H01L2924/014 , H01L2924/14 , H01L2924/00014
摘要： The present invention relates to a method of forming a structured metallization on a semiconductor wafer, wherein a main surface of the wafer has a passivation layer applied thereto, which is structured so as to determine at least one bond pad. Initially, a metal bump is produced on the at least one bond pad. An activated dielectric is then produced on the areas of the passivation layer on which the structured metallization is to be formed. Finally, metal is chemically deposited directly on the activated dielectric and on the metal bump in such a way that the structured metallization formed on the activated dielectric and the metal chemically deposited on the metal bump are electro-conductively joined.
摘要翻译：本发明涉及一种在半导体晶片上形成结构化金属化的方法，其中晶片的主表面具有施加到其上的钝化层，其被构造成确定至少一个焊盘。最初，在至少一个接合焊盘上产生金属凸块。然后在其上将形成结构化金属化的钝化层的区域上产生活化的电介质。最后，将金属直接化学沉积在活化的电介质和金属凸块上，使得形成在活化的电介质上的结构化金属化物和化学沉积在金属凸块上的金属被电导接合。

2. 发明授权

US5989993A Method for galvanic forming of bonding pads 失效
标题翻译：焊接电镀形成方法
公开(公告)号：US5989993A
公开(公告)日：1999-11-23
申请号：US636163
申请日：1996-04-22
申请人： Elke Zakel , Rolf Aschenbrenner , Andreas Ostmann , Paul Kasulke
发明人： Elke Zakel , Rolf Aschenbrenner , Andreas Ostmann , Paul Kasulke
IPC分类号： H01L21/48 , H01L21/60 , H01L21/288
CPC分类号： H01L24/11 , H01L21/4853 , H01L2224/0401 , H01L2224/05027 , H01L2224/05568 , H01L2224/1147 , H01L2224/13023 , H01L2224/13099 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01015 , H01L2924/01029 , H01L2924/01032 , H01L2924/01042 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/351
摘要： Method for the preparation of electrodeposited or galvanically deposited bumps for the bonding of integrated circuits, characterized by two subsequent metal depositions, deposited without an external current source (chemical metal deposition) on a metallization 1, the first deposition being thicker than the second and the second deposition being more even or more regular throughout a large area than the first one.
摘要翻译：用于制备用于结合集成电路的电沉积或电沉积凸块的方法，其特征在于在金属化层1上沉积无外部电流源（化学金属沉积）的两个随后的金属沉积，第一沉积比第二沉积或第二沉积第二沉积在比第一沉积物大的区域中更均匀或更规则。

3. 发明授权

US06277660B1 Method and apparatus for testing chips 有权
公开(公告)号：US06277660B1
公开(公告)日：2001-08-21
申请号：US09497437
申请日：2000-02-03
申请人： Elke Zakel , Frank Ansorge , Paul Kasulke , Andreas Ostmann , Rolf Aschenbrenner , Lothar Dietrich
发明人： Elke Zakel , Frank Ansorge , Paul Kasulke , Andreas Ostmann , Rolf Aschenbrenner , Lothar Dietrich
IPC分类号： H01L2126
CPC分类号： G01R1/07307 , H01L21/4853 , H01L2224/05568 , H01L2224/05573 , H01L2224/11003 , H01L2224/16225 , H01L2924/01322 , H01L2924/15173
摘要： Method and apparatus for the testing of substrates which are provided with a wiring structure, in particular, chips (21), in conjunction with which, by means of a solder-deposit carrier (25) which is provided with a structured, electrically conductive coating (12) with bond pads (17) for the arranging of solder deposits (28) and their transfer to correspondingly arranged bond pads (22) of a substrate (21), an electrical check of the wiring structure of the substrate (21) takes place during the transfer of the solder deposits (28).

4. 发明授权

US06211571B1 Method and apparatus for testing chips 失效
标题翻译：测试芯片的方法和设备
公开(公告)号：US06211571B1
公开(公告)日：2001-04-03
申请号：US08709344
申请日：1996-09-06
申请人： Elke Zakel , Frank Ansorge , Paul Kasulke , Andreas Ostmann , Rolf Aschenbrenner , Lothar Dietrich
发明人： Elke Zakel , Frank Ansorge , Paul Kasulke , Andreas Ostmann , Rolf Aschenbrenner , Lothar Dietrich
IPC分类号： H01L21331
CPC分类号： G01R1/07307 , H01L21/4853 , H01L2224/05568 , H01L2224/05573 , H01L2224/11003 , H01L2224/16225 , H01L2924/01322 , H01L2924/15173
摘要： Method and apparatus for the testing of substrates which are provided with a wiring structure, in particular, chips (21), in conjunction with which, by means of a solder-deposit carrier (25) which is provided with a structured, electrically conductive coating (12) with bond pads (17) for the arranging of solder deposits (28) and their transfer to correspondingly arranged bond pads (22) of a substrate (21), an electrical check of the wiring structure of the substrate (21) takes place during the transfer of the solder deposits (28).
摘要翻译：用于测试衬底的方法和装置，其具有布线结构，特别是芯片（21），借助于焊料沉积载体（25），其配备有结构化的导电涂层（12）具有用于布置焊料沉积物（28）的接合焊盘（17）和它们转移到基板（21）的相应布置的焊盘（22），基板（21）的布线结构的电检查在焊料沉积物转移过程中的位置（28）。

5. 发明授权

US5956232A Chip support arrangement and chip support for the manufacture of a chip casing 失效
标题翻译：芯片支撑布置和芯片支架用于制造芯片外壳
公开(公告)号：US5956232A
公开(公告)日：1999-09-21
申请号：US836721
申请日：1997-06-25
申请人： Elke Zakel , David Lin , Jorg Gwiasda , Andreas Ostmann
发明人： Elke Zakel , David Lin , Jorg Gwiasda , Andreas Ostmann
IPC分类号： H01L21/60 , H01L23/12 , H01L23/498 , H05K7/02
CPC分类号： H01L23/4985 , H01L24/50
摘要： Chip-support arrangement (23) with a chip support (23) for the manufacture of a chip casing, said chip support being provided on a support foil (20) with conducting paths (21) which are connected on the front side of the support foil facing a chip (39) to contact-surface metallizations (40) of the chip and which with their free ends form a connection-surface arrangement (42) distributed in planar manner for the purpose of connection to an electronic component or a substrate, whereby the conducting paths (21) are arranged on the reverse side of the support foil (20), recesses (28) in the support foil (20) are provided in the region of the contact-surface metallizations (40), the conducting paths for forming the connection-surface arrangement (42) are covered with a perforated mask (36) and the thickness (s) of the support foil is smaller than or substantially equal to the height (h) of the contact-surface metallizations (40) on the surface of the chip.
摘要翻译： PCT No.PCT / DE95 / 01780 Sec。 371日期：1997年6月25日 102（e）1997年6月25日PCT 1995年12月7日PCT PCT。第WO96 / 21947号公报日期1997年7月18日具有用于制造芯片壳体的芯片支撑（23）的芯片支撑装置（23），所述芯片支撑件设置在支撑箔（20）上，导电路径（21）连接在所述支撑箔的前侧面向所述芯片的接触表面金属化（40）的芯片（39），并且其自由端形成以平面方式分布的连接表面布置（42），用于连接到电子组件或基板，由此导电路径（21）布置在支撑箔（20）的相反侧上，支撑箔（20）中的凹部（28）设置在接触表面金属化（40）的区域中），形成连接表面布置（42）的导电路径用穿孔掩模（36）覆盖，并且支撑箔的厚度小于或基本等于接触面布置（42）的高度（h）表面金属化（40）在芯片的表面上。

6. 发明授权

US09243341B2 Device and method for producing targeted flow and current density patterns in a chemical and/or electrolytic surface treatment 有权
标题翻译：用于在化学和/或电解表面处理中产生目标流动和电流密度模式的装置和方法
公开(公告)号：US09243341B2
公开(公告)日：2016-01-26
申请号：US13812975
申请日：2011-07-29
申请人： Lothar Dietrich , Ralf Schmidt , Andreas Ostmann
发明人： Lothar Dietrich , Ralf Schmidt , Andreas Ostmann
IPC分类号： C25D5/08 , C25D17/00 , C25D21/10 , C23C18/16 , C25D11/00 , C25D21/12 , F17D3/00 , H01L21/02 , C25D5/02
CPC分类号： C25D5/08 , C23C18/1628 , C25D5/02 , C25D11/00 , C25D17/001 , C25D17/008 , C25D21/12 , F17D3/00 , H01L21/02 , Y10T137/8593
摘要： The invention relates to a device and method for producing targeted flow and current density patterns in a chemical and/or electrolytic surface treatment. The device comprises a flow distributor body which is disposed, with the front face thereof, plane-parallel to a substrate to be processed, and which has outlet openings on the front face, through which process solution flows onto the substrate surface. The process solution flowing back from the substrate is led off through connecting passages onto the rear face of the flow distributor body. At the same time a targeted distribution of an electrical field on a conductive substrate surface is effected by a specific arrangement of said connecting passages.
摘要翻译：本发明涉及用于在化学和/或电解表面处理中产生目标流动和电流密度模式的装置和方法。该装置包括流动分配器主体，其前表面平行于待处理的基板，并且在前表面上具有出口，流程溶解在基板表面上。从基板流回的处理液通过连接通道引导到流量分配器本体的后表面。同时，通过所述连接通道的特定布置来实现导电基板表面上的电场的目标分布。

7. 发明授权

US08975116B2 Electronic assembly including an embedded electronic component 有权
标题翻译：电子组件包括嵌入式电子元件
公开(公告)号：US08975116B2
公开(公告)日：2015-03-10
申请号：US13515137
申请日：2010-12-14
申请人： Andreas Ostmann , Dionysios Manessis , Lars Böttcher , Stefan Karaszkiewicz
发明人： Andreas Ostmann , Dionysios Manessis , Lars Böttcher , Stefan Karaszkiewicz
IPC分类号： H01L21/00 , H05K1/18 , H01L21/48 , H01L21/56 , H01L23/00 , H01L23/31 , H05K3/02
CPC分类号： H05K1/188 , H01L21/4832 , H01L21/56 , H01L23/3107 , H01L24/16 , H01L24/24 , H01L24/28 , H01L24/29 , H01L24/32 , H01L24/81 , H01L24/82 , H01L24/83 , H01L2221/68377 , H01L2223/54426 , H01L2224/0401 , H01L2224/04105 , H01L2224/13144 , H01L2224/13147 , H01L2224/13155 , H01L2224/13164 , H01L2224/136 , H01L2224/2402 , H01L2224/2919 , H01L2224/81121 , H01L2224/81801 , H01L2224/83192 , H01L2224/838 , H01L2224/92 , H01L2924/00013 , H01L2924/01005 , H01L2924/01013 , H01L2924/01023 , H01L2924/01029 , H01L2924/01046 , H01L2924/0105 , H01L2924/01057 , H01L2924/01079 , H01L2924/01082 , H01L2924/0665 , H01L2924/07802 , H05K3/025 , H05K2201/0969 , H05K2201/09745 , H05K2203/0353 , H01L2224/81 , H01L2224/82 , H01L2224/83 , H01L2224/13099 , H01L2924/00 , H01L2924/014
摘要： An electronic unit is produced including at least one electronic component at least partially embedded in an insulating material. A film assembly is provided with at least one conductive layer and a carrier layer. The conductive layer includes openings in the form of holes for receiving bumps, which are connected to contact surfaces of the at least one electronic component. The at least one component is placed on the film assembly such that the bumps engage with the openings of the conductive layer. The at least one component is partially embedded from the side opposite of the bumps into a dielectric layer. The carrier layer of the film assembly is removed such that the surface of the bumps is exposed. A metallization layer is then deposited on the side of the remaining conductive layer having the exposed bumps and so as to produce conductor tracks that overlap with the bumps.
摘要翻译：制造的电子单元包括至少部分地嵌入绝缘材料中的至少一个电子部件。膜组件设置有至少一个导电层和载体层。导电层包括用于接收凸块形式的开口，凸起连接到至少一个电子部件的接触表面。将至少一个部件放置在胶片组件上，使得凸块与导电层的开口接合。所述至少一个部件从与所述凸块相对的一侧部分嵌入到电介质层中。除去膜组件的载体层，使得凸块的表面露出。然后在具有暴露的凸块的剩余导电层的侧面上沉积金属化层，以便产生与凸块重叠的导体轨迹。

8. 发明授权

US08861220B2 Method for generating an electronic system, method for generating a freeform surface having such a system, and electronic system and freeform surfaces having such a system 有权
标题翻译：用于产生电子系统的方法，用于产生具有这种系统的自由曲面的方法，以及具有这种系统的电子系统和自由曲面
公开(公告)号：US08861220B2
公开(公告)日：2014-10-14
申请号：US13381552
申请日：2010-06-29
申请人： Thomas Löher , Andreas Ostmann , Manuel Seckel
发明人： Thomas Löher , Andreas Ostmann , Manuel Seckel
IPC分类号： H01R9/00 , H05K1/18 , H05K1/02 , H05K1/03 , H05K3/28 , A41D1/00
CPC分类号： H05K1/0283 , A41D1/005 , H05K1/038 , H05K1/189 , H05K3/284 , H05K2201/09263 , Y10T29/49126 , Y10T29/49146
摘要： The invention relates to a method for generating an electronic system for application to freeform surfaces, a method for producing freeform surfaces having an electronic system, and an electronic system and a combination of a freeform surface having at least one such system. According to the invention, an elastic interconnect device having an elastic substrate and an elastic, fanned-out contact structure with contact surfaces comprised of conductor lines is generated first. Then, electronic components are mounted on the interconnect device. Finally, the interconnect device is encapsulated. If a freeform surface with an electronic system is to be generated, the electronic system produced in this way is then mounted on the previously provided freeform surface.
摘要翻译：本发明涉及一种用于产生用于自由形成表面的电子系统的方法，一种用于生产具有电子系统的自由曲面的方法，以及电子系统以及具有至少一个这样的系统的自由曲面的组合。根据本发明，首先产生具有弹性基板和具有由导体线构成的接触表面的弹性的扇形接触结构的弹性互连装置。然后，电子部件安装在互连装置上。最后，互连器件被封装。如果要产生具有电子系统的自由曲面，则以这种方式制造的电子系统然后安装在先前提供的自由曲面上。

9. 发明申请

US20120176764A1 METHOD FOR GENERATING AN ELECTRONIC SYSTEM, METHOD FOR GENERATING A FREEFORM SURFACE HAVING SUCH A SYSTEM, AND ELECTRONIC SYSTEM AND FREEFORM SURFACES HAVING SUCH A SYSTEM 有权
标题翻译：用于生成电子系统的方法，用于产生具有这样的系统的FREEFORM表面的方法，以及具有这种系统的电子系统和FREEFORM表面
公开(公告)号：US20120176764A1
公开(公告)日：2012-07-12
申请号：US13381552
申请日：2010-06-29
申请人： Thomas Löher , Andreas Ostmann , Manuel Seckel
发明人： Thomas Löher , Andreas Ostmann , Manuel Seckel
IPC分类号： H05K7/00 , H05K3/36 , H05K13/04 , H05K3/30
CPC分类号： H05K1/0283 , A41D1/005 , H05K1/038 , H05K1/189 , H05K3/284 , H05K2201/09263 , Y10T29/49126 , Y10T29/49146
摘要： The invention relates to a method for generating an electronic system for application to freeform surfaces, a method for producing freeform surfaces having an electronic system, and an electronic system and a combination of a freeform surface having at least one such system. According to the invention, an elastic interconnect device having an elastic substrate and an elastic, fanned-out contact structure with contact surfaces comprised of conductor lines is generated first. Then, electronic components are mounted on the interconnect device. Finally, the interconnect device is encapsulated. If a freeform surface with an electronic system is to be generated, the electronic system produced in this way is then mounted on the previously provided freeform surface.
摘要翻译：本发明涉及一种用于产生用于自由形成表面的电子系统的方法，一种用于生产具有电子系统的自由曲面的方法，以及电子系统以及具有至少一个这样的系统的自由曲面的组合。根据本发明，首先产生具有弹性基板和具有由导体线构成的接触表面的弹性的扇形接触结构的弹性互连装置。然后，电子部件安装在互连装置上。最后，互连器件被封装。如果要产生具有电子系统的自由曲面，则以这种方式制造的电子系统然后安装在先前提供的自由曲面上。

10. 发明申请

US20080074856A1 Electronic Subassembly 审中-公开
标题翻译：电子组件
公开(公告)号：US20080074856A1
公开(公告)日：2008-03-27
申请号：US11850970
申请日：2007-09-06
申请人： Andreas Ostmann
发明人： Andreas Ostmann
IPC分类号： H05K7/02 , H05K7/14
CPC分类号： H04B1/38 , H01L25/105 , H01L2225/1023 , H01L2225/1064 , H01L2225/107 , H01L2924/0002 , H05K1/144 , H01L2924/00
摘要： An electronic subassembly having a plurality of components which are connected to each other at least partially for signal- and data exchange, said components having contacts for the supply of electrical energy. One or more components are combined to form a separate radio module which is provided respectively with the contacts for the supply of electrical energy and which has at least one antenna. A transmitter-receiver connected to the at least one antenna is assigned to each radio module for signal- and data exchange between the components of the individual radio modules via the antennae thereof.
摘要翻译：一种具有至少部分地彼此连接以进行信号和数据交换的多个部件的电子部件，所述部件具有用于供应电能的触点。一个或多个组件被组合以形成单独的无线电模块，其分别设置有用于供应电能的触点并且具有至少一个天线。连接到至少一个天线的发射机 - 接收机被分配给每个无线电模块，用于经由其天线的各个无线电模块的组件之间的信号和数据交换。

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