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1. 发明授权

US07393614B2 Set of masks including a first mask and a second trimming mask with a semitransparent region having a transparency between 20% and 80% to control diffraction effects and obtain maximum depth of focus for the projection of structure patterns onto a semiconductor wafer 失效
$Set of masks including a first mask and a second trimming mask with a semitransparent region having a transparency between 20% and 80% to control diffraction effects and obtain maximum depth of focus for the projection of structure patterns onto a semiconductor wafer$
标题翻译：包括具有第一掩模和第二修整掩模的掩模，其具有透明度在20％至80％之间的半透明区域以控制衍射效应并获得用于将结构图案投影到半导体晶片上的最大焦深
公开(公告)号：US07393614B2
公开(公告)日：2008-07-01
申请号：US10792693
申请日：2004-03-05
申请人： Roderick Köhle , Rainer Pforr , Jörg Thiele , Wolfgang Dettmann , Markus Hofsäss , Mario Hennig
发明人： Roderick Köhle , Rainer Pforr , Jörg Thiele , Wolfgang Dettmann , Markus Hofsäss , Mario Hennig
IPC分类号： G03F1/00 , G03F1/14
CPC分类号： G03F7/70466 , G03F1/30 , G03F1/34 , G03F1/70
摘要： A set of at least two masks for the projection of structure patterns coordinated with one another by a projection system into the same photosensitive layer of a semiconductor wafer, in which the set of at least two masks includes a primary mask having an opaque structure element, which is formed at a first position on the first mask. A second mask of the set, for example a trimming mask, which is assigned to the first mask, can have a semitransparent region assigned to the structure element of the first mask. The semitransparent region can be formed at the same position on the second mask as the opaque structure element on the first mask. With the aid of the suitable choice of the transparency of the semitransparent region, it is possible to enable an undesirable resist region to be trimmed away for enlargement of a process window during exposure of the photosensitive layer on the semiconductor wafer.
摘要翻译：一组至少两个掩模，用于通过投影系统将相互配合的结构图案投影到半导体晶片的相同感光层中，其中该组至少两个掩模包括具有不透明结构元件的主掩模，其形成在第一掩模上的第一位置。该集合的第二掩码（例如，被分配给第一掩码的修剪掩模）可以具有分配给第一掩码的结构元素的半透明区域。半透明区域可以形成在第二掩模上与第一掩模上的不透明结构元件相同的位置处。借助于半透明区域的透明度的适当选择，有可能在半导体晶片上的感光层曝光期间使不期望的抗蚀剂区域被修剪以放大处理窗口。

2. 发明授权

US06680151B2 Alternating phase mask 有权
标题翻译：交替相位掩模
公开(公告)号：US06680151B2
公开(公告)日：2004-01-20
申请号：US10174646
申请日：2002-06-18
申请人： Michael Heissmeier , Markus Hofsäss , Burkhard Ludwig , Molela Moukara , Christoph Nölscher
发明人： Michael Heissmeier , Markus Hofsäss , Burkhard Ludwig , Molela Moukara , Christoph Nölscher
IPC分类号： G03F900
CPC分类号： G03F1/30
摘要： An alternating phase mask is described in which a propagation of a T phase conflict which occurs in the case of a T pattern structure is avoided by producing a phase jump at one of the 90° corners of the T pattern structure. First and second transparent area segments, which produce a mutual phase difference of 180°, are separated by a narrow slot running approximately at 45° toward the corner of the T pattern structure. The structure containing the transparent area segments, which are separated by the slot running at 45°, can also be provided at the other corner of the T structure providing a solution for each T conflict. The trimming mask for eliminating the dark line artificially produced by the 180° phase jump is a conventional mask and requires no additional coloration. Moreover, alignment errors are minimal on account of the small number of trimming openings.
摘要翻译：描述了一种交替相位掩模，其中通过在T图案结构的90°角之一处产生相位跳跃来避免在T图案结构的情况下发生的T相冲突的传播。产生180°相互相位差的第一透明区域和第二透明区域段通过大致45度向T图案结构的拐角延伸的窄槽分隔开。包含由45°运行的槽隔开的透明区域段的结构也可以设置在T结构的另一个角上，为每个T冲突提供解决方案。用于消除由180°相位跳跃人为产生的暗线的修剪掩模是常规的掩模，并且不需要额外的着色。此外，由于修剪开口的数量少，对准误差最小。

3. 发明授权

US06730463B2 Method for determining and removing phase conflicts on alternating phase masks 有权
标题翻译：用于确定和消除交替相位掩模上相位冲突的方法
公开(公告)号：US06730463B2
公开(公告)日：2004-05-04
申请号：US10126371
申请日：2002-04-19
申请人： Michael Heissmeier , Markus Hofsäss , Burkhard Ludwig , Molela Moukara , Christoph Nölscher
发明人： Michael Heissmeier , Markus Hofsäss , Burkhard Ludwig , Molela Moukara , Christoph Nölscher
IPC分类号： G03C500
CPC分类号： G03F1/30
摘要： A photoresist layer on a substrate wafer is exposed in first sections with a first exposure radiation and in second sections with a second exposure radiation that is phase-shifted by 180°. The first and second sections adjoin one another in boundary regions in which the photoresist layer is artificially not sufficiently exposed. Where a distance between these boundary regions is smaller than a photolithographically critical, least distance, the photoresist layer is exposed, at a first boundary region, with a third exposure radiation and at a second boundary region with a fourth exposure radiation phase-shifted by 180°. A trim mask provided for the process has a first translucent region and a second translucent region. The first light-transparent region and the second light-transparent region are fashioned such that the light passing through the first light-transparent region and the light passing through the second light-transparent region has a phase displacement of 180°.
摘要翻译：衬底晶片上的光致抗蚀剂层在具有第一曝光辐射的第一部分中暴露，并且在第二部分中具有相移180°的第二曝光辐射。第一和第二部分在其中光致抗蚀剂层人为地不充分暴露的边界区域彼此相邻。在这些边界区域之间的距离小于光刻临界的最小距离的情况下，光致抗蚀剂层在第一边界区域处以第三曝光辐射暴露，并且在第二边界区域处以第四曝光辐射相位偏移180° °。为该工艺提供的修剪掩模具有第一半透明区域和第二半透明区域。第一透光区域和第二透光区域被形成为使得穿过第一透光区域的光和穿过第二透光区域的光线具有180°的相位偏移。

4. 发明授权

US07484189B2 Method for searching for potential faults in a layout of an integrated circuit 失效
标题翻译：用于搜索集成电路布局中的潜在故障的方法
公开(公告)号：US07484189B2
公开(公告)日：2009-01-27
申请号：US11506201
申请日：2006-08-18
申请人： Markus Hofsäss , Eva-Maria Nash
发明人： Markus Hofsäss , Eva-Maria Nash
IPC分类号： G06F17/50 , G06F19/00 , G06F11/00 , G01R31/26 , G01R31/317 , G01R21/00
CPC分类号： G06F17/5081
摘要： A layout comprises a plurality of elemental areas which define the shape and arrangement of patterns of an integrated circuit. A method for searching for potential faults in the layout begins with dividing the layout into sections. One of a number of predetermined classes is allocated to a section by means of allocation criteria. An evaluation criterion allocated to the class which was allocated to the section is then applied to the section in order to obtain an evaluation result. Each section is then identified as potentially faulted in dependence on the evaluation result.
摘要翻译：布局包括限定集成电路的图案的形状和布置的多个元件区域。在布局中搜索潜在故障的方法首先将布局分为几个部分。通过分配标准将多个预定类别中的一个分配给部分。然后将分配给该部分的分类的评估标准应用于该部分以获得评估结果。然后根据评估结果将每个部分确定为潜在的故障。

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