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1. 发明申请

US20090185425A1 Integrated Circuit Having a Memory Cell Arrangement and Method for Reading a Memory Cell State Using a Plurality of Partial Readings 有权
标题翻译：具有存储单元布置的集成电路以及使用多个部分读数读取存储单元状态的方法
公开(公告)号：US20090185425A1
公开(公告)日：2009-07-23
申请号：US12016750
申请日：2008-01-18
申请人： Roberto Ravasio , Detlev Richter , Gert Koebernik , Girolamo Gallo , Mirko Reissmann , Ramirez Xavier Veredas
发明人： Roberto Ravasio , Detlev Richter , Gert Koebernik , Girolamo Gallo , Mirko Reissmann , Ramirez Xavier Veredas
IPC分类号： G11C16/06 , G11C7/00
CPC分类号： G11C16/26 , B82Y10/00 , G11C5/02 , G11C5/04 , G11C11/5614 , G11C11/5642 , G11C11/5664 , G11C11/5678 , G11C13/0004 , G11C13/0011 , G11C13/0014 , G11C13/004 , G11C13/025 , G11C16/0483 , G11C2013/0054 , G11C2211/5634 , G11C2213/16 , G11C2213/71
摘要： Embodiments of the invention relate generally to an integrated circuit having a memory cell arrangement and a method for reading a memory cell state using a plurality of partial readings. In an embodiment of the invention, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include at least one memory cell, the memory cell being capable of storing a plurality of memory cell states being distinguishable by a predefined number of memory cell threshold values, and a controller configured to read a memory cell state of the at least one memory cell using a number of reference levels that is higher than the predefined number of memory cell threshold values, wherein the reading includes a first partial reading using a first set of a plurality of reference levels and a second partial reading using a second set of a plurality of reference levels, wherein the second set of a plurality of reference levels includes at least one reference level which is different from the reference levels of the first set of a plurality of reference levels.
摘要翻译：本发明的实施例一般涉及具有存储单元布置的集成电路和使用多个部分读数来读取存储单元状态的方法。在本发明的实施例中，提供了具有存储单元布置的集成电路。存储单元布置可以包括至少一个存储单元，该存储单元能够存储可预定数量的存储单元阈值区分的多个存储单元状态，以及控制器，被配置为读取存储单元状态的存储单元状态至少一个存储器单元，其使用高于所述预定数量的存储单元阈值的多个参考电平，其中所述读取包括使用第一组多个参考电平的第一部分读取和使用第二组的第二部分读取多个参考电平的第二组，其中多个参考电平的第二组包括与多个参考电平的第一组的参考电平不同的至少一个参考电平。

2. 发明授权

US07800943B2 Integrated circuit having a memory cell arrangement and method for reading a memory cell state using a plurality of partial readings 有权
标题翻译：具有存储单元布置的集成电路和使用多个部分读数读取存储单元状态的方法
公开(公告)号：US07800943B2
公开(公告)日：2010-09-21
申请号：US12016750
申请日：2008-01-18
申请人： Roberto Ravasio , Detlev Richter , Gert Koebernik , Girolamo Gallo , Mirko Reissmann , Ramirez Xavier Veredas
发明人： Roberto Ravasio , Detlev Richter , Gert Koebernik , Girolamo Gallo , Mirko Reissmann , Ramirez Xavier Veredas
IPC分类号： G11C11/34 , G11C16/04 , G11C16/06
CPC分类号： G11C16/26 , B82Y10/00 , G11C5/02 , G11C5/04 , G11C11/5614 , G11C11/5642 , G11C11/5664 , G11C11/5678 , G11C13/0004 , G11C13/0011 , G11C13/0014 , G11C13/004 , G11C13/025 , G11C16/0483 , G11C2013/0054 , G11C2211/5634 , G11C2213/16 , G11C2213/71
摘要： Embodiments of the invention relate generally to an integrated circuit having a memory cell arrangement and a method for reading a memory cell state using a plurality of partial readings. In an embodiment of the invention, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include at least one memory cell, the memory cell being capable of storing a plurality of memory cell states being distinguishable by a predefined number of memory cell threshold values, and a controller configured to read a memory cell state of the at least one memory cell using a number of reference levels that is higher than the predefined number of memory cell threshold values, wherein the reading includes a first partial reading using a first set of a plurality of reference levels and a second partial reading using a second set of a plurality of reference levels, wherein the second set of a plurality of reference levels includes at least one reference level which is different from the reference levels of the first set of a plurality of reference levels.
摘要翻译：本发明的实施例一般涉及具有存储单元布置的集成电路和使用多个部分读数来读取存储单元状态的方法。在本发明的实施例中，提供了具有存储单元布置的集成电路。存储单元布置可以包括至少一个存储单元，该存储单元能够存储可预定数量的存储单元阈值区分的多个存储单元状态，以及控制器，被配置为读取存储单元状态的存储单元状态至少一个存储器单元，其使用高于所述预定数量的存储单元阈值的多个参考电平，其中所述读取包括使用第一组多个参考电平的第一部分读取和使用第二组的第二部分读取多个参考电平的第二组，其中多个参考电平的第二组包括与多个参考电平的第一组的参考电平不同的至少一个参考电平。

3. 发明授权

US07940575B2 Memory device and method providing logic connections for data transfer 有权
标题翻译：提供用于数据传输的逻辑连接的存储器件和方法
公开(公告)号：US07940575B2
公开(公告)日：2011-05-10
申请号：US12058191
申请日：2008-03-28
申请人： Roberto Ravasio , Andreas Kux , Detlev Richter , Girolamo Gallo , Josef Willer , Ramirez Xavier Veredas
发明人： Roberto Ravasio , Andreas Kux , Detlev Richter , Girolamo Gallo , Josef Willer , Ramirez Xavier Veredas
IPC分类号： G11C7/10 , G11C8/12 , G11C16/06
CPC分类号： G06F13/385 , Y02D10/14 , Y02D10/151
摘要： In an embodiment, a method for transferring data in a memory device is provided. The method may include transferring data from a first memory cell arrangement including a plurality of memory cells to a second memory cell arrangement including a plurality of memory cells via a connecting circuit arrangement coupled to the plurality of memory cell arrangements and providing a plurality of controllable connections via a plurality of connecting circuit terminals, the memory cell arrangements being connected with at least one connecting circuit terminal of the plurality of connecting circuit terminals, wherein the connecting circuit is configured to provide arbitrarily controllable signal flow connections between the plurality of connecting circuit terminals. The data are transferred via a logic connection using the controllable connections. Simultaneously, a further logic connection may be provided to a memory cell arrangement of the memory cell arrangements using the controllable connections.
摘要翻译：在一个实施例中，提供了一种用于在存储器件中传送数据的方法。该方法可以包括经由耦合到多个存储器单元布置的连接电路装置将数据从包括多个存储单元的第一存储单元布置传送到包括多个存储单元的第二存储单元布置，并提供多个可控制的连接通过多个连接电路端子，所述存储单元布置与所述多个连接电路端子中的至少一个连接电路端子连接，其中所述连接电路被配置为在所述多个连接电路端子之间提供任意可控的信号流连接。数据通过使用可控连接的逻辑连接进行传输。同时，可以使用可控制连接将另外的逻辑连接提供给存储器单元布置。

4. 发明申请

US20090244949A1 Memory Device and Method Providing Logic Connections for Data Transfer 有权
标题翻译：为数据传输提供逻辑连接的存储器件和方法
公开(公告)号：US20090244949A1
公开(公告)日：2009-10-01
申请号：US12058191
申请日：2008-03-28
申请人： Roberto Ravasio , Andreas Kux , Detlev Richter , Girolamo Gallo , Josef Willer , Ramirez Xavier Veredas
发明人： Roberto Ravasio , Andreas Kux , Detlev Richter , Girolamo Gallo , Josef Willer , Ramirez Xavier Veredas
IPC分类号： G11C5/06
CPC分类号： G06F13/385 , Y02D10/14 , Y02D10/151
摘要： In an embodiment, a method for transferring data in a memory device is provided. The method may include transferring data from a first memory cell arrangement including a plurality of memory cells to a second memory cell arrangement including a plurality of memory cells via a connecting circuit arrangement coupled to the plurality of memory cell arrangements and providing a plurality of controllable connections via a plurality of connecting circuit terminals, the memory cell arrangements being connected with at least one connecting circuit terminal of the plurality of connecting circuit terminals, wherein the connecting circuit is configured to provide arbitrarily controllable signal flow connections between the plurality of connecting circuit terminals. The data are transferred via a logic connection using the controllable connections. Simultaneously, a further logic connection may be provided to a memory cell arrangement of the memory cell arrangements using the controllable connections.
摘要翻译：在一个实施例中，提供了一种用于在存储器件中传送数据的方法。该方法可以包括经由耦合到多个存储器单元布置的连接电路装置将数据从包括多个存储单元的第一存储单元布置传送到包括多个存储单元的第二存储单元布置，并提供多个可控制的连接通过多个连接电路端子，所述存储单元布置与所述多个连接电路端子中的至少一个连接电路端子连接，其中所述连接电路被配置为在所述多个连接电路端子之间提供任意可控的信号流连接。数据通过使用可控连接的逻辑连接进行传输。同时，可以使用可控制连接将另外的逻辑连接提供给存储器单元布置。

5. 发明授权

US07221602B2 Memory system comprising a semiconductor memory 有权
标题翻译：存储器系统，包括半导体存储器
公开(公告)号：US07221602B2
公开(公告)日：2007-05-22
申请号：US10735250
申请日：2003-12-12
申请人： Rino Micheloni , Roberto Ravasio
发明人： Rino Micheloni , Roberto Ravasio
IPC分类号： G11C7/00
CPC分类号： G11C7/1051 , G06F13/4243 , G11C7/04 , G11C7/1063 , G11C7/22 , G11C16/32
摘要： A memory system comprising a semiconductor memory for storing digital data, said memory being connectable to a control device in order to receive an address signal and to make data selected through the output-available address signal. The system is characterised in that it comprises a generating circuit for activating a wait signal to be forwarded to the control device during reading operations in such a way as to indicate the non-availability of the data to be read. The generating circuit is such to deactivate the wait signal, in such a way as to indicate the availability of the data to be read, following a waiting time interval correlated with an effective access time for said memory.
摘要翻译：一种存储器系统，包括用于存储数字数据的半导体存储器，所述存储器可连接到控制装置，以便接收地址信号并且通过输出可用地址信号选择数据。该系统的特征在于，其包括用于在读取操作期间激活等待信号以发送到控制设备的发生电路，以便指示要读取的数据的不可用性。发生电路是这样的，以等待信号去激活，以便在与所述存储器的有效访问时间相关的等待时间间隔之后，指示待读取的数据的可用性。

6. 发明申请

US20070030735A1 Page buffer circuit and method for multi-level NAND programmable memories 有权
标题翻译：页面缓冲电路和多级NAND可编程存储器的方法
公开(公告)号：US20070030735A1
公开(公告)日：2007-02-08
申请号：US11495874
申请日：2006-07-28
申请人： Luca Crippa , Chiara Missiroli , Roberto Ravasio , Rino Micheloni , Angelo Bovino
发明人： Luca Crippa , Chiara Missiroli , Roberto Ravasio , Rino Micheloni , Angelo Bovino
IPC分类号： G11C16/04
CPC分类号： G11C16/12 , G11C11/5628 , G11C16/0483 , G11C2211/5621 , G11C2211/5642 , G11C2216/14
摘要： A page buffer for an electrically programmable memory including at least one read/program unit having a coupling line operatively associable with at least one of said bit lines and adapted to at least temporarily storing data bits read from or to be written into either one of the first or second memory page stored in the memory cells of a selected memory cell sets. The read/program unit includes enabling means for selectively enabling a change in programming state of a selected memory cell by causing the coupling line to take one among a program enabling potential and a program inhibition potential, conditioned to a target data value to be stored in the first group of data bits of the selected memory cell and an existing data value already stored in the second group of data bits of the selected memory cell. The enabling means includes reading means for retrieving the existing data value, means for receiving an indication of the target data value, combining means for combining the received target data value with the retrieved existing data value, thereby modifying said indication of the target data value so as to obtain a modified indication. Conditioning means in the combining means condition a potential of the coupling line based on the existing data value and the modified indication so as to cause the coupling line to take the program enabling potential or the program inhibition potential.
摘要翻译：一种用于电可编程存储器的页面缓冲器，包括至少一个读/程序单元，其具有可操作地与至少一个所述位线相关联的耦合线，并且适于至少临时存储从或写入到存储在所选存储单元组的存储单元中的第一或第二存储器页。读/程序单元包括启用装置，用于通过使耦合线在程序使能电位和程序禁止电位之间采取一种方式来有选择地启用所选择的存储单元的编程状态的改变，所选存储单元的第一组数据位和已存储在所选存储单元的第二组数据位中的现有数据值。启用装置包括用于检索现有数据值的读取装置，用于接收目标数据值的指示的装置，用于将接收的目标数据值与所检索的现有数据值组合的组合装置，从而修改目标数据值的所述指示，从而以获得修改的指示。组合装置中的调节装置基于现有数据值和修改的指示来条件耦合线的电位，以使耦合线采取程序使能电位或程序禁止电位。

7. 发明申请

US20060059406A1 Memory with embedded error correction codes 有权
公开(公告)号：US20060059406A1
公开(公告)日：2006-03-16
申请号：US11221584
申请日：2005-09-08
申请人： Rino Micheloni , Roberto Ravasio , Angelo Bovino , Vincenzo Altieri
发明人： Rino Micheloni , Roberto Ravasio , Angelo Bovino , Vincenzo Altieri
IPC分类号： G11C29/00
CPC分类号： G06F11/1048
摘要： A memory has one bus for data, addresses, and commands. A data register is coupled to the bus to store the data written to and read from the memory, a command register is coupled to the bus for receiving memory commands, and an address register is coupled to the bus to address the memory. The memory also includes an Error Correction Code circuit for calculating an ECC. The memory is configured to be responsive to external commands for controlling the operation of the ECC circuit for reading or writing of the ECC that are separate from external commands controlling reads or writes of the memory data. The memory may also include a status register that stores information regarding the passing or failing of the ECC.

8. 发明申请

US20110167318A1 READING METHOD OF A MEMORY DEVICE WITH EMBEDDED ERROR-CORRECTING CODE AND MEMORY DEVICE WITH EMBEDDED ERROR-CORRECTING CODE 有权
标题翻译：具有嵌入式错误修正代码的存储器件和带有嵌入式错误校正代码的存储器件的读取方法
公开(公告)号：US20110167318A1
公开(公告)日：2011-07-07
申请号：US13047678
申请日：2011-03-14
申请人： Alessia Marelli , Valeria Intini , Roberto Ravasio , Rino Micheloni
发明人： Alessia Marelli , Valeria Intini , Roberto Ravasio , Rino Micheloni
IPC分类号： G06F11/10
CPC分类号： G06F11/1076 , G06F11/1068 , G06F11/141 , G11B20/18
摘要： A reading method for a memory device with error-correcting encoding envisages the steps of: carrying out a first reading of a plurality of memory locations (A0, A1, . . . , ALS-1) to generate a first recovered string (S1), and performing a first decoding attempt using the first recovered string (S1). When the first decoding attempt fails, the memory locations are read at least one second time, and at least one second recovered string (S2-SN) is generated, On the basis of a comparison between the first recovered string (S1) and the second recovered string (S2-SN), a modified string (SM) is generated, in which erasures (X) are located, and at least one second decoding attempt is carried out using the modified string (SM).
摘要翻译：具有纠错编码的存储器件的读取方法设想的步骤是：执行多个存储器位置（A0，A1，...，ALS-1）的第一读取以产生第一恢复串（S1），并且使用第一恢复串执行第一解码尝试（S1）。当第一解码尝试失败时，至少读取一次存储器位置，并且生成至少一个第二恢复串（S2-SN）。基于第一恢复串（S1）与第二恢复串恢复字符串（S2-SN），生成修改字符串（SM），其中存在擦除（X），并且使用修改字符串（SM）执行至少一个第二解码尝试。

9. 发明申请

US20110167206A1 CONFIGURATION OF A MULTILEVEL FLASH MEMORY DEVICE 有权
标题翻译：多级闪存存储器件的配置
公开(公告)号：US20110167206A1
公开(公告)日：2011-07-07
申请号：US13048760
申请日：2011-03-15
申请人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
发明人： Angelo Bovino , Roberto Ravasio , Rino Micheloni
IPC分类号： G06F12/02
CPC分类号： G11C11/5621 , G11C16/20
摘要： A multi-level flash memory device allows for a faster and more effective configuration of the operating parameters of the memory device for performing the different functioning algorithms of the memory. The identification of an optimal configuration of the operating parameters of the memory device during testing is simplified by allowing for a one-time processing of configuration bits into algorithm-friendly data that are stored in an embedded ancillary random access memory at every power-on of the memory device. This is done by executing a specific power-on algorithm code stored in the ancillary read only memory of the embedded microprocessor.
摘要翻译：多级闪存设备允许更快更有效地配置存储器设备的操作参数，以执行存储器的不同功能的算法。在测试期间识别存储器件的操作参数的最佳配置通过允许将配置位一次性处理成算法友好的数据来简化，该数据存储在嵌入式辅助随机存取存储器中，每次上电时存储设备。这通过执行存储在嵌入式微处理器的辅助只读存储器中的特定加电算法代码来完成。

10. 发明授权

US07394694B2 Flash memory device with NAND architecture with reduced capacitive coupling effect 有权
标题翻译：具有NAND架构的闪存器件具有降低的电容耦合效应
公开(公告)号：US07394694B2
公开(公告)日：2008-07-01
申请号：US11445491
申请日：2006-05-31
申请人： Rino Micheloni , Roberto Ravasio , Ilaria Motta
发明人： Rino Micheloni , Roberto Ravasio , Ilaria Motta
IPC分类号： G11C11/34
CPC分类号： G11C16/3404 , G11C16/3409
摘要： A NAND flash memory device includes a matrix of memory cells each having a threshold voltage. The matrix includes an individually erasable sector and is arranged in plural rows and columns with the cells of each column arranged in plural strings of cells connected in series. The memory device includes logic that erases the cells of a selected sector, and restoring logic that restores the threshold voltage of the erased cells. The restoring logic acts in succession on each of plural blocks of the sector, each block including groups of one or more cells. The restoring logic reads each group with respect to a limit value exceeding a reading reference value, programs only each group wherein the threshold voltage of at least one cell does not reach the limit value, and stops the restoring in response to reaching the limit value by at least one set of the groups.
摘要翻译： NAND闪速存储器件包括每个具有阈值电压的存储器单元矩阵。矩阵包括单独的可擦除扇区，并且被布置成多行和列，其中每列的单元被排列成串联连接的多个单元格单元。存储器件包括擦除所选扇区的单元的逻辑，以及恢复已擦除单元的阈值电压的恢复逻辑。恢复逻辑依次作用于扇区的多个块中的每个块，每个块包括一个或多个单元的组。恢复逻辑相对于超过读取参考值的限制值读取每个组，仅对至少一个单元的阈值电压没有达到极限值的每个组进行编程，并且响应于达到极限值而停止恢复至少一组这些组。

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