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1. 发明申请

US20100274994A1 PROCESSOR OPERATING MODE FOR MITIGATING DEPENDENCY CONDITIONS 有权
标题翻译：处理器操作模式以减轻依赖性条件
公开(公告)号：US20100274994A1
公开(公告)日：2010-10-28
申请号：US12428464
申请日：2009-04-22
申请人： Robert T. Golla , Paul J. Jordan , Jama I. Barreh , Matthew B. Smittel , Yuan C. Chou , Jared C. Smolens
发明人： Robert T. Golla , Paul J. Jordan , Jama I. Barreh , Matthew B. Smittel , Yuan C. Chou , Jared C. Smolens
IPC分类号： G06F9/30
CPC分类号： G06F9/3838 , G06F9/30032 , G06F9/30109 , G06F9/30189
摘要： Various techniques for mitigating dependencies between groups of instructions are disclosed. In one embodiment, such dependencies include “evil twin” conditions, in which a first floating-point instruction has as a destination a first portion of a logical floating-point register (e.g., a single-precision write), and in which a second, subsequent floating-point instruction has as a source the first portion and a second portion of the same logical floating-point register (e.g., a double-precision read). The disclosed techniques may be applicable in a multithreaded processor implementing register renaming. In one embodiment, a processor may enter an operating mode in which detection of evil twin “producers” (e.g., single-precision writes) causes the instruction sequence to be modified to break potential dependencies. Modification of the instruction sequence may continue until one or more exit criteria are reached (e.g., committing a predetermined number of single-precision writes). This operating mode may be employed on a per-thread basis.
摘要翻译：公开了用于减轻指令组之间依赖性的各种技术。在一个实施例中，这种依赖性包括“恶双”条件，其中第一浮点指令具有作为目的地的逻辑浮点寄存器的第一部分（例如，单精度写入），并且其中第二浮点指令后续浮点指令作为源的相同逻辑浮点寄存器的第一部分和第二部分（例如，双精度读取）。所公开的技术可以适用于实现寄存器重命名的多线程处理器。在一个实施例中，处理器可以进入操作模式，在该操作模式中，恶意孪生“生产者”（例如，单精度写入）的检测导致指令序列被修改以破坏潜在依赖性。指令序列的修改可以继续，直到达到一个或多个退出标准（例如，提交预定数量的单精度写入）。该操作模式可以在每个线程的基础上使用。

2. 发明授权

US08504805B2 Processor operating mode for mitigating dependency conditions between instructions having different operand sizes 有权
标题翻译：用于缓解具有不同操作数大小的指令之间的依赖条件的处理器操作模式
公开(公告)号：US08504805B2
公开(公告)日：2013-08-06
申请号：US12428464
申请日：2009-04-22
申请人： Robert T. Golla , Paul J. Jordan , Jama I. Barreh , Matthew B. Smittle , Yuan C. Chou , Jared C. Smolens
发明人： Robert T. Golla , Paul J. Jordan , Jama I. Barreh , Matthew B. Smittle , Yuan C. Chou , Jared C. Smolens
IPC分类号： G06F7/483
CPC分类号： G06F9/3838 , G06F9/30032 , G06F9/30109 , G06F9/30189
摘要： Various techniques for mitigating dependencies between groups of instructions are disclosed. In one embodiment, such dependencies include “evil twin” conditions, in which a first floating-point instruction has as a destination a first portion of a logical floating-point register (e.g., a single-precision write), and in which a second, subsequent floating-point instruction has as a source the first portion and a second portion of the same logical floating-point register (e.g., a double-precision read). The disclosed techniques may be applicable in a multithreaded processor implementing register renaming. In one embodiment, a processor may enter an operating mode in which detection of evil twin “producers” (e.g., single-precision writes) causes the instruction sequence to be modified to break potential dependencies. Modification of the instruction sequence may continue until one or more exit criteria are reached (e.g., committing a predetermined number of single-precision writes). This operating mode may be employed on a per-thread basis.
摘要翻译：公开了用于减轻指令组之间依赖性的各种技术。在一个实施例中，这种依赖性包括“恶双”条件，其中第一浮点指令具有作为目的地的逻辑浮点寄存器的第一部分（例如，单精度写入），并且其中第二浮点指令后续浮点指令作为源的相同逻辑浮点寄存器的第一部分和第二部分（例如，双精度读取）。所公开的技术可以适用于实现寄存器重命名的多线程处理器。在一个实施例中，处理器可以进入操作模式，在该操作模式中，恶意孪生“生产者”（例如，单精度写入）的检测导致指令序列被修改以破坏潜在依赖性。指令序列的修改可以继续，直到达到一个或多个退出标准（例如，提交预定数量的单精度写入）。该操作模式可以在每个线程的基础上使用。

3. 发明授权

US08429386B2 Dynamic tag allocation in a multithreaded out-of-order processor 有权
标题翻译：多线程无序处理器中的动态标签分配
公开(公告)号：US08429386B2
公开(公告)日：2013-04-23
申请号：US12494532
申请日：2009-06-30
申请人： Paul J. Jordan , Robert T. Golla , Jama I. Barreh
发明人： Paul J. Jordan , Robert T. Golla , Jama I. Barreh
IPC分类号： G06F15/00 , G06F9/30 , G06F9/40
CPC分类号： G06F9/3851 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3885
摘要： Various techniques for dynamically allocating instruction tags and using those tags are disclosed. These techniques may apply to processors supporting out-of-order execution and to architectures that supports multiple threads. A group of instructions may be assigned a tag value from a pool of available tag values. A tag value may be usable to determine the program order of a group of instructions relative to other instructions in a thread. After the group of instructions has been (or is about to be) committed, the tag value may be freed so that it can be re-used on a second group of instructions. Tag values are dynamically allocated between threads; accordingly, a particular tag value or range of tag values is not dedicated to a particular thread.
摘要翻译：公开了用于动态分配指令标签和使用这些标签的各种技术。这些技术可能适用于支持无序执行的处理器和支持多线程的体系结构。可以从可用标签值池中分配一组指令。标签值可用于确定相对于线程中的其他指令的一组指令的程序顺序。在指示组（或将要））提交之后，可以释放标签值，以便可以在第二组指令上重新使用。标记值在线程之间动态分配; 因此，特定标签值或标签值的范围不专用于特定线程。

4. 发明授权

US07343474B1 Minimal address state in a fine grain multithreaded processor 有权
标题翻译：细粒度多线程处理器中的最小地址状态
公开(公告)号：US07343474B1
公开(公告)日：2008-03-11
申请号：US10881616
申请日：2004-06-30
申请人： Paul J. Jordan , Robert T. Golla , Jama I. Barreh
发明人： Paul J. Jordan , Robert T. Golla , Jama I. Barreh
IPC分类号： G06F9/30
CPC分类号： G06F9/3867 , G06F9/3802 , G06F9/3851
摘要： In one embodiment, a processor comprises a plurality of pipeline stages and a first circuit operable at a first pipeline stage of the plurality of pipeline stages. The first circuit is configured to maintain a plurality of program counters (PCs), each of which corresponds to one of a plurality of threads that the processor is configured to have concurrently in process with respect to the plurality of pipeline stages. The first circuit is configured to provide a first PC to a second pipeline stage of the plurality of pipeline stages. The first PC is derived from one of the plurality of PCs that corresponds to a first thread of the plurality of threads, and a first instruction entering the second pipeline stage is from the first thread.
摘要翻译：在一个实施例中，处理器包括多个流水线级和在多个流水线级的第一流水线级可工作的第一电路。第一电路被配置为维持多个程序计数器（PC），每个程序计数器（PC）对应于处理器被配置为相对于多个流水线级并行处理的多个线程中的一个。第一电路被配置为向多个流水线级的第二流水线级提供第一PC。第一个PC是从与多个线程中的第一个线程相对应的多个PC中的一个导出的，并且进入第二流水线级的第一指令来自第一线程。

5. 发明授权

US07861063B1 Delay slot handling in a processor 有权
标题翻译：在处理器中延迟插槽处理
公开(公告)号：US07861063B1
公开(公告)日：2010-12-28
申请号：US10881217
申请日：2004-06-30
申请人： Robert T. Golla , Paul J. Jordan , Jama I. Barreh
发明人： Robert T. Golla , Paul J. Jordan , Jama I. Barreh
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/30072 , G06F9/3851 , G06F9/3857 , G06F9/3859 , G06F9/3861
摘要： In one embodiment, a processor comprises a fetch unit and a pick unit. The fetch unit is configured to fetch instructions for execution by the processor. The pick unit is configured to schedule instructions fetched by the fetch unit for execution in the processor. The pick unit is configured to inhibit scheduling a delayed control transfer instruction (DCTI) until a delay slot instruction of the DCTI is available for scheduling. For example, in some embodiments, the pick unit may inhibit scheduling until the delay slot instruction is written to an instruction buffer, until the delay slot instruction is fetched, etc.
摘要翻译：在一个实施例中，处理器包括取出单元和拾取单元。提取单元被配置为提取处理器执行的指令。拾取单元被配置为调度由提取单元获取的在处理器中执行的指令。拾取单元被配置为禁止调度延迟的控制传送指令（DCTI），直到DCTI的延迟时隙指令可用于调度。例如，在一些实施例中，拾取单元可以禁止调度，直到延迟时隙指令被写入指令缓冲器，直到延迟时隙指令被取出等。

6. 发明申请

US20100333098A1 DYNAMIC TAG ALLOCATION IN A MULTITHREADED OUT-OF-ORDER PROCESSOR 有权
标题翻译：动态标签分配在一个多边进阶的处理器
公开(公告)号：US20100333098A1
公开(公告)日：2010-12-30
申请号：US12494532
申请日：2009-06-30
申请人： Paul J. Jordan , Robert T. Golla , Jama I. Barreh
发明人： Paul J. Jordan , Robert T. Golla , Jama I. Barreh
IPC分类号： G06F9/46 , G06F12/08
CPC分类号： G06F9/3851 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3885
摘要： Various techniques for dynamically allocating instruction tags and using those tags are disclosed. These techniques may apply to processors supporting out-of-order execution and to architectures that supports multiple threads. A group of instructions may be assigned a tag value from a pool of available tag values. A tag value may be usable to determine the program order of a group of instructions relative to other instructions in a thread. After the group of instructions has been (or is about to be) committed, the tag value may be freed so that it can be re-used on a second group of instructions. Tag values are dynamically allocated between threads; accordingly, a particular tag value or range of tag values is not dedicated to a particular thread.
摘要翻译：公开了用于动态分配指令标签和使用这些标签的各种技术。这些技术可能适用于支持无序执行的处理器和支持多线程的体系结构。可以从可用标签值池中分配一组指令。标签值可用于确定相对于线程中的其他指令的一组指令的程序顺序。在指示组（或将要））提交之后，可以释放标签值，以便可以在第二组指令上重新使用。标记值在线程之间动态分配; 因此，特定标签值或标签值的范围不专用于特定线程。

7. 发明申请

US20130297910A1 MITIGATION OF THREAD HOGS ON A THREADED PROCESSOR USING A GENERAL LOAD/STORE TIMEOUT COUNTER 审中-公开
标题翻译：使用一般负载/存储超时计数器在螺纹加工器上减少螺纹头
公开(公告)号：US20130297910A1
公开(公告)日：2013-11-07
申请号：US13463319
申请日：2012-05-03
申请人： Jared C. Smolens , Robert T. Golla , Mark A. Luttrell , Paul J. Jordan
发明人： Jared C. Smolens , Robert T. Golla , Mark A. Luttrell , Paul J. Jordan
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/3861 , G06F9/3851 , G06F9/5016 , G06F2209/507
摘要： Systems and methods for efficient thread arbitration in a threaded processor with dynamic resource allocation. A processor includes a resource shared by multiple threads. The resource includes entries which may be allocated for use by any thread. Control logic detects long latency instructions. Long latency instructions have a latency greater than a given threshold. One example is a load instruction that has a read-after-write (RAW) data dependency on a store instruction that misses a last-level data cache. The long latency instruction or an immediately younger instruction is selected for replay for an associated thread. A pipeline flush and replay for the associated thread begins with the selected instruction. Instructions younger than the long latency instruction are held at a given pipeline stage until the long latency instruction completes. During replay, this hold prevents resources from being allocated to the associated thread while the long latency instruction is being serviced.
摘要翻译：在具有动态资源分配的线程处理器中有效的线程仲裁的系统和方法。处理器包括由多个线程共享的资源。资源包括可以分配给任何线程使用的条目。控制逻辑检测长延迟指令。长延迟指令的延迟大于给定的阈值。一个示例是对于丢失最后一级数据高速缓存的存储指令具有对后读写（RAW）数据依赖性的加载指令。选择长延迟指令或立即更年轻的指令用于相关线程的重放。相关线程的流水线冲洗和重播将以所选指令开始。比长延迟指令更年轻的指令保持在给定的流水线阶段，直到长延迟指令完成。在重放期间，这种保持可以防止资源被分配给相关联的线程，而长时间延迟指令被服务。

8. 发明申请

US20100169611A1 BRANCH MISPREDICTION RECOVERY MECHANISM FOR MICROPROCESSORS 有权
标题翻译：用于微处理器的分支机构故障恢复机制
公开(公告)号：US20100169611A1
公开(公告)日：2010-07-01
申请号：US12346349
申请日：2008-12-30
申请人： Yuan C. Chou , Robert T. Golla , Mark A. Luttrell , Paul J. Jordan , Manish Shah
发明人： Yuan C. Chou , Robert T. Golla , Mark A. Luttrell , Paul J. Jordan , Manish Shah
IPC分类号： G06F9/312
CPC分类号： G06F9/3844 , G06F9/3863
摘要： A system and method for reducing branch misprediction penalty. In response to detecting a mispredicted branch instruction, circuitry within a microprocessor identifies a predetermined condition prior to retirement of the branch instruction. Upon identifying this condition, the entire corresponding pipeline is flushed prior to retirement of the branch instruction, and instruction fetch is started at a corresponding address of an oldest instruction in the pipeline immediately prior to the flushing of the pipeline. The correct outcome is stored prior to the pipeline flush. In order to distinguish the mispredicted branch from other instructions, identification information may be stored alongside the correct outcome. One example of the predetermined condition being satisfied is in response to a timer reaching a predetermined threshold value, wherein the timer begins incrementing in response to the mispredicted branch detection and resets at retirement of the mispredicted branch.
摘要翻译：减少分支误判处罚的系统和方法。响应于检测到错误的分支指令，微处理器内的电路在退出分支指令之前识别预定的条件。在识别该条件之后，在分支指令退出之前将整个对应的流水线冲洗，并且在冲洗流水线之前在管道中的最早的指令的对应地址开始指令提取。在管道冲洗之前存储正确的结果。为了将错误预测的分支与其他指令区分开，识别信息可以与正确的结果一起存储。满足预定条件的一个示例是响应于定时器达到预定阈值，其中定时器响应于错误预测的分支检测而开始递增，并且在退出预测分支时重置。

9. 发明授权

US08099586B2 Branch misprediction recovery mechanism for microprocessors 有权
标题翻译：微处理器分支错误预测恢复机制
公开(公告)号：US08099586B2
公开(公告)日：2012-01-17
申请号：US12346349
申请日：2008-12-30
申请人： Yuan C. Chou , Robert T. Golla , Mark A. Luttrell , Paul J. Jordan , Manish Shah
发明人： Yuan C. Chou , Robert T. Golla , Mark A. Luttrell , Paul J. Jordan , Manish Shah
IPC分类号： G06F9/00
CPC分类号： G06F9/3844 , G06F9/3863
摘要： A system and method for reducing branch misprediction penalty. In response to detecting a mispredicted branch instruction, circuitry within a microprocessor identifies a predetermined condition prior to retirement of the branch instruction. Upon identifying this condition, the entire corresponding pipeline is flushed prior to retirement of the branch instruction, and instruction fetch is started at a corresponding address of an oldest instruction in the pipeline immediately prior to the flushing of the pipeline. The correct outcome is stored prior to the pipeline flush. In order to distinguish the mispredicted branch from other instructions, identification information may be stored alongside the correct outcome. One example of the predetermined condition being satisfied is in response to a timer reaching a predetermined threshold value, wherein the timer begins incrementing in response to the mispredicted branch detection and resets at retirement of the mispredicted branch.
摘要翻译：减少分支误判处罚的系统和方法。响应于检测到错误的分支指令，微处理器内的电路在退出分支指令之前识别预定的条件。在识别该条件之后，在分支指令退出之前将整个对应的流水线冲洗，并且在冲洗流水线之前在管道中的最早的指令的对应地址开始指令提取。在管道冲洗之前存储正确的结果。为了将错误预测的分支与其他指令区分开，识别信息可以与正确的结果一起存储。满足预定条件的一个示例是响应于定时器达到预定阈值，其中定时器响应于错误预测的分支检测而开始递增，并且在退出预测分支时重置。

10. 发明申请

US20110296142A1 PROCESSOR AND METHOD PROVIDING INSTRUCTION SUPPORT FOR INSTRUCTIONS THAT UTILIZE MULTIPLE REGISTER WINDOWS 有权
标题翻译：处理器和方法提供指令支持使用多个寄存器窗口的指令
公开(公告)号：US20110296142A1
公开(公告)日：2011-12-01
申请号：US12790074
申请日：2010-05-28
申请人： Christopher H. Olson , Paul J. Jordan , Jama I. Barreh
发明人： Christopher H. Olson , Paul J. Jordan , Jama I. Barreh
IPC分类号： G06F9/30 , G06F9/315 , G06F9/312
CPC分类号： G06F9/30127 , G06F7/5324 , G06F9/30032 , G06F9/30043 , G06F9/30145 , G06F9/3824 , G06F9/384 , G06F9/3844 , G06F9/3851 , G06F9/3867 , G06F21/556
摘要： A processor including instruction support for large-operand instructions that use multiple register windows may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may also include an instruction execution unit that, during operation, receives instructions for execution from the instruction fetch unit and executes a large-operand instruction defined within the ISA, where execution of the large-operand instruction is dependent upon a plurality of registers arranged within a plurality of register windows. The processor may further include control circuitry (which may be included within the fetch unit, the execution unit, or elsewhere within the processor) that determines whether one or more of the register windows depended upon by the large-operand instruction are not present. In response to determining that one or more of these register windows are not present, the control circuitry causes them to be restored.
摘要翻译：包括对使用多个寄存器窗口的大操作数指令的指令支持的处理器可以从定义的指令集架构（ISA）发出用于执行编程器可选择指令的指令。处理器还可以包括指令执行单元，其在操作期间从指令获取单元接收执行指令，并执行在ISA内定义的大操作数指令，其中大操作数指令的执行取决于多个寄存器布置在多个寄存器窗口内。处理器还可以包括控制电路（其可以包括在提取单元，执行单元或处理器内的其他地方），其确定不存在大操作数指令所依赖的寄存器窗口中的一个或多个。响应于确定这些寄存器窗口中的一个或多个不存在，控制电路使它们被恢复。

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