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1. 发明申请

US20110296142A1 PROCESSOR AND METHOD PROVIDING INSTRUCTION SUPPORT FOR INSTRUCTIONS THAT UTILIZE MULTIPLE REGISTER WINDOWS 有权
标题翻译：处理器和方法提供指令支持使用多个寄存器窗口的指令
公开(公告)号：US20110296142A1
公开(公告)日：2011-12-01
申请号：US12790074
申请日：2010-05-28
申请人： Christopher H. Olson , Paul J. Jordan , Jama I. Barreh
发明人： Christopher H. Olson , Paul J. Jordan , Jama I. Barreh
IPC分类号： G06F9/30 , G06F9/315 , G06F9/312
CPC分类号： G06F9/30127 , G06F7/5324 , G06F9/30032 , G06F9/30043 , G06F9/30145 , G06F9/3824 , G06F9/384 , G06F9/3844 , G06F9/3851 , G06F9/3867 , G06F21/556
摘要： A processor including instruction support for large-operand instructions that use multiple register windows may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may also include an instruction execution unit that, during operation, receives instructions for execution from the instruction fetch unit and executes a large-operand instruction defined within the ISA, where execution of the large-operand instruction is dependent upon a plurality of registers arranged within a plurality of register windows. The processor may further include control circuitry (which may be included within the fetch unit, the execution unit, or elsewhere within the processor) that determines whether one or more of the register windows depended upon by the large-operand instruction are not present. In response to determining that one or more of these register windows are not present, the control circuitry causes them to be restored.
摘要翻译：包括对使用多个寄存器窗口的大操作数指令的指令支持的处理器可以从定义的指令集架构（ISA）发出用于执行编程器可选择指令的指令。处理器还可以包括指令执行单元，其在操作期间从指令获取单元接收执行指令，并执行在ISA内定义的大操作数指令，其中大操作数指令的执行取决于多个寄存器布置在多个寄存器窗口内。处理器还可以包括控制电路（其可以包括在提取单元，执行单元或处理器内的其他地方），其确定不存在大操作数指令所依赖的寄存器窗口中的一个或多个。响应于确定这些寄存器窗口中的一个或多个不存在，控制电路使它们被恢复。

2. 发明授权

US08555038B2 Processor and method providing instruction support for instructions that utilize multiple register windows 有权
标题翻译：处理器和方法为使用多个寄存器窗口的指令提供指令支持
公开(公告)号：US08555038B2
公开(公告)日：2013-10-08
申请号：US12790074
申请日：2010-05-28
申请人： Christopher H. Olson , Paul J. Jordan , Jama I. Barreh
发明人： Christopher H. Olson , Paul J. Jordan , Jama I. Barreh
IPC分类号： G06F9/00
CPC分类号： G06F9/30127 , G06F7/5324 , G06F9/30032 , G06F9/30043 , G06F9/30145 , G06F9/3824 , G06F9/384 , G06F9/3844 , G06F9/3851 , G06F9/3867 , G06F21/556
摘要： A processor including instruction support for large-operand instructions that use multiple register windows may issue, for execution, programmer-selectable instructions from a defined instruction set architecture (ISA). The processor may also include an instruction execution unit that, during operation, receives instructions for execution from the instruction fetch unit and executes a large-operand instruction defined within the ISA, where execution of the large-operand instruction is dependent upon a plurality of registers arranged within a plurality of register windows. The processor may further include control circuitry (which may be included within the fetch unit, the execution unit, or elsewhere within the processor) that determines whether one or more of the register windows depended upon by the large-operand instruction are not present. In response to determining that one or more of these register windows are not present, the control circuitry causes them to be restored.
摘要翻译：包括对使用多个寄存器窗口的大操作数指令的指令支持的处理器可以从定义的指令集架构（ISA）发出用于执行编程器可选择指令的指令。处理器还可以包括指令执行单元，其在操作期间从指令获取单元接收执行指令，并执行在ISA内定义的大操作数指令，其中大操作数指令的执行取决于多个寄存器布置在多个寄存器窗口内。处理器还可以包括控制电路（其可以包括在提取单元，执行单元或处理器内的其他地方），其确定不存在大操作数指令所依赖的寄存器窗口中的一个或多个。响应于确定这些寄存器窗口中的一个或多个不存在，控制电路使它们被恢复。

3. 发明授权

US08429386B2 Dynamic tag allocation in a multithreaded out-of-order processor 有权
标题翻译：多线程无序处理器中的动态标签分配
公开(公告)号：US08429386B2
公开(公告)日：2013-04-23
申请号：US12494532
申请日：2009-06-30
申请人： Paul J. Jordan , Robert T. Golla , Jama I. Barreh
发明人： Paul J. Jordan , Robert T. Golla , Jama I. Barreh
IPC分类号： G06F15/00 , G06F9/30 , G06F9/40
CPC分类号： G06F9/3851 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3885
摘要： Various techniques for dynamically allocating instruction tags and using those tags are disclosed. These techniques may apply to processors supporting out-of-order execution and to architectures that supports multiple threads. A group of instructions may be assigned a tag value from a pool of available tag values. A tag value may be usable to determine the program order of a group of instructions relative to other instructions in a thread. After the group of instructions has been (or is about to be) committed, the tag value may be freed so that it can be re-used on a second group of instructions. Tag values are dynamically allocated between threads; accordingly, a particular tag value or range of tag values is not dedicated to a particular thread.
摘要翻译：公开了用于动态分配指令标签和使用这些标签的各种技术。这些技术可能适用于支持无序执行的处理器和支持多线程的体系结构。可以从可用标签值池中分配一组指令。标签值可用于确定相对于线程中的其他指令的一组指令的程序顺序。在指示组（或将要））提交之后，可以释放标签值，以便可以在第二组指令上重新使用。标记值在线程之间动态分配; 因此，特定标签值或标签值的范围不专用于特定线程。

4. 发明申请

US20130138888A1 STORING A TARGET ADDRESS OF A CONTROL TRANSFER INSTRUCTION IN AN INSTRUCTION FIELD 审中-公开
标题翻译：在指挥领域存储控制传输指令的目标地址
公开(公告)号：US20130138888A1
公开(公告)日：2013-05-30
申请号：US13307850
申请日：2011-11-30
申请人： Jama I. Barreh , Manish K. Shah , Christopher H. Olson
发明人： Jama I. Barreh , Manish K. Shah , Christopher H. Olson
IPC分类号： G06F12/08
CPC分类号： G06F9/324 , G06F9/382 , G06F12/0862 , Y02D10/13
摘要： A control transfer instruction (CTI), such as a branch, jump, etc., may have an offset value for a control transfer that is to be performed. The offset value may be usable to compute a target address for the CTI (e.g., the address of a next instruction to be executed for a thread or instruction stream). The offset may be specified relative to a program counter. In response to detecting a specified offset value, the CTI may be modified to include at least a portion of a computed target address. Information indicating this modification has been performed may be stored, for example, in a pre-decode bit. In some cases, CTI modification may be performed only when a target address is a “near” target, rather than a “far” target. Modifying CTIs as described herein may eliminate redundant address calculations and produce a savings of power and/or time in some embodiments.
摘要翻译：诸如分支，跳转等的控制传送指令（CTI）可以具有要执行的控制传输的偏移值。偏移值可用于计算CTI的目标地址（例如，针对线程或指令流执行的下一条指令的地址）。可以相对于程序计数器指定偏移量。响应于检测到指定的偏移值，可以修改CTI以包括计算的目标地址的至少一部分。已经执行了表示该修改的信息可以被存储在例如预解码位中。在某些情况下，仅当目标地址是“近”目标而不是“远”目标时才可以执行CTI修改。如本文所述的修改CTI可以在一些实施例中消除冗余地址计算并产生功率和/或时间的节省。

5. 发明授权

US07343474B1 Minimal address state in a fine grain multithreaded processor 有权
标题翻译：细粒度多线程处理器中的最小地址状态
公开(公告)号：US07343474B1
公开(公告)日：2008-03-11
申请号：US10881616
申请日：2004-06-30
申请人： Paul J. Jordan , Robert T. Golla , Jama I. Barreh
发明人： Paul J. Jordan , Robert T. Golla , Jama I. Barreh
IPC分类号： G06F9/30
CPC分类号： G06F9/3867 , G06F9/3802 , G06F9/3851
摘要： In one embodiment, a processor comprises a plurality of pipeline stages and a first circuit operable at a first pipeline stage of the plurality of pipeline stages. The first circuit is configured to maintain a plurality of program counters (PCs), each of which corresponds to one of a plurality of threads that the processor is configured to have concurrently in process with respect to the plurality of pipeline stages. The first circuit is configured to provide a first PC to a second pipeline stage of the plurality of pipeline stages. The first PC is derived from one of the plurality of PCs that corresponds to a first thread of the plurality of threads, and a first instruction entering the second pipeline stage is from the first thread.
摘要翻译：在一个实施例中，处理器包括多个流水线级和在多个流水线级的第一流水线级可工作的第一电路。第一电路被配置为维持多个程序计数器（PC），每个程序计数器（PC）对应于处理器被配置为相对于多个流水线级并行处理的多个线程中的一个。第一电路被配置为向多个流水线级的第二流水线级提供第一PC。第一个PC是从与多个线程中的第一个线程相对应的多个PC中的一个导出的，并且进入第二流水线级的第一指令来自第一线程。

6. 发明授权

US07861063B1 Delay slot handling in a processor 有权
标题翻译：在处理器中延迟插槽处理
公开(公告)号：US07861063B1
公开(公告)日：2010-12-28
申请号：US10881217
申请日：2004-06-30
申请人： Robert T. Golla , Paul J. Jordan , Jama I. Barreh
发明人： Robert T. Golla , Paul J. Jordan , Jama I. Barreh
IPC分类号： G06F9/30
CPC分类号： G06F9/3842 , G06F9/30072 , G06F9/3851 , G06F9/3857 , G06F9/3859 , G06F9/3861
摘要： In one embodiment, a processor comprises a fetch unit and a pick unit. The fetch unit is configured to fetch instructions for execution by the processor. The pick unit is configured to schedule instructions fetched by the fetch unit for execution in the processor. The pick unit is configured to inhibit scheduling a delayed control transfer instruction (DCTI) until a delay slot instruction of the DCTI is available for scheduling. For example, in some embodiments, the pick unit may inhibit scheduling until the delay slot instruction is written to an instruction buffer, until the delay slot instruction is fetched, etc.
摘要翻译：在一个实施例中，处理器包括取出单元和拾取单元。提取单元被配置为提取处理器执行的指令。拾取单元被配置为调度由提取单元获取的在处理器中执行的指令。拾取单元被配置为禁止调度延迟的控制传送指令（DCTI），直到DCTI的延迟时隙指令可用于调度。例如，在一些实施例中，拾取单元可以禁止调度，直到延迟时隙指令被写入指令缓冲器，直到延迟时隙指令被取出等。

7. 发明申请

US20100274994A1 PROCESSOR OPERATING MODE FOR MITIGATING DEPENDENCY CONDITIONS 有权
标题翻译：处理器操作模式以减轻依赖性条件
公开(公告)号：US20100274994A1
公开(公告)日：2010-10-28
申请号：US12428464
申请日：2009-04-22
申请人： Robert T. Golla , Paul J. Jordan , Jama I. Barreh , Matthew B. Smittel , Yuan C. Chou , Jared C. Smolens
发明人： Robert T. Golla , Paul J. Jordan , Jama I. Barreh , Matthew B. Smittel , Yuan C. Chou , Jared C. Smolens
IPC分类号： G06F9/30
CPC分类号： G06F9/3838 , G06F9/30032 , G06F9/30109 , G06F9/30189
摘要： Various techniques for mitigating dependencies between groups of instructions are disclosed. In one embodiment, such dependencies include “evil twin” conditions, in which a first floating-point instruction has as a destination a first portion of a logical floating-point register (e.g., a single-precision write), and in which a second, subsequent floating-point instruction has as a source the first portion and a second portion of the same logical floating-point register (e.g., a double-precision read). The disclosed techniques may be applicable in a multithreaded processor implementing register renaming. In one embodiment, a processor may enter an operating mode in which detection of evil twin “producers” (e.g., single-precision writes) causes the instruction sequence to be modified to break potential dependencies. Modification of the instruction sequence may continue until one or more exit criteria are reached (e.g., committing a predetermined number of single-precision writes). This operating mode may be employed on a per-thread basis.
摘要翻译：公开了用于减轻指令组之间依赖性的各种技术。在一个实施例中，这种依赖性包括“恶双”条件，其中第一浮点指令具有作为目的地的逻辑浮点寄存器的第一部分（例如，单精度写入），并且其中第二浮点指令后续浮点指令作为源的相同逻辑浮点寄存器的第一部分和第二部分（例如，双精度读取）。所公开的技术可以适用于实现寄存器重命名的多线程处理器。在一个实施例中，处理器可以进入操作模式，在该操作模式中，恶意孪生“生产者”（例如，单精度写入）的检测导致指令序列被修改以破坏潜在依赖性。指令序列的修改可以继续，直到达到一个或多个退出标准（例如，提交预定数量的单精度写入）。该操作模式可以在每个线程的基础上使用。

8. 发明授权

US08504805B2 Processor operating mode for mitigating dependency conditions between instructions having different operand sizes 有权
标题翻译：用于缓解具有不同操作数大小的指令之间的依赖条件的处理器操作模式
公开(公告)号：US08504805B2
公开(公告)日：2013-08-06
申请号：US12428464
申请日：2009-04-22
申请人： Robert T. Golla , Paul J. Jordan , Jama I. Barreh , Matthew B. Smittle , Yuan C. Chou , Jared C. Smolens
发明人： Robert T. Golla , Paul J. Jordan , Jama I. Barreh , Matthew B. Smittle , Yuan C. Chou , Jared C. Smolens
IPC分类号： G06F7/483
CPC分类号： G06F9/3838 , G06F9/30032 , G06F9/30109 , G06F9/30189
摘要： Various techniques for mitigating dependencies between groups of instructions are disclosed. In one embodiment, such dependencies include “evil twin” conditions, in which a first floating-point instruction has as a destination a first portion of a logical floating-point register (e.g., a single-precision write), and in which a second, subsequent floating-point instruction has as a source the first portion and a second portion of the same logical floating-point register (e.g., a double-precision read). The disclosed techniques may be applicable in a multithreaded processor implementing register renaming. In one embodiment, a processor may enter an operating mode in which detection of evil twin “producers” (e.g., single-precision writes) causes the instruction sequence to be modified to break potential dependencies. Modification of the instruction sequence may continue until one or more exit criteria are reached (e.g., committing a predetermined number of single-precision writes). This operating mode may be employed on a per-thread basis.
摘要翻译：公开了用于减轻指令组之间依赖性的各种技术。在一个实施例中，这种依赖性包括“恶双”条件，其中第一浮点指令具有作为目的地的逻辑浮点寄存器的第一部分（例如，单精度写入），并且其中第二浮点指令后续浮点指令作为源的相同逻辑浮点寄存器的第一部分和第二部分（例如，双精度读取）。所公开的技术可以适用于实现寄存器重命名的多线程处理器。在一个实施例中，处理器可以进入操作模式，在该操作模式中，恶意孪生“生产者”（例如，单精度写入）的检测导致指令序列被修改以破坏潜在依赖性。指令序列的修改可以继续，直到达到一个或多个退出标准（例如，提交预定数量的单精度写入）。该操作模式可以在每个线程的基础上使用。

9. 发明申请

US20100333098A1 DYNAMIC TAG ALLOCATION IN A MULTITHREADED OUT-OF-ORDER PROCESSOR 有权
标题翻译：动态标签分配在一个多边进阶的处理器
公开(公告)号：US20100333098A1
公开(公告)日：2010-12-30
申请号：US12494532
申请日：2009-06-30
申请人： Paul J. Jordan , Robert T. Golla , Jama I. Barreh
发明人： Paul J. Jordan , Robert T. Golla , Jama I. Barreh
IPC分类号： G06F9/46 , G06F12/08
CPC分类号： G06F9/3851 , G06F9/384 , G06F9/3853 , G06F9/3855 , G06F9/3885
摘要： Various techniques for dynamically allocating instruction tags and using those tags are disclosed. These techniques may apply to processors supporting out-of-order execution and to architectures that supports multiple threads. A group of instructions may be assigned a tag value from a pool of available tag values. A tag value may be usable to determine the program order of a group of instructions relative to other instructions in a thread. After the group of instructions has been (or is about to be) committed, the tag value may be freed so that it can be re-used on a second group of instructions. Tag values are dynamically allocated between threads; accordingly, a particular tag value or range of tag values is not dedicated to a particular thread.
摘要翻译：公开了用于动态分配指令标签和使用这些标签的各种技术。这些技术可能适用于支持无序执行的处理器和支持多线程的体系结构。可以从可用标签值池中分配一组指令。标签值可用于确定相对于线程中的其他指令的一组指令的程序顺序。在指示组（或将要））提交之后，可以释放标签值，以便可以在第二组指令上重新使用。标记值在线程之间动态分配; 因此，特定标签值或标签值的范围不专用于特定线程。

10. 发明授权

US08904156B2 Perceptron-based branch prediction mechanism for predicting conditional branch instructions on a multithreaded processor 有权
标题翻译：基于感知器的分支预测机制，用于在多线程处理器上预测条件分支指令
公开(公告)号：US08904156B2
公开(公告)日：2014-12-02
申请号：US12578859
申请日：2009-10-14
申请人： Manish K. Shah , Gregory F. Grohoski , Robert T. Golla , Jama I. Barreh
发明人： Manish K. Shah , Gregory F. Grohoski , Robert T. Golla , Jama I. Barreh
IPC分类号： G06F9/38
CPC分类号： G06F9/383 , G06F9/3836 , G06F9/384 , G06F9/3848 , G06F9/3851
摘要： A multithreaded microprocessor includes an instruction fetch unit including a perceptron-based conditional branch prediction unit configured to provide, for each of one or more concurrently executing threads, a direction branch prediction. The conditional branch prediction unit includes a plurality of storages each including a plurality of entries. Each entry may be configured to store one or more prediction values. Each prediction value of a given storage may correspond to at least one conditional branch instruction in a cache line. The conditional branch prediction unit may generate a separate index value for accessing each storage by generating a first index value for accessing a first storage by combining one or more portions of a received instruction fetch address, and generating each other index value for accessing the other storages by combining the first index value with a different portion of direction branch history information.
摘要翻译：多线程微处理器包括指令提取单元，其包括基于感知器的条件分支预测单元，被配置为针对一个或多个并行执行的线程中的每一个为方向分支预测提供。条件分支预测单元包括多个存储器，每个存储器包括多个条目。每个条目可被配置为存储一个或多个预测值。给定存储器的每个预测值可以对应于高速缓存行中的至少一个条件转移指令。条件分支预测单元可以通过生成用于访问第一存储器的第一索引值来生成用于访问每个存储器的单独索引值，该第一索引值通过组合接收到的指令获取地址的一个或多个部分，并且生成彼此用于访问其他存储器的索引值通过将第一索引值与方向分支历史信息的不同部分组合。

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