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1. 发明授权

US06489914B1 RSD analog to digital converter 有权
标题翻译： RSD模数转换器
公开(公告)号：US06489914B1
公开(公告)日：2002-12-03
申请号：US10005275
申请日：2001-12-04
申请人： Robert S. Jones, III , Brett J. Thompsen
发明人： Robert S. Jones, III , Brett J. Thompsen
IPC分类号： H03M110
CPC分类号： H03M1/1023 , H03M1/0687 , H03M1/403
摘要： A RSD analog to digital converter has an RSD stage that in turn has a switched capacitor integrator (SCI). The SCI uses an operational amplifier. A capacitor, which operates as a offset compensation capacitor, is precharged to the offset voltage of the operational amplifier during a precharge phase. The next phase switches this offset compensation capacitor in the path of the capacitors which are used to perform the integration. The effect is that the offset of the operational amplifier is corrected by the use of the compensation capacitor that had been precharged to the offset voltage during the previous phase.
摘要翻译： RSD模数转换器具有RSD级，其依次具有开关电容积分器（SCI）。 SCI使用运算放大器。作为偏移补偿电容器工作的电容器在预充电阶段被预充电到运算放大器的偏移电压。下一相将该偏移补偿电容器切换到用于执行积分的电容器的路径中。效果是通过使用在前一阶段预充电到偏移电压的补偿电容来校正运算放大器的偏移。

2. 发明授权

US08525721B2 Low power cycle data converter 有权
标题翻译：低功率循环数据转换器
公开(公告)号：US08525721B2
公开(公告)日：2013-09-03
申请号：US13237092
申请日：2011-09-20
申请人： Robert S. Jones, III
发明人： Robert S. Jones, III
IPC分类号： H03M1/34
CPC分类号： H03M1/403
摘要： A redundant signed digit (RSD) analog to digital converter (ADC) receives a high voltage (VRH) and a low voltage (VRL) for use in converting an input signal to a digital signal. A doubling circuit receives the input signal and doubles the input signal to provide a doubled input signal using an amplifier and a first capacitor. The first capacitor has a capacitance of a first magnitude. A VR circuit continues processing the doubled input signal to provide a 2VR signal. A Vref circuit (VR+C5 and C6) provides a first RSD residue signal that is equal to a sum of a reference Vref and the 2VR signal. The first RSD residue signal is produced using the amplifier, a second capacitor, and the high power supply voltage. The second capacitor has a capacitance equal to half that of the first capacitor.
摘要翻译：冗余有符号数字（RSD）模数转换器（ADC）接收用于将输入信号转换为数字信号的高电压（VRH）和低电压（VRL）。双倍电路接收输入信号并使输入信号加倍，以使用放大器和第一电容器提供双倍的输入信号。第一电容器具有第一大小的电容。 VR电路继续处理双倍输入信号以提供2VR信号。 Vref电路（VR + C5和C6）提供等于参考Vref和2VR信号之和的第一RSD残留信号。使用放大器，第二电容器和高电源电压产生第一RSD残留信号。第二电容器具有等于第一电容器的一半的电容。

3. 发明授权

US06297757B1 Method and circuit for testing an analog-to-digital converter module on a data processing system having an intermodule bus 有权
标题翻译：用于在具有模块间总线的数据处理系统上测试模拟 - 数字转换器模块的方法和电路
公开(公告)号：US06297757B1
公开(公告)日：2001-10-02
申请号：US09248551
申请日：1999-02-11
申请人： Jules D. Campbell, Jr. , Jiang Chen , Robert S. Jones, III , Christian Ahrens , Scott Willard Herrin
发明人： Jules D. Campbell, Jr. , Jiang Chen , Robert S. Jones, III , Christian Ahrens , Scott Willard Herrin
IPC分类号： H03M106
CPC分类号： H03M1/108 , H03M1/12
摘要： A data processing system (20) includes a plurality of modules (44, 48) and an analog-to-digital converter (ADC) (46). The ADC (46) includes at least one port terminal (66) for transmitting test information from the ADC (46). The plurality of modules (44,48) and the ADC (46) are coupled to a central processing unit (CPU) (22) via an intermodule bus (42). A tester can exchange test information with the ADC (46) directly through the port terminal (66) instead of using the intermodule bus (42). Also, various sub-modules (62, 64, 60, 74) of the ADC (46) can be independently tested without performing a conversion process.
摘要翻译：数据处理系统（20）包括多个模块（44,48）和模数转换器（ADC）（46）。 ADC（46）包括用于从ADC（46）发送测试信息的至少一个端口（66）。多个模块（44,48）和ADC（46）经由模块间总线（42）耦合到中央处理单元（CPU）（22）。测试人员可以直接通过端口（66）与ADC（46）交换测试信息，而不是使用模块间总线（42）。此外，可以独立地测试ADC（46）的各个子模块（62,64,60,74），而不进行转换处理。

4. 发明授权

US09112523B1 Multiplying digital to analog converter (MDAC) with error compensation and method of operation 有权
标题翻译：乘法数字到模拟转换器（MDAC），具有误差补偿和操作方法
公开(公告)号：US09112523B1
公开(公告)日：2015-08-18
申请号：US14291355
申请日：2014-05-30
申请人： Alex A. Ford , Robert S. Jones, III
发明人： Alex A. Ford , Robert S. Jones, III
IPC分类号： H03M1/06 , H03M1/08 , H03M1/36 , H03K3/013
CPC分类号： H03M1/0609 , H03M1/168
摘要： The present disclosure provides methods and circuits for compensating reference shifting error. A compensation reference voltage is applied to an error compensation circuit, which is coupled to a multiplying circuit. A compensation parasitic capacitance is induced in the error compensation circuit. The compensation parasitic capacitance is configured to negate a parasitic capacitance induced in the multiplying circuit.
摘要翻译：本公开提供了用于补偿参考移位误差的方法和电路。补偿参考电压被施加到耦合到乘法电路的误差补偿电路。在误差补偿电路中产生补偿寄生电容。补偿寄生电容被配置为否定在乘法电路中感应的寄生电容。

5. 发明授权

US07589658B2 Analog-to-digital converter with variable gain and method thereof 有权
标题翻译：具有可变增益的模数转换器及其方法
公开(公告)号：US07589658B2
公开(公告)日：2009-09-15
申请号：US12026205
申请日：2008-02-05
申请人： Juxiang Ren , Mike R. Garrard , Robert S. Jones, III , Douglas A. Garrity
发明人： Juxiang Ren , Mike R. Garrard , Robert S. Jones, III , Douglas A. Garrity
IPC分类号： H03M1/38
CPC分类号： H03M1/186 , H03M1/0682 , H03M1/403 , H03M1/442
摘要： An analog-to-digital converter (ADC) device includes an input terminal to receive an analog signal, an analog component, and control logic. The analog component includes an amplifier having an input and an output and a capacitor network coupled to the input and the output of the amplifier. The capacitor network comprises a plurality of capacitors. The control logic is configured to, in a first mode, configure the capacitor network and the amplifier in an amplification configuration to amplify the analog signal by a predetermined gain to generate an amplified analog signal. The control logic further is configured to, in a second mode, configure the capacitor network and the amplifier to generate a series of one or more residue voltages using the amplified analog signal.
摘要翻译：模数转换器（ADC）装置包括用于接收模拟信号的输入端，模拟分量和控制逻辑。模拟组件包括具有输入和输出的放大器以及耦合到放大器的输入和输出的电容器网络。电容器网络包括多个电容器。控制逻辑被配置为在第一模式中，以放大配置来配置电容器网络和放大器以将模拟信号放大预定增益以产生放大的模拟信号。控制逻辑还被配置为在第二模式中，配置电容器网络和放大器以使用放大的模拟信号产生一系列一个或多个残余电压。

6. 发明授权

US6130635A Method of converting an analog signal in an A/D converter utilizing RDAC precharging 失效
标题翻译：使用RDAC预充电在A / D转换器中转换模拟信号的方法
公开(公告)号：US6130635A
公开(公告)日：2000-10-10
申请号：US128274
申请日：1998-08-03
申请人： Robert S. Jones, III
发明人： Robert S. Jones, III
IPC分类号： H03M1/06 , H03M1/76 , H03M1/12
CPC分类号： H03M1/06 , H03M1/765
摘要： A method for operating a circuit in an analog to digital converter, including providing a resistor network (205) having a plurality of resistor banks (200) connected together, each resistor bank of the plurality of resistor banks having a plurality of resistors (210) connected together in series and a plurality of first switches (220) for selecting a node (215) between adjacent resistors, and a plurality of second switches (235) for selecting a chosen resistor bank of the plurality of resistor banks. A first switch is closed in a chosen resistor bank to charge a parasitic capacitance (250), and a second switch is closed after closing the first switch, and after charging the parasitic capacitance in the chosen resistor bank.
摘要翻译：一种用于操作模数转换器中的电路的方法，包括提供具有连接在一起的多个电阻器组（200）的电阻器网络（205），所述多个电阻器组中的每个电阻器组具有多个电阻器（210）串联连接在一起的多个第一开关（220）和用于选择相邻电阻器之间的节点（215）的多个第一开关（220）和用于选择多个电阻器组中所选电阻器组的多个第二开关（235）。在所选择的电阻器组中，第一开关闭合以对寄生电容（250）充电，并且在闭合第一开关之后并且在所选择的电阻器组中对寄生电容充电之后关闭第二开关。

7. 发明申请

US20090195428A1 ANALOG-TO-DIGITAL CONVERTER WITH VARIABLE GAIN AND METHOD THEREOF 有权
标题翻译：具有可变增益的模数转数转换器及其方法
公开(公告)号：US20090195428A1
公开(公告)日：2009-08-06
申请号：US12026205
申请日：2008-02-05
申请人： Juxiang Ren , Mike R. Garrard , Robert S. Jones, III , Douglas A. Garrity
发明人： Juxiang Ren , Mike R. Garrard , Robert S. Jones, III , Douglas A. Garrity
IPC分类号： H03M1/12
CPC分类号： H03M1/186 , H03M1/0682 , H03M1/403 , H03M1/442
摘要： An analog-to-digital converter (ADC) device includes an input terminal to receive an analog signal, an analog component, and control logic. The analog component includes an amplifier having an input and an output and a capacitor network coupled to the input and the output of the amplifier. The capacitor network comprises a plurality of capacitors. The control logic is configured to, in a first mode, configure the capacitor network and the amplifier in an amplification configuration to amplify the analog signal by a predetermined gain to generate an amplified analog signal. The control logic further is configured to, in a second mode, configure the capacitor network and the amplifier to generate a series of one or more residue voltages using the amplified analog signal.
摘要翻译：模数转换器（ADC）装置包括用于接收模拟信号的输入端，模拟分量和控制逻辑。模拟组件包括具有输入和输出的放大器以及耦合到放大器的输入和输出的电容器网络。电容器网络包括多个电容器。控制逻辑被配置为在第一模式中，以放大配置来配置电容器网络和放大器，以将预定增益放大模拟信号以产生放大的模拟信号。控制逻辑还被配置为在第二模式中，配置电容器网络和放大器以使用放大的模拟信号产生一系列一个或多个残余电压。

8. 发明授权

US06346908B1 Apparatus for converting an analog signal utilizing resistor D/A converter precharging 有权
标题翻译：用于使用电阻器D / A转换器预充电来转换模拟信号的装置
公开(公告)号：US06346908B1
公开(公告)日：2002-02-12
申请号：US09574754
申请日：2000-05-18
申请人： Robert S. Jones, III
发明人： Robert S. Jones, III
IPC分类号： H03M112
CPC分类号： H03M1/06 , H03M1/765
摘要： A method for operating a circuit in an analog to digital converter, including providing a resistor network (205) having a plurality of resistor banks (200) connected together, each resistor bank of the plurality of resistor banks having a plurality of resistors (210) connected together in series and a plurality of first switches (220) for selecting a node (215) between adjacent resistors, and a plurality of second switches (235) for selecting a chosen resistor bank of the plurality of resistor banks. A first switch is closed in a chosen resistor bank to charge a parasitic capacitance (250), and a second switch is closed after closing the first switch, and after charging the parasitic capacitance in the chosen resistor bank.
摘要翻译：一种用于操作模数转换器中的电路的方法，包括提供具有连接在一起的多个电阻器组（200）的电阻器网络（205），所述多个电阻器组中的每个电阻器组具有多个电阻器（210）串联连接在一起的多个第一开关（220）和用于选择相邻电阻器之间的节点（215）的多个第一开关（220）和用于选择多个电阻器组中所选电阻器组的多个第二开关（235）。在所选择的电阻器组中，第一开关闭合以对寄生电容（250）充电，并且在闭合第一开关之后并且在所选择的电阻器组中对寄生电容充电之后关闭第二开关。

9. 发明授权

US5406220A Pole/zero compensation in cascode amplifiers 失效
标题翻译：串联放大器中的零点/零点补偿
公开(公告)号：US5406220A
公开(公告)日：1995-04-11
申请号：US143967
申请日：1993-11-01
申请人： Robert S. Jones, III , Jeffrey D. Ganger
发明人： Robert S. Jones, III , Jeffrey D. Ganger
IPC分类号： H03F1/08 , H03F3/45
CPC分类号： H03F3/45192 , H03F1/086 , H03F2203/45028 , H03F2203/45184 , H03F2203/45201 , H03F2203/45264
摘要： Compensation for a second pole located at an internal node (107 and 108) of a two pole cascode differential amplifier (30) is accomplished by introducing a left half plane zero in the transfer function of the cascode differential amplifier (30). This is done by coupling a compensation capacitor (46, 47) between an output node (105, 106) and the internal node (107, 108) of the cascode differential amplifier (30). The compensation capacitors (46, 47) improve high frequency performance of the amplifier (30) by improving phase margin and increasing stability.
摘要翻译：通过在共源共栅差分放大器（30）的传递函数中引入左半平面零点来实现位于两极共源共栅差分放大器（30）的内部节点（107和108）处的第二极点的补偿。这通过将输出节点（105,106）和共源共栅差分放大器（30）的内部节点（107,108）之间的补偿电容器（46,47）耦合来完成。补偿电容器（46,47）通过改善相位裕度和增加的稳定性来改善放大器（30）的高频性能。

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