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1. 发明授权

US06713358B1 Method for making a semiconductor device having a high-k gate dielectric 有权
标题翻译：制造具有高k栅极电介质的半导体器件的方法
公开(公告)号：US06713358B1
公开(公告)日：2004-03-30
申请号：US10288043
申请日：2002-11-05
申请人： Robert S. Chau , Timothy E. Glassman , Christopher G. Parker , Matthew V. Metz , Lawrence J. Foley , Reza Arghavani , Douglas W. Barlage
发明人： Robert S. Chau , Timothy E. Glassman , Christopher G. Parker , Matthew V. Metz , Lawrence J. Foley , Reza Arghavani , Douglas W. Barlage
IPC分类号： H01L21336
CPC分类号： H01L21/28194 , H01L21/28167 , H01L21/28202 , H01L29/513 , H01L29/517 , H01L29/518
摘要： A method for making a semiconductor device is described. That method comprises forming a high-k gate dielectric layer on a substrate. After forming a silicon nitride layer on the high-k gate dielectric layer, a gate electrode is formed on the silicon nitride layer.
摘要翻译：描述制造半导体器件的方法。该方法包括在衬底上形成高k栅介质层。在高k栅极电介质层上形成氮化硅层之后，在氮化硅层上形成栅电极。

2. 发明授权

US06787440B2 Method for making a semiconductor device having an ultra-thin high-k gate dielectric 有权
公开(公告)号：US06787440B2
公开(公告)日：2004-09-07
申请号：US10315268
申请日：2002-12-10
申请人： Christopher G. Parker , Markus Kuhn , Ying Zhou , Scott A. Hareland , Suman Datta , Nick Lindert , Robert S. Chau , Timothy E. Glassman , Matthew V. Metz , Sunit Tyagi
发明人： Christopher G. Parker , Markus Kuhn , Ying Zhou , Scott A. Hareland , Suman Datta , Nick Lindert , Robert S. Chau , Timothy E. Glassman , Matthew V. Metz , Sunit Tyagi
IPC分类号： H01L214763
CPC分类号： H01L21/28194 , H01L21/28202 , H01L29/513 , H01L29/518
摘要： A method for making a semiconductor device is described. That method comprises forming on a substrate a buffer layer and a high-k gate dielectric layer, oxidizing the surface of the high-k gate dielectric layer, and then forming a gate electrode on the oxidized high-k gate dielectric layer.

3. 发明授权

US06667232B2 Thin dielectric layers and non-thermal formation thereof 失效
标题翻译：形成薄栅极电介质层的方法
公开(公告)号：US06667232B2
公开(公告)日：2003-12-23
申请号：US09208268
申请日：1998-12-08
申请人： Steven J. Keating , Robert S. Chau , Reza Arghavani , Jack T. Kavalieros , Douglas W. Barlage
发明人： Steven J. Keating , Robert S. Chau , Reza Arghavani , Jack T. Kavalieros , Douglas W. Barlage
IPC分类号： H01L214763
CPC分类号： H01L21/0214 , H01L21/02329 , H01L21/0234 , H01L21/28185 , H01L21/28202 , H01L21/3143 , H01L29/51 , H01L29/518 , H01L2924/0002 , Y10S438/954 , H01L2924/00
摘要： A method of forming a dielectric layer suitable for use as the gate dielectric layer in a MOSFET includes passivating the surface of a semiconductor substrate at a temperature less than approximately 80° C. and nitridizing the passivation layer. In particular embodiments, passivating a silicon wafer includes forming a hydroxy-silicate layer at approximately 24° C. In a further aspect of the present invention, an integrated circuit includes a plurality of insulated gate field effect transistors, wherein various ones of the plurality of transistors have gate dielectric layers of the nitridized passivation layer.
摘要翻译：形成适合用作MOSFET中的栅介质层的电介质层的方法包括在低于大约80℃的温度下钝化半导体衬底的表面并使钝化层氮化。在特定实施例中，钝化硅晶片包括在约24℃下形成羟基硅酸盐层。在本发明的另一方面，集成电路包括多个绝缘栅场效应晶体管，其中多个晶体管具有氮化钝化层的栅介质层。

4. 发明授权

US06597046B1 Integrated circuit with multiple gate dielectric structures 有权
标题翻译：具有多栅绝缘结构的集成电路
公开(公告)号：US06597046B1
公开(公告)日：2003-07-22
申请号：US09378053
申请日：1999-08-20
申请人： Robert S. Chau , Reza Arghavani , Bruce Beattie
发明人： Robert S. Chau , Reza Arghavani , Bruce Beattie
IPC分类号： H01L2976
CPC分类号： H01L21/823462
摘要： An integrated circuit includes insulated gate field effect transistors (IGFETs), having gate dielectric layers wherein a nitrogen concentration in the gate dielectric varies between a first concentration at the gate electrode/gate dielectric interface and a second concentration at the gate dielectric/substrate interface. In one embodiment the gate dielectric is an oxynitride formed by an N2 plasma; and the oxynitride has top surface nitrogen concentration that is higher than a bottom surface nitrogen concentration. In a further aspect of the present invention, an integrated circuit includes a plurality of IGFETs, wherein various ones of the plurality of IGFETs have different gate dielectric thicknesses and compositions. A method of forming IGFETs with different gate dielectric thicknesses and compositions, on a single integrated circuit, includes forming a first oxynitride layer, forming a masking layer, removing a portion of the first oxynitride layer, forming an oxide layer where the oxynitride was removed, and forming a plurality of gate electrodes, a first portion of the gate electrodes overlying the first oxynitride layer.
摘要翻译：集成电路包括绝缘栅场效应晶体管（IGFET），其具有栅极电介质层，其中栅极电介质中的氮浓度在栅极电极/栅极电介质界面处的第一浓度与栅极电介质/衬底界面处的第二浓度之间变化。在一个实施例中，栅极电介质是由N 2等离子体形成的氧氮化物; 氮氧化物的顶表面氮浓度高于底面氮浓度。在本发明的另一方面，集成电路包括多个IGFET，其中多个IGFET中的各种具有不同的栅介质厚度和组成。在单个集成电路上形成具有不同栅电介质厚度和组成的IGFET的方法包括形成第一氧氮化物层，形成掩模层，去除第一氮氧化物层的一部分，形成除去氧氮化物的氧化物层，以及形成多个栅电极，所述栅电极的覆盖所述第一氧氮化物层的第一部分。

5. 发明授权

US6140251A Method of processing a substrate 失效
标题翻译：处理基板的方法
公开(公告)号：US6140251A
公开(公告)日：2000-10-31
申请号：US987888
申请日：1997-12-10
申请人： Reza Arghavani , Robert S. Chau , Weimin Han
发明人： Reza Arghavani , Robert S. Chau , Weimin Han
IPC分类号： H01L21/28 , H01L21/314 , H01L21/316 , H01L21/762 , H01L29/51 , H01L21/31 , H01L21/469
CPC分类号： H01L21/28202 , H01L21/02164 , H01L21/02271 , H01L21/3145 , H01L21/31612 , H01L21/76224 , H01L21/76232 , H01L29/518
摘要： A method of processing a semiconductor substrate, comprising the steps of: heating a substance within a first chamber, at a selected temperature which is above the minimum decomposition temperature of the substance, to cause decomposition of the substance into a predetermined gas; cooling the gas to below the minimum decomposition temperature of the substance; transporting the gas from the first chamber to a second chamber; and exposing a semiconductor substrate, located in the second chamber, to the cooled gas.
摘要翻译：一种处理半导体衬底的方法，包括以下步骤：在高于物质最小分解温度的选定温度下加热第一室内物质，使物质分解成预定气体; 将气体冷却至物质的最低分解温度以下; 将气体从第一室输送到第二室; 以及将位于所述第二室中的半导体衬底暴露于所述冷却气体。

6. 发明授权

US06221789B1 Thin oxides of silicon 失效
标题翻译：硅的薄氧化物
公开(公告)号：US06221789B1
公开(公告)日：2001-04-24
申请号：US09124562
申请日：1998-07-29
申请人： Reza Arghavani , Robert S. Chau
发明人： Reza Arghavani , Robert S. Chau
IPC分类号： H01L21469
CPC分类号： H01L21/28211 , C23C8/10 , H01L21/02238 , H01L21/02255 , H01L21/3144 , H01L21/31654 , H01L21/31662
摘要： An oxidation process that produces multi-layer, yet very thin oxides of silicon, formed on silicon substrates, includes pushing wafers at a particular range of speeds, into a furnace at a particular range of temperatures, sequentially oxidizing the wafers in varying chemical ambients, and operating an external chlorine compound generator coupled to the furnace. Oxides formed in this manner have good uniformity and low interface state density and are suitable for forming FETs. In a particular embodiment, a first portion of an oxide stack is formed in an oxygen/nitrogen ambient, a second portion of an oxide stack is formed in a carbon dioxide/hydrogen chloride/oxygen ambient, and a third portion of an oxide stack is formed by a wet oxidation. The second portion of the oxide stack is formed when 1,2-dichloroethylene is treated with heat and oxygen to produce carbon dioxide and hydrogen chloride gas that is then introduced into the furnace.
摘要翻译：在硅衬底上形成多层但非常薄的硅氧化物的氧化工艺包括将晶片以特定的速度推入特定温度范围内的炉中，在不同的化学环境中依次氧化晶片，并操作耦合到炉的外部氯化合物发生器。以这种方式形成的氧化物具有良好的均匀性和低界面态密度，并且适于形成FET。在一个具体实施方案中，在氧/氮环境中形成氧化物堆叠的第一部分，形成氧化物堆叠的第二部分在二氧化碳/氯化氢/氧气环境中，并且氧化物堆叠的第三部分通过湿氧化形成。当用热和氧处理1,2-二氯乙烯时，形成氧化物堆叠的第二部分，以产生二氧化碳和氯化氢气体，然后将其引入炉中。

7. 发明授权

US6124171A Method of forming gate oxide having dual thickness by oxidation process 有权
标题翻译：通过氧化工艺形成具有双重厚度的栅极氧化物的方法
公开(公告)号：US6124171A
公开(公告)日：2000-09-26
申请号：US160556
申请日：1998-09-24
申请人： Reza Arghavani , Bruce Beattie , Robert S. Chau , Jack Kavalieros , Bob McFadden
发明人： Reza Arghavani , Bruce Beattie , Robert S. Chau , Jack Kavalieros , Bob McFadden
IPC分类号： H01L21/8234 , H01L21/336
CPC分类号： H01L21/823462 , Y10S438/981
摘要： Transistors are formed on the substrate having two different thickness' of gate oxides. A silicon nitride mask is used to protect one of the gate oxides while the other is grown. A nitride mask is formed from a hydrogen balanced nitride layer formed using direct plasma deposited nitride with an ammonia and silane chemistry. In one embodiment the nitride mask remains in place in the completed transistor.
摘要翻译：晶体管形成在具有两个不同厚度的栅极氧化物的衬底上。使用氮化硅掩模来保护栅极氧化物中的一个，而另一个生长。氮化物掩模由使用直接等离子体沉积氮化物与氨和硅烷化学形成的氢平衡氮化物层形成。在一个实施例中，氮化物掩模保留在完成的晶体管中的适当位置。

8. 发明授权

US06566727B1 N2O nitrided-oxide trench sidewalls to prevent boron outdiffusion and decrease stress 失效
标题翻译： N2O氮化氧化物沟槽侧壁，以防止硼扩散并减少应力
公开(公告)号：US06566727B1
公开(公告)日：2003-05-20
申请号：US09433541
申请日：1999-11-03
申请人： Reza Arghavani , Robert S. Chau , Simon Yang , John Graham
发明人： Reza Arghavani , Robert S. Chau , Simon Yang , John Graham
IPC分类号： H01L2500
CPC分类号： H01L21/31053 , H01L21/76235
摘要： A method of forming an isolation structure in a semiconductor substrate is described. A trench is first etched into a semiconductor substrate. A first oxide layer is then formed with the trench. The first oxide layer is subjected to a nitrogen-oxide gas ambient and is annealed to form an oxy-nitride surface on the first oxide layer and a silicon-oxynitride interface between the first oxide layer and the semiconductor substrate. A second oxide layer is then deposited over the oxy-nitride surface of the first oxide layer. The method and isolation structure of the present invention prevents dopant outdiffusion, reduces trench stresses, allows more uniform growth of thin gate oxides, and permits the use of thinner gate oxides.
摘要翻译：描述在半导体衬底中形成隔离结构的方法。首先将沟槽蚀刻到半导体衬底中。然后用沟槽形成第一氧化物层。对第一氧化物层进行氮氧化物气氛环境的退火处理，以在第一氧化物层上形成氧氮化物表面，在第一氧化物层和半导体衬底之间形成氮氧化硅界面。然后将第二氧化物层沉积在第一氧化物层的氧化氮化物表面上。本发明的方法和隔离结构防止掺杂剂扩散，减小沟槽应力，允许薄栅极氧化物的更均匀生长，并允许使用更薄的栅极氧化物。

9. 发明授权

US5780346A N.sub.2 O nitrided-oxide trench sidewalls and method of making isolation structure 失效
标题翻译： N2O氮化氧化物沟槽侧壁和隔离结构的制备方法
公开(公告)号：US5780346A
公开(公告)日：1998-07-14
申请号：US775571
申请日：1996-12-31
申请人： Reza Arghavani , Robert S. Chau , Simon Yang , John Graham
发明人： Reza Arghavani , Robert S. Chau , Simon Yang , John Graham
IPC分类号： H01L21/76 , H01L21/3105 , H01L21/762
CPC分类号： H01L21/31053 , H01L21/76235
摘要： A method of forming an isolation structure in a semiconductor substrate is described. A trench is first etched into a semiconductor substrate. A first oxide layer is then formed with the trench. The first oxide layer is subjected to a nitrogen-oxide gas ambient and is annealed to form an oxy-nitride surface on the first oxide layer and a silicon-oxynitride interface between the first oxide layer and the semiconductor substrate. A second oxide layer is then deposited over the oxy-nitride surface of the first oxide layer. The method and isolation structure of the present invention prevents dopant outdiffusion, reduces trench stresses, allows more uniform growth of thin gate oxides, and permits the use of thinner gate oxides.
摘要翻译：描述在半导体衬底中形成隔离结构的方法。首先将沟槽蚀刻到半导体衬底中。然后用沟槽形成第一氧化物层。对第一氧化物层进行氮氧化物气氛环境的退火处理，以在第一氧化物层上形成氧氮化物表面，在第一氧化物层和半导体衬底之间形成氮氧化硅界面。然后将第二氧化物层沉积在第一氧化物层的氧化氮化物表面上。本发明的方法和隔离结构防止掺杂剂扩散，减小沟槽应力，允许薄栅极氧化物的更均匀生长，并允许使用更薄的栅极氧化物。

10. 发明授权

US09634007B2 Trench confined epitaxially grown device layer(s) 有权
公开(公告)号：US09634007B2
公开(公告)日：2017-04-25
申请号：US14302350
申请日：2014-06-11
申请人： Ravi Pillarisetty , Seung Hoon Sung , Niti Goel , Jack T. Kavalieros , Sansaptak Dasgupta , Van H. Le , Willy Rachmady , Marko Radosavljevic , Gilbert Dewey , Han Wui Then , Niloy Mukherjee , Matthew V. Metz , Robert S. Chau
发明人： Ravi Pillarisetty , Seung Hoon Sung , Niti Goel , Jack T. Kavalieros , Sansaptak Dasgupta , Van H. Le , Willy Rachmady , Marko Radosavljevic , Gilbert Dewey , Han Wui Then , Niloy Mukherjee , Matthew V. Metz , Robert S. Chau
IPC分类号： H01L29/66 , H01L29/78 , H01L21/02 , H01L21/762 , H01L27/092 , H01L21/8258 , H01L29/423 , H01L29/786 , B82Y10/00 , B82Y40/00 , H01L29/775 , H01L29/06 , H01L21/8238
CPC分类号： H01L21/845 , B82Y10/00 , B82Y40/00 , H01L21/02639 , H01L21/823807 , H01L21/8258 , H01L27/092 , H01L27/1211 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/6653 , H01L29/66795 , H01L29/6681 , H01L29/775 , H01L29/78 , H01L29/785 , H01L29/7853 , H01L29/78696
摘要： Trench-confined selective epitaxial growth process in which epitaxial growth of a semiconductor device layer proceeds within the confines of a trench. In embodiments, a trench is fabricated to include a pristine, planar semiconductor seeding surface disposed at the bottom of the trench. Semiconductor regions around the seeding surface may be recessed relative to the seeding surface with Isolation dielectric disposed there on to surround the semiconductor seeding layer and form the trench. In embodiments to form the trench, a sacrificial hardmask fin may be covered in dielectric which is then planarized to expose the hardmask fin, which is then removed to expose the seeding surface. A semiconductor device layer is formed from the seeding surface through selective heteroepitaxy. In embodiments, non-planar devices are formed from the semiconductor device layer by recessing a top surface of the isolation dielectric. In embodiments, non-planar devices CMOS devices having high carrier mobility may be made from the semiconductor device layer.

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