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1. 发明授权

US06198142B1 Transistor with minimal junction capacitance and method of fabrication 失效
标题翻译：具有最小结电容的晶体管和制造方法
公开(公告)号：US06198142B1
公开(公告)日：2001-03-06
申请号：US09127349
申请日：1998-07-31
申请人： Robert S. Chau , Chia-Hong Jan , Paul Packan , Mitchell C. Taylor
发明人： Robert S. Chau , Chia-Hong Jan , Paul Packan , Mitchell C. Taylor
IPC分类号： H01L2976
CPC分类号： H01L29/66636 , H01L21/26533 , H01L29/0653 , H01L29/165 , H01L29/665 , H01L29/66537 , H01L29/7834
摘要： A novel MOS transistor having minimal junction capacitance in this method of fabrication. According to the present invention, a gate dielectric layer is formed on a first surface of the semiconductor substrate. A gate electrode is then formed on the gate dielectric layer. Next, a pair of recesses are formed in the semiconductor substrate on opposite sides of the gate electrode. A dielectric layer is then formed on the surface of each of the recesses. A Semiconductor material is then deposited into the recesses to form a pair of source/drain regions.
摘要翻译：在该制造方法中具有最小结电容的新型MOS晶体管。根据本发明，在半导体衬底的第一表面上形成栅介质层。然后在栅极电介质层上形成栅电极。接下来，在栅电极的相对侧上的半导体衬底中形成一对凹部。然后在每个凹部的表面上形成介电层。然后将半导体材料沉积到凹槽中以形成一对源极/漏极区域。

2. 发明授权

US5908313A Method of forming a transistor 失效
标题翻译：形成晶体管的方法
公开(公告)号：US5908313A
公开(公告)日：1999-06-01
申请号：US775410
申请日：1996-12-31
申请人： Robert S. Chau , Chia-Hong Jan , Paul Packan , Mitchell C. Taylor
发明人： Robert S. Chau , Chia-Hong Jan , Paul Packan , Mitchell C. Taylor
IPC分类号： H01L21/225 , H01L21/265 , H01L21/28 , H01L21/336 , H01L29/06 , H01L29/10 , H01L29/417 , H01L29/49
CPC分类号： H01L29/66477 , H01L21/26586 , H01L21/28052 , H01L29/0653 , H01L29/1083 , H01L29/41766 , H01L29/41783 , H01L29/4925 , H01L29/66628 , H01L29/66636 , H01L21/2254 , H01L21/2257 , H01L21/26506
摘要： A novel MOS transistor having minimal junction capacitance in this method of fabrication. According to the present invention, a gate dielectric layer is formed on a first surface of the semiconductor substrate. A gate electrode is then formed on the gate dielectric layer. Next, a pair of recesses are formed in the semiconductor substrate on opposite sides of the gate electrode. A dielectric layer is then formed on the surface of each of the recesses. A Semiconductor material is then deposited into the recesses to form a pair of source/drain regions.
摘要翻译：在该制造方法中具有最小结电容的新型MOS晶体管。根据本发明，在半导体衬底的第一表面上形成栅介质层。然后在栅极电介质层上形成栅电极。接下来，在栅电极的相对侧上的半导体衬底中形成一对凹部。然后在每个凹部的表面上形成介电层。然后将半导体材料沉积到凹槽中以形成一对源极/漏极区域。

3. 发明授权

US6121100A Method of fabricating a MOS transistor with a raised source/drain extension 失效
标题翻译：制造具有升高的源极/漏极延伸的MOS晶体管的方法
公开(公告)号：US6121100A
公开(公告)日：2000-09-19
申请号：US1337
申请日：1997-12-31
申请人： Ebrahim Andideh , Lawrence Brigham , Robert S. Chau , Tahir Ghani , Chia-Hong Jan , Justin Sandford , Mitchell C. Taylor
发明人： Ebrahim Andideh , Lawrence Brigham , Robert S. Chau , Tahir Ghani , Chia-Hong Jan , Justin Sandford , Mitchell C. Taylor
IPC分类号： H01L21/225 , H01L21/336 , H01L21/8238 , H01L29/417 , H01L29/45 , H01L29/49 , H01L29/78
CPC分类号： H01L29/6653 , H01L21/2254 , H01L21/823814 , H01L29/41766 , H01L29/41783 , H01L29/456 , H01L29/4925 , H01L29/66636 , H01L29/7834 , H01L29/665 , H01L29/66545
摘要： A method of forming a MOS transistor. According to the method of the present invention, a pair of source/drain contact regions are formed on opposite sides of a gate electrode. After forming the pair of source/drain contact regions, semiconductor material is deposited onto opposite sides of the gate electrode. Dopants are then diffused from the semiconductor material into the substrate beneath the gate electrode to form a pair of source/drain extensions.
摘要翻译：一种形成MOS晶体管的方法。根据本发明的方法，在栅电极的相对侧上形成一对源极/漏极接触区域。在形成一对源极/漏极接触区域之后，半导体材料沉积在栅电极的相对侧上。掺杂剂然后从半导体材料扩散到栅电极下方的衬底中，以形成一对源/漏扩展。

4. 发明授权

US08999798B2 Methods for forming NMOS EPI layers 有权
标题翻译：形成NMOS EPI层的方法
公开(公告)号：US08999798B2
公开(公告)日：2015-04-07
申请号：US12968528
申请日：2010-12-15
申请人： Mitchell C. Taylor , Susan B. Felch
发明人： Mitchell C. Taylor , Susan B. Felch
IPC分类号： H01L21/336 , H01L21/67 , H01L21/20 , H01J37/32 , H01L21/223 , H01L21/268 , H01L29/165 , H01L29/66 , H01L29/78 , H01L21/02 , H01L21/683
CPC分类号： H01L21/67207 , H01J37/321 , H01J37/32357 , H01J37/32412 , H01L21/02529 , H01L21/02532 , H01L21/0262 , H01L21/2018 , H01L21/2236 , H01L21/268 , H01L21/67115 , H01L21/67167 , H01L21/6719 , H01L21/6831 , H01L29/165 , H01L29/66636 , H01L29/78 , H01L29/7848
摘要： NMOS transistors having controlled channel strain and junction resistance and methods for the fabrication of same are provided herein. In some embodiments, a method for forming an NMOS transistor may include (a) providing a substrate having a p-type silicon region; (b) depositing a silicon seed layer atop the p-type silicon region; (c) depositing a silicon-containing bulk layer comprising silicon, silicon and a lattice adjusting element or silicon and an n-type dopant atop the silicon seed layer; (d) implanting at least one of the lattice adjusting element or the n-type dopant which is absent from the silicon-containing bulk layer deposited in (c) into the silicon-containing bulk layer; and (e) annealing the silicon-containing bulk layer with an energy beam after implantation in (d). In some embodiments, the substrate may comprise a partially fabricated NMOS transistor device having a source/drain region defined therein.
摘要翻译：具有受控的通道应变和结电阻的NMOS晶体管及其制造方法在此提供。在一些实施例中，用于形成NMOS晶体管的方法可以包括（a）提供具有p型硅区域的衬底; （b）在p型硅区域的顶部沉积硅晶种层; （c）在所述硅籽晶层的顶部沉积包含硅，硅和晶格调节元件或硅和n型掺杂剂的含硅体层; （d）将沉积在（c）中的含硅体积层中不存在的晶格调整元件或n型掺杂物中的至少一个注入到含硅体层中; 和（e）在（d）中植入之后用能量束对含硅体层进行退火。在一些实施例中，衬底可以包括其中限定了源极/漏极区域的部分制造的NMOS晶体管器件。

5. 发明申请

US20080160683A1 SOURCE/DRAIN EXTENSIONS IN NMOS DEVICES 审中-公开
标题翻译： NMOS器件中的源/漏极扩展
公开(公告)号：US20080160683A1
公开(公告)日：2008-07-03
申请号：US11618368
申请日：2006-12-29
申请人： Aaron O. Vanderpool , Mitchell C. Taylor
发明人： Aaron O. Vanderpool , Mitchell C. Taylor
IPC分类号： H01L21/8232 , H01L21/335
CPC分类号： H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L21/26586 , H01L29/1045 , H01L29/1083 , H01L29/6659 , H01L29/7833
摘要： A method including implanting carbon and fluorine into a substrate in an area of the substrate between a source/drain region and a channel, the area designated for a source/drain extension; and a source/drain extension dopant following implanting carbon and fluorine, implanting phosphorous in the area. A method including disrupting a crystal lattice of a semiconductor substrate in an area of the substrate between a source/drain region and a channel designated for a source/drain extension; after disrupting, implanting carbon and fluorine in the area; and implanting phosphorous in the area. A method including performing a boron halo implant before implanting phosphorous to form N-type source/drain extensions. An apparatus including an N-type transistor having a source/drain extension comprising carbon and phosphorous, formed in an area of a substrate between a source/drain region of the transistor and a channel of the transistor.
摘要翻译：一种方法，包括在源极/漏极区域和沟道之间的衬底区域中注入碳和氟，指定用于源极/漏极延伸的区域; 以及在注入碳和氟之后的源极/漏极扩展掺杂剂，在该区域中注入磷。一种方法，包括在源极/漏极区域和指定用于源极/漏极延伸的沟道之间的衬底区域中破坏半导体衬底的晶格; 破坏后，在该地区植入碳氟; 并在该区域植入磷。一种方法，包括在注入磷之前进行硼卤素注入以形成N型源/漏扩展。一种包括形成在晶体管的源极/漏极区域和晶体管的沟道之间的衬底的区域中的包括碳和磷的源极/漏极延伸的N型晶体管的装置。

6. 发明授权

US07671358B2 Plasma implantated impurities in junction region recesses 失效
标题翻译：接合区凹陷中的等离子体植入杂质
公开(公告)号：US07671358B2
公开(公告)日：2010-03-02
申请号：US11899250
申请日：2007-09-04
申请人： Nick Lindert , Mitchell C. Taylor
发明人： Nick Lindert , Mitchell C. Taylor
IPC分类号： H01L31/00
CPC分类号： H01L29/7848 , H01L21/26506 , H01L21/26513 , H01L21/823807 , H01L21/823814 , H01L29/1083 , H01L29/165 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834 , Y10S257/917
摘要： A transistor device having a conformal depth of impurities implanted by isotropic ion implantation into etched junction recesses. For example, a conformal depth of arsenic impurities and/or carbon impurities may be implanted by plasma immersion ion implantation in junction recesses to reduce boron diffusion and current leakage from boron doped junction region material deposited in the junction recesses. This may be accomplished by removing, such as by etching, portions of a substrate adjacent to a gate electrode to form junction recesses. The junction recesses may then be conformally implanted with a depth of arsenic and carbon impurities using plasma immersion ion implantation. After impurity implantation, boron doped silicon germanium can be formed in the junction recesses.
摘要翻译：具有通过各向同性离子注入注入蚀刻的接合凹部中的杂质的保形深度的晶体管器件。例如，砷杂质和/或碳杂质的保形深度可以通过等离子体浸没离子注入植入连接凹槽中，以减少沉积在接合凹部中的硼掺杂结区域材料的硼扩散和电流泄漏。这可以通过例如通过蚀刻除去与栅电极相邻的衬底的部分以形成结凹陷来实现。然后，可以使用等离子体浸没离子注入，在接合凹槽中共同地注入砷和碳杂质的深度。在杂质注入之后，可以在接合凹槽中形成硼掺杂的硅锗。

7. 发明授权

US07235843B2 Implanting carbon to form P-type source drain extensions 有权
标题翻译：植入碳以形成P型源极漏极延伸
公开(公告)号：US07235843B2
公开(公告)日：2007-06-26
申请号：US11325864
申请日：2006-01-05
申请人： Aaron O. Vanderpool , Mitchell C. Taylor
发明人： Aaron O. Vanderpool , Mitchell C. Taylor
IPC分类号： H01L29/78
CPC分类号： H01L29/7833 , H01L21/26506 , H01L21/26513 , H01L29/6659
摘要： The use of a carbon implant, in addition to the conventional fluorine implant, may significantly reduce the transient enhanced diffusion in P-type source drain extension regions. As a result, resistivity may be reduced, and dopant density may be increased, increasing current drive in some embodiments.
摘要翻译：除了常规的氟注入之外，碳植入物的使用可以显着减少P型源极漏极延伸区域中的瞬时增强的扩散。结果，在一些实施例中，可以降低电阻率并且可以增加掺杂剂密度，增加电流驱动。

8. 发明授权

US06432798B1 Extension of shallow trench isolation by ion implantation 有权
标题翻译：通过离子注入扩展浅沟槽隔离
公开(公告)号：US06432798B1
公开(公告)日：2002-08-13
申请号：US09636297
申请日：2000-08-10
申请人： Mark Y. Liu , Leonard C. Pipes , Mitchell C. Taylor
发明人： Mark Y. Liu , Leonard C. Pipes , Mitchell C. Taylor
IPC分类号： H01L2176
CPC分类号： H01L21/76237
摘要： A shallow trench isolation (STI) structure is formed by etching trenches into the surface of a substrate in alignment with a patterned masking layer. An ion implantation of, for example, carbon, nitrogen, or oxygen, is performed so as to create an electrically insulating layer extending downwardly from a bottom surface of the trench. By implanting such extensions, STI structures with greater effective aspect ratios may be obtained which, in turn, allow greater packing density in integrated circuits. Implanted isolation structures may be formed without etching a trench by implanting into regions of the substrate. In this way, trench etch, dielectric back-fill, and planarization operations can be eliminated. Furthermore the implanted regions may be formed by multiple implants at different energies so as to obtain multiple, typically contiguous, target ranges. Ions of various masses or charges may be used so as to obtain the desired implant depth and concentration profile in the isolation structures, independent of whether these structures are trench extensions or formed directly beneath a planarized substrate surface.
摘要翻译：通过将沟槽蚀刻到与图案化掩模层对准的衬底的表面中来形成浅沟槽隔离（STI）结构。进行例如碳，氮或氧的离子注入，以形成从沟槽的底表面向下延伸的电绝缘层。通过植入这种扩展，可以获得具有更大有效纵横比的STI结构，这又可以在集成电路中允许更大的堆积密度。可以通过注入到衬底的区域中而不蚀刻沟槽来形成植入式隔离结构。以这种方式，可以消除沟槽蚀刻，电介质背面填充和平坦化操作。此外，植入区域可以由不同能量的多个植入物形成，以便获得多个通常连续的目标范围。可以使用各种质量或电荷的离子，以便在隔离结构中获得期望的注入深度和浓度分布，而不管这些结构是沟槽延伸还是直接形成在平坦化的衬底表面下方。

9. 发明授权

US06200883B1 Ion implantation method 失效
标题翻译：离子注入法
公开(公告)号：US06200883B1
公开(公告)日：2001-03-13
申请号：US08876593
申请日：1997-06-16
申请人： Mitchell C. Taylor , Babak Adibi , Majeed Ali Foad
发明人： Mitchell C. Taylor , Babak Adibi , Majeed Ali Foad
IPC分类号： H01L21265
CPC分类号： H01L21/26513 , C23C14/48 , H01L21/26566 , H01L21/2658
摘要： In ion implantation processes for forming junctions in semiconductor devices, a proportion of ions implant into the semiconductor material beyond the desired junction depth due to channelling along axes and planes of symmetry in the crystal. A method is provided in which ions are implanted at a series of different energies starting with a lower energy than that required for the desired junction depth. The initial amorphising of the surface regions of the semiconductor during the lower energy implantation reduces the channelling probability when the ions are subsequently implanted at the full energy resulting in a more sharply defined junction.
摘要翻译：在用于在半导体器件中形成结的离子注入工艺中，由于沿着晶体中的轴和对称平面的沟道，一部分离子注入半导体材料超过所需的结深度。提供了一种方法，其中以比所需结深度所需的能量低的能量开始以一系列不同的能量注入离子。在较低能量注入期间，半导体的表面区域的初始非晶化降低了当离子随后以全能量注入时产生更清晰界定的结的沟道概率。

10. 发明授权

US06936518B2 Creating shallow junction transistors 失效
标题翻译：创建浅结晶体管
公开(公告)号：US06936518B2
公开(公告)日：2005-08-30
申请号：US10761550
申请日：2004-01-21
申请人： Jack Hwang , Mitchell C. Taylor , Mark Y. Liu , Nick Lindert
发明人： Jack Hwang , Mitchell C. Taylor , Mark Y. Liu , Nick Lindert
IPC分类号： H01L21/223 , H01L21/28 , H01L21/336 , H01L21/8238
CPC分类号： H01L29/6659 , H01L21/2236 , H01L21/28035 , H01L21/823814
摘要： A polysilicon structure may be defined on a semiconductor substrate using plasma doping to dope the sidewalls and upper surface of the polysilicon material as well as the source drain extensions. Shortly after plasma doping, the structure may be encapsulated within a suitable capping layer to prevent the removal of the thin surface doped regions during subsequent semiconductor processing.
摘要翻译：可以使用等离子体掺杂在半导体衬底上限定多晶硅结构以掺杂多晶硅材料的侧壁和上表面以及源极漏极延伸。在等离子体掺杂之后不久，该结构可以封装在合适的覆盖层内，以防止在随后的半导体处理期间去除薄表面掺杂区域。

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