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    • 1. 发明授权
    • Low voltage operational amplifier input stage and method
    • 低压运算放大器输入级和方法
    • US5734296A
    • 1998-03-31
    • US618671
    • 1996-03-19
    • Robert N. DotsonRichard S. GriffithRobert L. Vyne
    • Robert N. DotsonRichard S. GriffithRobert L. Vyne
    • H03F3/30H03F3/343H03F3/45H03F3/16
    • H03F3/4508H03F3/3067H03F3/343H03F3/45076H03F2203/45028H03F2203/45182
    • Low voltage operational amplifier (10) operates in a voltage range of one to eight volts over a temperature range of 0.degree. to 70.degree. centigrade. Op amp input stage (12) uses N-channel depletion-mode MOSFETs to provide amplification of the differential input and maintain constant transconductance. Source follower MOSFET (13) provides unity gain in transferring the AC signal, STAGE-1 OUTPUT, to the base of current sinking transistor (18). Sink control circuit (14) and source control circuit (22) generate the base drive currents for transistors (18) and (24). The signal at the output of MOSFET (13) either causes the sink transistor (18) to sink current or the signal to be transposed by means of a translinear loop (16) and causes the source transistor (24) to source current. An output stage provides approximately fifty milliamps of current drive and is quiescent until the output driver is selected.
    • 低压运算放大器(10)在0至70℃的温度范围内工作在1-8伏特的电压范围内。 运算放大器输入级(12)使用N沟道耗尽型MOSFET来提供差分输入的放大并保持恒定的跨导。 源极跟随器MOSFET(13)在将AC信号STAGE-1 OUTPUT传送到电流吸收晶体管(18)的基极时提供单位增益。 漏极控制电路(14)和源极控制电路(22)产生用于晶体管(18)和(24)的基极驱动电流。 MOSFET(13)的输出处的信号或者使得宿晶体管(18)通过一个跨线性环路(16)吸收电流或者被转置的信号,并且使源极晶体管(24)产生电流。 输出级提供大约五十毫安的电流驱动器,并且静止,直到选择输出驱动器为止。
    • 2. 发明授权
    • Low voltage operational amplifier and method
    • 低压运算放大器及方法
    • US5699015A
    • 1997-12-16
    • US618544
    • 1996-03-19
    • Robert N. DotsonRichard S. GriffithThomas D. PettyRobert L. Vyne
    • Robert N. DotsonRichard S. GriffithThomas D. PettyRobert L. Vyne
    • H03F3/45H03F3/20H03F3/30H03F3/16H03F3/26
    • H03F3/3001
    • Low voltage operational amplifier (10) operates in a voltage range of one to eight volts over a temperature range of 0.degree. to 70.degree. centigrade. Op amp input stage (12) uses N-channel depletion-mode MOSFETs to provide amplification of the differential input and maintain constant transconductance. Source follower MOSFET (13) provides unity gain in transferring the AC signal, STAGE-1 OUTPUT, to the base of current sinking transistor (18). Sink control circuit (14) and source control circuit (22) generate the base drive currents for transistors (18) and (24). The signal at the output of MOSFET (13) either causes the sink transistor (18) to sink current or the signal to be transposed by means of a translinear loop (16) and causes the source transistor (24) to source current.
    • 低压运算放大器(10)在0至70℃的温度范围内工作在1-8伏特的电压范围内。 运算放大器输入级(12)使用N沟道耗尽型MOSFET来提供差分输入的放大并保持恒定的跨导。 源极跟随器MOSFET(13)在将AC信号STAGE-1 OUTPUT传送到电流吸收晶体管(18)的基极时提供单位增益。 漏极控制电路(14)和源极控制电路(22)产生用于晶体管(18)和(24)的基极驱动电流。 MOSFET(13)的输出处的信号或者使得宿晶体管(18)通过一个跨线性环路(16)吸收电流或被转置的信号,并且使源极晶体管(24)发射电流。
    • 3. 发明授权
    • Method and circuit for reducing offset voltages for a differential input
stage
    • 用于降低差分输入级的失调电压的方法和电路
    • US5726597A
    • 1998-03-10
    • US706095
    • 1996-08-30
    • Thomas D. PettyRichard S. GriffithRobert L. VyneRobert N. Dotson
    • Thomas D. PettyRichard S. GriffithRobert L. VyneRobert N. Dotson
    • H03F3/45H03K5/24H03K5/22
    • H03K5/2481H03F3/45762H03F2203/45342
    • A trim circuit (10) and method of reducing offset voltages in a differential input stage. The differential input transistors (32 and 42) have separate bulk terminals for receiving a voltage to compensate for the input offset voltage. A current source (60) supplies a static current to the offset compensation circuit for generating a bias voltage at node (55). The transistors (64 and 66) receive a voltage at input terminals (30 and 40) and supply an additional current to an offset compensation circuit (20). A switch circuit (50) has switch pairs (52, 56, and 54, 58) for transferring a voltage to the bulk terminal of one of the differential transistors (32 and 42) while grounding the bulk terminal of the other transistor. The differential voltage supplied across the bulk terminals of transistors (32 and 42) changes the threshold voltage of the transistors reducing the offset voltage of the input stage.
    • 一种微调电路(10)和减小差分输入级中的偏移电压的方法。 差分输入晶体管(32和42)具有单独的体积端子,用于接收电压以补偿输入偏移电压。 电流源(60)将静态电流提供给偏移补偿电路,用于在节点(55)处产生偏置电压。 晶体管(64和66)在输入端(30和40)处接收电压,并向偏移补偿电路(20)提供附加电流。 开关电路(50)具有用于将电压传送到差分晶体管(32和42)中的一个的体电极的开关对(52,56和54,58),同时接地另一个晶体管的体端子。 在晶体管(32和42)的批量端子之间提供的差分电压改变了晶体管的阈值电压,从而降低了输入级的偏移电压。
    • 4. 发明授权
    • Pulse stretching and level shifting circuit
    • 脉冲拉伸和电平移位电路
    • US4501974A
    • 1985-02-26
    • US449035
    • 1982-12-13
    • Ira MillerMichael W. NullRobert N. Dotson
    • Ira MillerMichael W. NullRobert N. Dotson
    • H03K5/003H03K5/04H03K17/56H03K3/017
    • H03K5/003H03K5/04
    • A pulse stretching integrated circuit includes an on-chip capacitor. A first transistor means including an input transistor and an emitter follower transistor supplies a charging current to the capacitor so as to charge it to a first voltage when an input signal pulse is in a first logical state. A differential transistor pair has a first input coupled to the emitter follower transistor and to the capacitor and has a second input coupled to a reference voltage for generating a first output when the capacitor voltage is less than the reference voltage and for generating a second output when the capacitive voltage is greater than the reference voltage. An additional transistor is coupled to the capacitor for discharging the capacitor when the input signal pulse is in a second logical state causing the voltage at the first input of the differential pair to fall below the reference voltage.
    • 脉冲拉伸集成电路包括片上电容器。 包括输入晶体管和射极跟随器晶体管的第一晶体管装置向电容器提供充电电流,以便当输入信号脉冲处于第一逻辑状态时将其充电到第一电压。 差分晶体管对具有耦合到射极跟随器晶体管和电容器的第一输入,并且具有耦合到参考电压的第二输入,用于当电容器电压小于参考电压时产生第一输出,并且当第 电容电压大于参考电压。 当输入信号脉冲处于第二逻辑状态时,附加晶体管耦合到电容器,用于对电容器进行放电,导致差分对的第一输入处的电压低于参考电压。