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1. 发明授权

US08633547B2 Structure for spanning gap in body-bias voltage routing structure 有权
标题翻译：体偏电压布线结构跨越间隙的结构
公开(公告)号：US08633547B2
公开(公告)日：2014-01-21
申请号：US12140197
申请日：2008-06-16
申请人： Robert Masleid , James B. Burr , Michael Pelham
发明人： Robert Masleid , James B. Burr , Michael Pelham
IPC分类号： H01L29/76
CPC分类号： H01L23/535 , H01L23/52 , H01L23/585 , H01L27/0218 , H01L27/092 , H01L2924/0002 , H01L2924/00
摘要： Structures for spanning gap in body-bias voltage routing structure. In an embodiment, a structure is comprised of at least one metal wire.
摘要翻译：体偏电压布线结构跨越间隙的结构。在一个实施例中，结构由至少一根金属线构成。

2. 发明授权

US07388260B1 Structure for spanning gap in body-bias voltage routing structure 有权
标题翻译：体偏电压布线结构跨越间隙的结构
公开(公告)号：US07388260B1
公开(公告)日：2008-06-17
申请号：US10816269
申请日：2004-03-31
申请人： Robert P. Masleid , James B. Burr , Michael Pelham
发明人： Robert P. Masleid , James B. Burr , Michael Pelham
IPC分类号： H01L29/76
CPC分类号： H01L23/535 , H01L23/52 , H01L23/585 , H01L27/0218 , H01L27/092 , H01L2924/0002 , H01L2924/00
摘要： Structures for spanning gap in body-bias voltage routing structure. In an embodiment, a structure is comprised of at least one metal wire.
摘要翻译：体偏电压布线结构跨越间隙的结构。在一个实施例中，结构由至少一根金属线构成。

3. 发明授权

US08146037B2 Method for generating a deep N-well pattern for an integrated circuit design 失效
标题翻译：用于生成用于集成电路设计的深N阱图案的方法
公开(公告)号：US08146037B2
公开(公告)日：2012-03-27
申请号：US12544149
申请日：2009-08-19
申请人： Michael Pelham , James B. Burr
发明人： Michael Pelham , James B. Burr
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for the design and layout for a patterned deep N-well. A tile is specified as a fundamental building block for the deep N-well pattern. The tile comprises a first element on a first layer and may comprise a second element on a second layer. A two dimensional region is covered with an array of contiguous tiles, with the elements on each layer connecting with elements of adjacent tiles to form extended shapes. The array may be converted to a collection of sub-arrays through the removal of tiles. The array or collection of sub-arrays may be merged to produce a first layer pattern and second layer pattern. Design rule checks may be applied to verify the pattern. The first layer shapes and second layer shapes may be edited. The first layer shapes and the second layer shapes may then be combined to produce a deep N-well pattern.
摘要翻译：一种用于图案化深N阱的设计和布局的方法。将瓷砖指定为深N型图案的基本构建块。瓦片包括在第一层上的第一元件，并且可以包括在第二层上的第二元件。二维区域覆盖有连续瓦片阵列，每层上的元素与相邻瓦片的元素连接以形成延伸形状。阵列可以通过去除瓦片而转换为子阵列的集合。子阵列的阵列或集合可以被合并以产生第一层图案和第二层图案。可以应用设计规则检查来验证模式。可以编辑第一层形状和第二层形状。然后可以组合第一层形状和第二层形状以产生深N阱图案。

4. 发明申请

US20090313591A1 METHOD FOR GENERATING A DEEP N-WELL PATTERN FOR AN INTEGRATED CIRCUIT DESIGN 失效
标题翻译：用于生成用于集成电路设计的深层N阱图案的方法
公开(公告)号：US20090313591A1
公开(公告)日：2009-12-17
申请号：US12544149
申请日：2009-08-19
申请人： Michael Pelham , James B. Burr
发明人： Michael Pelham , James B. Burr
IPC分类号： G06F17/50
CPC分类号： G06F17/5068
摘要： A method for the design and layout for a patterned deep N-well. A tile is specified as a fundamental building block for the deep N-well pattern. The tile comprises a first element on a first layer and may comprise a second element on a second layer. A two dimensional region is covered with an array of contiguous tiles, with the elements on each layer connecting with elements of adjacent tiles to form extended shapes. The array may be converted to a collection of sub-arrays through the removal of tiles. The array or collection of sub-arrays may be merged to produce a first layer pattern and second layer pattern. Design rule checks may be applied to verify the pattern. The first layer shapes and second layer shapes may be edited. The first layer shapes and the second layer shapes may then be combined to produce a deep N-well pattern.
摘要翻译：一种用于图案化深N阱的设计和布局的方法。将瓷砖指定为深N型图案的基本构建块。瓦片包括在第一层上的第一元件，并且可以包括在第二层上的第二元件。二维区域覆盖有连续瓦片阵列，每层上的元素与相邻瓦片的元素连接以形成延伸形状。阵列可以通过去除瓦片而转换为子阵列的集合。子阵列的阵列或集合可以被合并以产生第一层图案和第二层图案。可以应用设计规则检查来验证模式。可以编辑第一层形状和第二层形状。然后可以组合第一层形状和第二层形状以产生深N阱图案。

5. 发明申请

US20080246110A1 STRUCTURE FOR SPANNING GAP IN BODY-BIAS VOLTAGE ROUTING STRUCTURE 有权
标题翻译： BODY-BIAS电压路由结构中的扫描缝隙结构
公开(公告)号：US20080246110A1
公开(公告)日：2008-10-09
申请号：US12140197
申请日：2008-06-16
申请人： Robert P. Masleid , James B. Burr , Michael Pelham
发明人： Robert P. Masleid , James B. Burr , Michael Pelham
IPC分类号： H01L23/52
CPC分类号： H01L23/535 , H01L23/52 , H01L23/585 , H01L27/0218 , H01L27/092 , H01L2924/0002 , H01L2924/00
摘要： Structures for spanning gap in body-bias voltage routing structure. In an embodiment, a structure is comprised of at least one metal wire.
摘要翻译：体偏电压布线结构跨越间隙的结构。在一个实施例中，结构由至少一根金属线构成。

6. 发明授权

US07049699B1 Low RC structures for routing body-bias voltage 失效
标题翻译：低RC结构用于路由体偏置电压
公开(公告)号：US07049699B1
公开(公告)日：2006-05-23
申请号：US10712129
申请日：2003-11-12
申请人： Robert Paul Masleid , James B. Burr , Michael Pelham
发明人： Robert Paul Masleid , James B. Burr , Michael Pelham
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L23/5286 , H01L27/0203 , H01L2924/0002 , H01L2924/00
摘要： Low RC structures for routing body-bias voltage are provided and described. These low RC structures are comprised of a deep well structure coupled to a metal structure.
摘要翻译：提供和描述用于布置体偏置电压的低RC结构。这些低RC结构由耦合到金属结构的深阱结构组成。

7. 发明授权

US08298896B2 Formation of a super steep retrograde channel 有权
标题翻译：形成一个超级陡峭的逆行通道
公开(公告)号：US08298896B2
公开(公告)日：2012-10-30
申请号：US13214593
申请日：2011-08-22
申请人： James B. Burr , Archisman Bagchi , Jawad Nasrullah
发明人： James B. Burr , Archisman Bagchi , Jawad Nasrullah
IPC分类号： H01L21/336
CPC分类号： H01L21/26513 , H01L29/1033 , H01L29/1083 , H01L29/7833
摘要： Systems and methods for raised source/drain with super steep retrograde channel are described. In accordance with a first embodiment, a semiconductor device comprises a substrate comprising a surface and a gate oxide disposed above the surface comprising a gate oxide thickness. The semiconductor device further comprises a super steep retrograde channel region formed at a depth below the surface. The depth is about ten to thirty times the gate oxide thickness. Embodiments may provide a more desirable body biasing voltage to threshold voltage characteristic than is available under the conventional art.
摘要翻译：描述了具有超陡逆行通道的升高源极/漏极的系统和方法。根据第一实施例，半导体器件包括包括表面的衬底和设置在包括栅极氧化物厚度的表面之上的栅极氧化物。半导体器件还包括形成在表面下方深度的超陡逆行通道区域。深度约为栅极氧化物厚度的十至三十倍。实施例可以提供比常规技术中可获得的阈值电压特性更理想的主体偏置电压。

8. 发明授权

US07949864B1 Balanced adaptive body bias control 有权
标题翻译：平衡自适应体偏置控制
公开(公告)号：US07949864B1
公开(公告)日：2011-05-24
申请号：US11238446
申请日：2005-09-28
申请人： Vjekoslav Svilan , James B. Burr
发明人： Vjekoslav Svilan , James B. Burr
IPC分类号： G06F1/32 , G06F1/24
CPC分类号： G06F1/3203 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Systems and methods of balanced adaptive body bias control. In accordance with a first embodiment of the present invention, a method of balanced adaptive body bias control comprises determining a desirable dynamic condition for circuitry of an integrated circuit. A first dynamic indicator corresponding to the desirable dynamic condition is accessed. Second and third dynamic indicators of the integrated circuit are accessed. A first body biasing voltage is adjusted by an increment so as to change the first dynamic indicator in the direction of the desirable dynamic condition. A second body biasing voltage is adjusted based on a relationship between the second dynamic indicator and the third dynamic indicator.
摘要翻译：平衡自适应体偏置控制的系统和方法。根据本发明的第一实施例，平衡自适应体偏置控制的方法包括确定用于集成电路的电路的期望的动态条件。访问对应于期望的动态条件的第一动态指示符。访问集成电路的第二和第三动态指示器。通过增量来调整第一体偏置电压，以便在期望的动态条件的方向上改变第一动态指示器。基于第二动态指示器和第三动态指示器之间的关系来调整第二身体偏置电压。

9. 发明申请

US20110086478A1 SYSTEMS AND METHODS FOR INTEGRATED CIRCUITS COMPRISING MULTIPLE BODY BIASING DOMAINS 有权
标题翻译：包含多个体积偏移域的集成电路的系统和方法
公开(公告)号：US20110086478A1
公开(公告)日：2011-04-14
申请号：US12968032
申请日：2010-12-14
申请人： Kleanthes G. Koniaris , Robert Paul Masleid , James B. Burr
发明人： Kleanthes G. Koniaris , Robert Paul Masleid , James B. Burr
IPC分类号： H01L21/8238
CPC分类号： H03K19/0027 , H03K2217/0018
摘要： Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.
摘要翻译：包括多个主体偏置域的集成电路的系统和方法。根据第一实施例，半导体结构包括第一类型材料的衬底。包括第二类型材料的壁的第一封闭结构从衬底的表面延伸到第一深度。所述第二类型材料的下面并耦合到所述封闭结构的平面深井从所述第一深度延伸到第二深度。所述第二类型材料的封闭结构和平面深孔形成第一类型材料的电隔离区域。第二类型半导体器件设置成从第一类型材料的电隔离区域接收第一主体偏置电压。形成在第一类型材料的电隔离区域内的第二类型材料的阱，并且设置第一类型半导体器件以从第二类型材料的阱接收第二主体偏置电压。

10. 发明申请

US20100321098A1 SYSTEMS AND METHODS FOR INTEGRATED CIRCUITS COMPRISING MULTIPLE BODY BIASING DOMAINS 有权
标题翻译：包含多个体积偏移域的集成电路的系统和方法
公开(公告)号：US20100321098A1
公开(公告)日：2010-12-23
申请号：US12873062
申请日：2010-08-31
申请人： Kleanthes G. Koniaris , Robert Paul Masleid , James B. Burr
发明人： Kleanthes G. Koniaris , Robert Paul Masleid , James B. Burr
IPC分类号： H03K3/01
CPC分类号： H01L21/823892 , H01L21/743 , H01L21/761 , H01L21/823878 , H01L29/78
摘要： Systems and methods for integrated circuits comprising multiple body biasing domains. In accordance with a first embodiment of the present invention, a semiconductor structure comprises a substrate of first type material. A first closed structure comprising walls of second type material extends from a surface of the substrate to a first depth. A planar deep well of said second type material underlying and coupled to the closed structure extends from the first depth to a second depth. The closed structure and the planar deep well of said second type material form an electrically isolated region of the first type material. A second-type semiconductor device is disposed to receive a first body biasing voltage from the electrically isolated region of the first type material. A well of the second-type material within the electrically isolated region of the first type material is formed and a first-type semiconductor device is disposed to receive a second body biasing voltage from the well of second-type material.
摘要翻译：包括多个主体偏置域的集成电路的系统和方法。根据本发明的第一实施例，半导体结构包括第一类型材料的衬底。包括第二类型材料的壁的第一封闭结构从衬底的表面延伸到第一深度。所述第二类型材料的下面并耦合到所述封闭结构的平面深井从所述第一深度延伸到第二深度。所述第二类型材料的封闭结构和平面深孔形成第一类型材料的电隔离区域。第二类型半导体器件设置成从第一类型材料的电隔离区域接收第一主体偏置电压。形成在第一类型材料的电隔离区域内的第二类型材料的阱，并且设置第一类型半导体器件以从第二类型材料的阱接收第二主体偏置电压。

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