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1. 发明授权

US5872040A Method for fabricating a thin film capacitor 失效
标题翻译：薄膜电容器的制造方法
公开(公告)号：US5872040A
公开(公告)日：1999-02-16
申请号：US862994
申请日：1997-05-27
申请人： Robert John Wojnarowski , James Wilson Rose , Ernest Wayne Balch , Leonard Richard Douglas , Evan Taylor Downey , Michael Gdula
发明人： Robert John Wojnarowski , James Wilson Rose , Ernest Wayne Balch , Leonard Richard Douglas , Evan Taylor Downey , Michael Gdula
IPC分类号： H01C17/12 , H01C17/24 , H01G4/06 , H01G4/08 , H05K1/16 , H01L21/20
CPC分类号： H01C17/24 , H01C17/12 , H01C17/2416 , H01G4/06 , H01G4/08 , H05K1/167 , Y10S148/136
摘要： A method is provided for the manufacture of precision electronic components such as resistors, inductors, and capacitors on a polymer or ceramic surface. The electronic components can be deposited and trimmed to precise or matched values without having precise depositions of all of the pre-patterned materials. Thin film electronic components are deposited on a surface, parameter values are measured or estimated, a correction offset file is generated, and the components are trimmed using adaptive lithography to a very close tolerance. A computer program can be used to enable the adjustment of electronic components by techniques such as changing the physical length of an inductor coil or resistor lead, or by changing a capacitor plate area.
摘要翻译：提供了一种用于在聚合物或陶瓷表面上制造诸如电阻器，电感器和电容器的精密电子部件的方法。电子部件可以沉积和修整成精确或匹配的值，而不会精确沉积所有预图案化材料。薄膜电子部件沉积在表面上，测量或估计参数值，产生校正偏移文件，并且使用适应光刻将组件修剪到非常接近的公差。可以使用计算机程序来实现电子部件的调整，例如改变电感线圈或电阻器引线的物理长度，或者改变电容器板面积。

2. 发明授权

US5683928A Method for fabricating a thin film resistor 失效
标题翻译：制造薄膜电阻的方法
公开(公告)号：US5683928A
公开(公告)日：1997-11-04
申请号：US349278
申请日：1994-12-05
申请人： Robert John Wojnarowski , James Wilson Rose , Ernest Wayne Balch , Leonard Richard Douglas , Evan Taylor Downey , Michael Gdula
发明人： Robert John Wojnarowski , James Wilson Rose , Ernest Wayne Balch , Leonard Richard Douglas , Evan Taylor Downey , Michael Gdula
IPC分类号： H01C17/12 , H01C17/24 , H01G4/06 , H01G4/08 , H05K1/16 , H01L21/70
CPC分类号： H01C17/24 , H01C17/12 , H01C17/2416 , H01G4/06 , H01G4/08 , H05K1/167 , Y10S148/136
摘要： A method is provided for the manufacture of precision electronic components such as resistors, inductors, and capacitors on a polymer or ceramic surface. The electronic components can be deposited and trimmed to precise or matched values without having precise depositions of all of the pre-patterned materials. Thin film electronic components are deposited on a surface, parameter values are measured or estimated, a correction offset file is generated, and the components are trimmed using adaptive lithography to a very close tolerance. A computer program can be used to enable the adjustment of electronic components by techniques such as changing the physical length of an inductor coil or resistor lead, or by changing a capacitor plate area.
摘要翻译：提供了一种用于在聚合物或陶瓷表面上制造诸如电阻器，电感器和电容器的精密电子部件的方法。电子部件可以沉积和修整成精确或匹配的值，而不会精确沉积所有预图案化材料。薄膜电子部件沉积在表面上，测量或估计参数值，产生校正偏移文件，并且使用适应光刻将组件修剪到非常接近的公差。可以使用计算机程序来实现电子部件的调整，例如改变电感线圈或电阻器引线的物理长度，或者改变电容器板面积。

3. 发明授权

US6040226A Method for fabricating a thin film inductor 有权
标题翻译：薄膜电感器的制造方法
公开(公告)号：US6040226A
公开(公告)日：2000-03-21
申请号：US177908
申请日：1998-10-23
申请人： Robert John Wojnarowski , James Wilson Rose , Ernest Wayne Balch , Leonard Richard Douglas , Evan Taylor Downey , Michael Gdula
发明人： Robert John Wojnarowski , James Wilson Rose , Ernest Wayne Balch , Leonard Richard Douglas , Evan Taylor Downey , Michael Gdula
IPC分类号： H01L21/20
CPC分类号： H01L21/20
摘要： A method is provided for the manufacture of precision electronic components such as resistors, inductors, and capacitors on a polymer or ceramic surface. The electronic components can be deposited and trimmed to precise or matched values without having precise depositions of all of the pre-patterned materials. Thin film electronic components are deposited on a surface, parameter values are measured or estimated, a correction offset file is generated, and the components are trimmed using adaptive lithography to a very close tolerance. A computer program can be used to enable the adjustment of electronic components by techniques such as changing the physical length of an inductor coil or resistor lead, or by changing a capacitor plate area.
摘要翻译：提供了一种用于在聚合物或陶瓷表面上制造诸如电阻器，电感器和电容器的精密电子部件的方法。电子部件可以沉积和修整成精确或匹配的值，而不会精确沉积所有预图案化材料。薄膜电子部件沉积在表面上，测量或估计参数值，产生校正偏移文件，并且使用适应光刻将组件修剪到非常接近的公差。可以使用计算机程序来实现电子部件的调整，例如改变电感线圈或电阻器引线的物理长度，或者改变电容器板面积。

4. 发明授权

US06410356B1 Silicon carbide large area device fabrication apparatus and method 失效
标题翻译：碳化硅大面积器件制造装置及方法
公开(公告)号：US06410356B1
公开(公告)日：2002-06-25
申请号：US09520751
申请日：2000-03-07
申请人： Robert John Wojnarowski , Ernest Wayne Balch , Leonard Richard Douglas
发明人： Robert John Wojnarowski , Ernest Wayne Balch , Leonard Richard Douglas
IPC分类号： H01L2166
CPC分类号： H01L22/20 , H01L23/34 , H01L2224/92144 , H01L2924/014 , H01L2924/1301 , H01L2924/00
摘要： A method for interconnecting high-temperature silicon carbide (SiC) devices enables such high-temperature devices to be used in fabricating electronic circuits of significant scale. This method comprises empirically measuring operational characteristics of a plurality of the devices to be interconnected, the operational characteristics comprising devices which are measured to be non-working and devices which are measured to be working; characterizing the operational characteristics in an operational characteristics map; designing interconnection paths between and among the devices that are characterized to be working by the operational characteristics map; and excluding from the interconnection paths, devices that are characterized to be non-working by the operational characteristics map. A preferred embodiment of this method further includes disposing a temporary polymer layer over the devices; forming via holes through the temporary polymer layer, to bonding pads of the devices; applying a current-balancing resistive metal over the temporary polymer layer; establishing connections between the current-balancing resistive metal and the bonding pads; designing the interconnection paths between and among the working devices by patterning the current-balancing resistive metal based on the operational characteristics map; and removing the temporary polymer layer.
摘要翻译：用于互连高温碳化硅（SiC）器件的方法使得这种高温器件能够用于制造具有显着规模的电子电路。该方法包括经验地测量待互连的多个设备的操作特性，操作特性包括被测量为不工作的设备和被测量为工作的设备; 表征操作特征图中的操作特性; 设计特征在于通过操作特征图工作的设备之间的互连路径; 并且从互连路径中排除特征在于通过操作特性图不工作的设备。该方法的优选实施例还包括在器件上设置临时聚合物层; 通过所述临时聚合物层形成通孔到所述装置的焊盘; 在临时聚合物层上施加电流平衡电阻金属; 建立电流平衡电阻金属和焊盘之间的连接; 通过基于操作特性图构图电流平衡电阻金属来设计工作装置之间和之间的互连路径; 并除去临时聚合物层。

5. 发明授权

US06603145B2 High temperature circuit apparatus 失效
公开(公告)号：US06603145B2
公开(公告)日：2003-08-05
申请号：US10136626
申请日：2002-05-02
申请人： Robert John Wojnarowski , Ernest Wayne Balch , Leonard Richard Douglas
发明人： Robert John Wojnarowski , Ernest Wayne Balch , Leonard Richard Douglas
IPC分类号： H01L310312
CPC分类号： H01L22/20 , H01L23/34 , H01L2224/92144 , H01L2924/014 , H01L2924/1301 , H01L2924/00
摘要： A method for interconnecting high-temperature silicon carbide (SiC) devices enables such high-temperature devices to be used in fabricating electronic circuits of significant scale. This method comprises empirically measuring operational characteristics of a plurality of the devices to be interconnected, the operational characteristics comprising devices which are measured to be non-working and devices which are measured to be working; characterizing the operational characteristics in an operational characteristics map; designing interconnection paths between and among the devices that are characterized to be working by the operational characteristics map; and excluding from the interconnection paths, devices that are characterized to be non-working by the operational characteristics map. A preferred embodiment of this method further includes disposing a temporary polymer layer over the devices; forming via holes through the temporary polymer layer, to bonding pads of the devices; applying a current-balancing resistive metal over the temporary polymer layer; establishing connections between the current-balancing resistive metal and the bonding pads; designing the interconnection paths between and among the working devices by patterning the current-balancing resistive metal based on the operational characteristics map; and removing the temporary polymer layer.

6. 发明授权

US06396153B2 Circuit chip package and fabrication method 有权
标题翻译：电路芯片封装及制作方法
公开(公告)号：US06396153B2
公开(公告)日：2002-05-28
申请号：US09768598
申请日：2001-01-25
申请人： Raymond Albert Fillion , Ernest Wayne Balch , Ronald Frank Kolc , William Edward Burdick, Jr. , Robert John Wojnarowski , Leonard Richard Douglas , Thomas Bert Gorczyca
发明人： Raymond Albert Fillion , Ernest Wayne Balch , Ronald Frank Kolc , William Edward Burdick, Jr. , Robert John Wojnarowski , Leonard Richard Douglas , Thomas Bert Gorczyca
IPC分类号： H01L2348
CPC分类号： H01L24/48 , H01L21/4853 , H01L21/486 , H01L23/5389 , H01L24/11 , H01L24/19 , H01L2224/0401 , H01L2224/05624 , H01L2224/13099 , H01L2224/24227 , H01L2224/4824 , H01L2224/48463 , H01L2224/85399 , H01L2224/92144 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/0103 , H01L2924/01073 , H01L2924/014 , H01L2924/04953 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： One method for packaging at least one circuit chip includes: providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on second side metallized portions of the second side and not on second side non-metallized portions of the second side, at least one substrate via extending from the first side to one of the second side metallized portions, and at least one chip via extending from the first side to one of the second side non-metallized portions; positioning the at least one circuit chip on the second side with at least one chip pad of the at least one circuit chip being aligned with the at least one chip via; and patterning connection metallization on selected portions of the first side of the interconnect layer and in the vias so as to extend to the at least one second side metallized portion and to the at least one chip pad. In related embodiments vias are pre-metallized and coupled to chip pads of the circuit chips by an electrically conductive binder. Thin film passive components and multilayer interconnections can additionally be incorporated into the package.
摘要翻译：一种用于封装至少一个电路芯片的方法包括：提供包括具有第一侧和第二侧的绝缘材料的互连层，在第二侧的第二侧金属化部分上而不是在第二侧非金属化部分上图案化的初始金属化第二侧，至少一个从第一侧延伸到第二侧金属化部分之一的衬底通孔;以及至少一个芯片通孔，其从第一侧延伸到第二侧非金属化部分之一; 将所述至少一个电路芯片定位在所述第二侧上，所述至少一个电路芯片的至少一个芯片焊盘与所述至少一个芯片通孔对准; 以及在所述互连层的第一侧和所述通孔的选定部分上图案化连接金属化，以便延伸到所述至少一个第二侧金属化部分和所述至少一个芯片焊盘。在相关实施例中，通孔被预先金属化并且通过导电粘合剂耦合到电路芯片的芯片焊盘。薄膜无源元件和多层互连可另外包含在封装中。

7. 发明授权

US06242282B1 Circuit chip package and fabrication method 有权
公开(公告)号：US06242282B1
公开(公告)日：2001-06-05
申请号：US09411101
申请日：1999-10-04
申请人： Raymond Albert Fillion , Ernest Wayne Balch , Ronald Frank Kolc , William Edward Burdick, Jr. , Robert John Wojnarowski , Leonard Richard Douglas , Thomas Bert Gorczyca
发明人： Raymond Albert Fillion , Ernest Wayne Balch , Ronald Frank Kolc , William Edward Burdick, Jr. , Robert John Wojnarowski , Leonard Richard Douglas , Thomas Bert Gorczyca
IPC分类号： H01L2144
CPC分类号： H01L24/48 , H01L21/4853 , H01L21/486 , H01L23/5389 , H01L24/11 , H01L24/19 , H01L2224/0401 , H01L2224/05624 , H01L2224/13099 , H01L2224/24227 , H01L2224/4824 , H01L2224/48463 , H01L2224/85399 , H01L2224/92144 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01029 , H01L2924/0103 , H01L2924/01073 , H01L2924/014 , H01L2924/04953 , H01L2924/12042 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： One method for packaging at least one circuit chip includes: providing an interconnect layer including insulative material having a first side and a second side, initial metallization patterned on second side metallized portions of the second side and not on second side non-metallized portions of the second side, at least one substrate via extending from the first side to one of the second side metallized portions, and at least one chip via extending from the first side to one of the second side non-metallized portions; positioning the at least one circuit chip on the second side with at least one chip pad of the at least one circuit chip being aligned with the at least one chip via; and patterning connection metallization on selected portions of the first side of the interconnect layer and in the vias so as to extend to the at least one second side metallized portion and to the at least one chip pad. In related embodiments vias are pre-metallized and coupled to chip pads of the circuit chips by an electrically conductive binder. Thin film passive components and multilayer interconnections can additionally be incorporated into the package.

8. 发明授权

US5675310A Thin film resistors on organic surfaces 失效
标题翻译：有机表面上的薄膜电阻
公开(公告)号：US5675310A
公开(公告)日：1997-10-07
申请号：US349228
申请日：1994-12-05
申请人： Robert John Wojnarowski , James Wilson Rose , Kyung Wook Paik , Michael Gdula
发明人： Robert John Wojnarowski , James Wilson Rose , Kyung Wook Paik , Michael Gdula
IPC分类号： H01C1/032 , H01C7/00 , H01C17/075 , H01L23/538 , H05K1/02 , H05K1/16 , H05K3/38 , H01C1/012 , H01L27/00
CPC分类号： H05K1/167 , H01C1/032 , H01C17/075 , H01C7/006 , H01L2224/73204 , H01L2224/82039 , H01L23/5389 , H01L2924/01077 , H05K1/0268 , H05K2201/0317 , H05K2203/0361 , H05K2203/171 , H05K3/388 , Y10S148/136 , Y10T29/49101
摘要： A method for fabricating a thin film resistor comprises applying a tantalum nitride layer over a dielectric layer, applying a metallization layer over the tantalum nitride layer, and patterning the metallization layer with a first portion of the metallization layer situated apart from a second portion of the metallization layer and both the first and second portions being at least partially situated on the tantalum nitride layer. In one embodiment, after patterning the metallization layer, the resistance value between the first and second portions of the metallization layer is determined and compared to a predetermined resistance value, and at least one of the first and second portions is trimmed to obtain a modified resistance value between the first and second portions that is closer to the predetermined resistance value than the determined resistance value.
摘要翻译：一种用于制造薄膜电阻器的方法包括在介电层上施加氮化钽层，在氮化钽层上施加金属化层，以及使金属化层的第一部分与金属化层的第二部分分开，金属化层，并且第一和第二部分至少部分地位于氮化钽层上。在一个实施例中，在图案化金属化层之后，确定金属化层的第一和第二部分之间的电阻值并将其与预定电阻值进行比较，并且修剪第一和第二部分中的至少一个以获得改良电阻第一和第二部分之间的值比所确定的电阻值更接近于预定电阻值。

9. 发明授权

US5849623A Method of forming thin film resistors on organic surfaces 失效
标题翻译：在有机表面上形成薄膜电阻的方法
公开(公告)号：US5849623A
公开(公告)日：1998-12-15
申请号：US862672
申请日：1997-05-23
申请人： Robert John Wojnarowski , James Wilson Rose , Kyung Wook Paik , Michael Gdula
发明人： Robert John Wojnarowski , James Wilson Rose , Kyung Wook Paik , Michael Gdula
IPC分类号： H01C1/032 , H01C7/00 , H01C17/075 , H01L23/538 , H05K1/02 , H05K1/16 , H05K3/38 , H01L21/20
CPC分类号： H05K1/167 , H01C1/032 , H01C17/075 , H01C7/006 , H01L2224/73204 , H01L2224/82039 , H01L23/5389 , H01L2924/01077 , H05K1/0268 , H05K2201/0317 , H05K2203/0361 , H05K2203/171 , H05K3/388 , Y10S148/136 , Y10T29/49101
摘要： A method for fabricating a thin film resistor comprises applying a tantalum nitride layer over a dielectric layer, applying a metallization layer over the tantalum nitride layer, and patterning the metallization layer with a first portion of the metallization layer situated apart from a second portion of the metallization layer and both the first and second portions being at least partially situated on the tantalum nitride layer. In one embodiment, after patterning the metallization layer, the resistance value between the first and second portions of the metallization layer is determined and compared to a predetermined resistance value, and at least one of the first and second portions is trimmed to obtain a modified resistance value between the first and second portions that is closer to the predetermined resistance value than the determined resistance value.
摘要翻译：一种用于制造薄膜电阻器的方法包括在介电层上施加氮化钽层，在氮化钽层上施加金属化层，以及使金属化层的第一部分与金属化层的第二部分分开，金属化层，并且第一和第二部分至少部分地位于氮化钽层上。在一个实施例中，在图案化金属化层之后，确定金属化层的第一和第二部分之间的电阻值并将其与预定电阻值进行比较，并且修剪第一和第二部分中的至少一个以获得改良电阻第一和第二部分之间的值比所确定的电阻值更接近于预定电阻值。

10. 发明授权

US5897728A Integrated circuit test structure and test process 失效
标题翻译：集成电路测试结构和测试过程
公开(公告)号：US5897728A
公开(公告)日：1999-04-27
申请号：US759691
申请日：1991-09-06
申请人： Herbert Stanley Cole , James Wilson Rose , Robert John Wojnarowski , Charles William Eichelberger
发明人： Herbert Stanley Cole , James Wilson Rose , Robert John Wojnarowski , Charles William Eichelberger
IPC分类号： G01R31/30 , G01R1/04 , G01R31/00 , G01R31/28 , H01L21/60 , H01L21/66 , H01L23/538 , H01L23/58 , B32B32/00
CPC分类号： G01R1/04 , G01R31/2863 , H01L22/32 , H01L23/5389 , H01L24/05 , H01L24/24 , H01L24/48 , H01L24/82 , H01L24/85 , H01L2224/04042 , H01L2224/05599 , H01L2224/05624 , H01L2224/24227 , H01L2224/32225 , H01L2224/451 , H01L2224/48091 , H01L2224/48137 , H01L2224/4823 , H01L2224/48465 , H01L2224/48471 , H01L2224/73265 , H01L2224/73267 , H01L2224/82039 , H01L2224/85205 , H01L24/45 , H01L2924/00014 , H01L2924/01006 , H01L2924/01007 , H01L2924/01013 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01039 , H01L2924/014 , H01L2924/12042 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/15312 , H01L2924/15787 , H01L2924/30105
摘要： For fully testing and burning-in an integrated circuit chip before it is incorporated into a high density interconnect or other standard hybrid bare chip circuit, a temporary test substrate having pins extending therethrough holds the chip within a cavity. Chip pads are electrically connected with the pins to create a package that can be tested using commercially available testing and burn-in devices. After testing, the chip is retrieved from the test structure undamaged. In using HDI techniques to interconnect the chip with the pins, metal-filled vias in a polymer layer overlying the temporary test substrate electrically connect the chip to the pins through a metal interconnect pattern on the polymer layer. In another embodiment, the chip is interconnected with the pins through wire bonds. Metal-filled vias pass through an insulative coating on the chip and make electrical contact with the chip pad. A temporary buffer pad connected to a respective via and offset from the chip pad connected to that via comprises a wire-bonding site.
摘要翻译：为了在将集成电路芯片并入高密度互连或其他标准混合裸芯片电路之前对其进行完全测试和烧录，具有延伸穿过的引脚的临时测试基板将芯片保持在空腔内。芯片焊盘与引脚电连接以产生可以使用市售测试和老化设备进行测试的封装。测试后，芯片从测试结构中检索到无损坏。在使用HDI技术将芯片与引脚互连时，覆盖临时测试基板的聚合物层中的金属填充的通孔通过聚合物层上的金属互连图案将芯片电连接到引脚。在另一个实施例中，芯片通过引线键与引脚互连。金属填充的通孔穿过芯片上的绝缘涂层，并与芯片焊盘电接触。连接到相应通孔并与连接到该通孔的芯片焊盘偏移的临时缓冲垫包括引线接合部位。

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