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1. 发明授权

US5134448A MOSFET with substrate source contact 失效
标题翻译： MOSFET与衬底源接触
公开(公告)号：US5134448A
公开(公告)日：1992-07-28
申请号：US643636
申请日：1991-01-22
申请人： Robert J. Johnsen , Paul W. Sanders
发明人： Robert J. Johnsen , Paul W. Sanders
IPC分类号： H01L21/336 , H01L21/74 , H01L29/10 , H01L29/41 , H01L29/423 , H01L29/78
CPC分类号： H01L29/1095 , H01L21/743 , H01L29/41 , H01L29/781 , H01L29/7813 , H01L29/42368
摘要： A MOSFET having a back-side source contact and top-side gate and drain contacts is provided by a structure comprising superposed N.sup.+, N-, P-, N.sup.+ regions arranged between top and bottom surfaces of the semiconductor die. In a preferred implementation, two trenches are etched from the top surface to the P-, N.sup.+ interface. A buried P-, N.sup.+ short is provided in one trench and a gate dielectric and gate electrode are provided over the sidewall P- region exposed in the other trench. This creates a vertical MOSFET in which the N.sup.+ substrate forms the source region shorted to the P- body region in which the channel is created by the gate. Superior performance is obtained in RF grounded-source circuit applications.
摘要翻译：具有背侧源极接触和顶侧栅极和漏极接触的MOSFET由包括叠置在半导体管芯的顶表面和底表面之间的N +，N-，P-，N +区域的结构提供。在优选的实施方案中，从顶表面到P，N +界面蚀刻两个沟槽。在一个沟槽中设置埋置的P-，N +短路，并且在暴露在另一个沟槽中的侧壁P-区域上设置栅极电介质和栅电极。这产生了垂直MOSFET，其中N +衬底形成与由栅极产生沟道的P-体区域短路的源极区域。在RF接地源电路应用中获得了卓越的性能。

2. 发明授权

US5023196A Method for forming a MOSFET with substrate source contact 失效
标题翻译：用于形成具有衬底源极接触的MOSFET的方法
公开(公告)号：US5023196A
公开(公告)日：1991-06-11
申请号：US471899
申请日：1990-01-29
申请人： Robert J. Johnsen , Paul W. Sanders
发明人： Robert J. Johnsen , Paul W. Sanders
IPC分类号： H01L21/336 , H01L21/74 , H01L29/10 , H01L29/41 , H01L29/423 , H01L29/78
CPC分类号： H01L29/7813 , H01L21/743 , H01L29/1095 , H01L29/41 , H01L29/781 , H01L29/42368 , Y10S148/168
摘要： A MOSFET having a back-side source contact and top-side gate and drain contacts is provided by a structure comprising superposed N.sup.+, N-,P-, N.sup.+ regions arranged between top and bottom surfaces of the semiconductor die. In a preferred implementation, two trenches are etched from the top surface to the P-, N.sup.+ interface. A buried P-, N.sup.+ short is provided in one trench and a gate dielectric and gate electrode are provided over the sidewall P- region exposed in the other trench. This creates a vertical MOSFET in which the N.sup.+ substrate forms the source region shorted to the P- body region in which the channel is created by the gate. Superior performance is obtained in RF grounded-source circuit applications.

3. 发明申请

US20130129714A1 PREVENTION AND TREATMENT OF CAST NEPHROPATHY 有权
标题翻译：预防和治疗慢性阻塞性肺疾病
公开(公告)号：US20130129714A1
公开(公告)日：2013-05-23
申请号：US13639002
申请日：2011-04-01
申请人： Paul W. Sanders
发明人： Paul W. Sanders
IPC分类号： C07K7/08 , C12N15/113 , C07K16/42
CPC分类号： C07K7/08 , A61K38/00 , C07K14/47 , C07K16/4241 , C07K2317/515 , C07K2317/565 , C12N15/113 , C12N2310/11 , C12N2310/14
摘要： Provided herein are polypeptides comprising or consisting essentially of a QSYDNTLSGSYVF (SEQ ID NO:1) or LSADSSGSYLYVF (SEQ ID NO:2) amino acid sequence. Also provided herein are methods of treating or preventing cast nephropathy in a subject. The methods comprise identifying a subject with or at risk of developing cast nephropathy and administering to the subject any of the polypeptides disclosed herein.
摘要翻译：本文提供的是包含或基本上由QSYDNTLSGSYVF（SEQ ID NO：1）或LSADSSGSYLYVF（SEQ ID NO：2）氨基酸序列组成的多肽。本文还提供了治疗或预防受试者中的肾性肾病的方法。所述方法包括鉴定患有或具有发展为流产性肾病的风险的受试者，并向受试者施用本文公开的任何多肽。

4. 发明申请

US20110272823A1 THROUGH SUBSTRATE VIAS 有权
标题翻译：通过基板VIAS
公开(公告)号：US20110272823A1
公开(公告)日：2011-11-10
申请号：US13188084
申请日：2011-07-21
申请人： Paul W. Sanders , Michael F. Petras , Chandrasekaram Ramiah
发明人： Paul W. Sanders , Michael F. Petras , Chandrasekaram Ramiah
IPC分类号： H01L21/28 , H01L23/48
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/12044 , H01L2924/3011 , H01L2924/00
摘要： Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region of a first thickness proximate the front surface of a substrate wafer by: (i) from the front surface, forming comparatively shallow vias of a first aspect ratio containing first conductors extending preferably through the first thickness but not through the initial wafer thickness, (ii) removing material from the rear surface to form a modified wafer of smaller final thickness with a new rear surface, and (iii) forming from the new rear surface, much deeper vias of second aspect ratios beneath the device region with second conductors therein contacting the first conductors, thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area. Both aspect ratios are desirably about ≦40, usefully ≦10 and preferably ≦5.
摘要翻译：在基本上所有的高温操作之后提供通过衬底通孔（TSV），所述高温操作是通过以下步骤形成靠近衬底晶片的前表面的第一厚度的器件区域：（i）从前表面形成第一方面的较浅的通孔比例包含优选地穿过第一厚度而不是通过初始晶片厚度的第一导体，（ii）从后表面去除材料以形成具有新的后表面的较小最终厚度的改性晶片，以及（iii）从新的后表面，在器件区域下方的第二宽高比的深度更深的通孔，其中其中第二导体接触第一导体，从而在制造和器件区域区域中基本上不影响晶片坚固性而提供前后互连。两个长宽比理想地约为＆lt; nlE; 40，有用地＆lt; 10;优选＆lt; nlE; 5。

5. 发明申请

US20100264548A1 THROUGH SUBSTRATE VIAS 有权
标题翻译：通过基板VIAS
公开(公告)号：US20100264548A1
公开(公告)日：2010-10-21
申请号：US12425159
申请日：2009-04-16
申请人： Paul W. Sanders , Michael F. Petras , Chandrasekaram Ramiah
发明人： Paul W. Sanders , Michael F. Petras , Chandrasekaram Ramiah
IPC分类号： H01L23/48 , H01L21/768
CPC分类号： H01L21/76898 , H01L23/481 , H01L2924/0002 , H01L2924/12044 , H01L2924/3011 , H01L2924/00
摘要： Through substrate vias (TSVs) are provided after substantially all high temperature operations needed to form a device region (26) of a first thickness (27) proximate the front surface (23) of a substrate wafer (20, 20′) by: (i) from the front surface (23), forming comparatively shallow vias (30, 30′) of a first aspect ratio containing first conductors (36, 36′) extending preferably through the first thickness (27) but not through the initial wafer (20) thickness (21), (ii) removing material (22″) from the rear surface (22) to form a modified wafer (20′) of smaller final thickness (21′) with a new rear surface (22′), and (iii) forming from the new rear surface (22′), much deeper vias (40, 40′) of second aspect ratios beneath the device region (26) with second conductors (56, 56′) therein contacting the first conductors (36, 36′), thereby providing front-to-back interconnections without substantially impacting wafer robustness during manufacturing and device region area. Both aspect ratios are desirably about ≦40, usefully ≦10 and preferably ≦5.
摘要翻译：在通过以下方式形成靠近基板晶片（20,20'）的前表面（23）的第一厚度（27）的器件区域（26）所需的基本上所有高温操作之后提供穿过衬底通孔（TSV）：（ i）从前表面（23）形成第一纵横比比较浅的通孔（30,30'），该第一纵横比包含优选地延伸穿过第一厚度（27）但不延伸穿过初始晶片的第一导体（36,36'） 20）厚度（21），（ii）从后表面（22）去除材料（22“）以形成具有新的后表面（22'）的较小最终厚度（21'）的改性晶片（20'），和（iii）从新的后表面（22'）形成在装置区域（26）下面的第二高宽比的更深的通孔（40,40'），其中第二导体（56,56'）在其中接触第一导体 36，36'），从而在制造和器件区域中基本上不影响晶片坚固性，从而提供前后互连区域。两个长宽比理想地约为＆lt; nlE; 40，有用地＆lt; 10;优选＆lt; nlE; 5。

6. 发明授权

US5734194A Semiconductor device and method of making 失效
标题翻译：半导体器件及其制造方法
公开(公告)号：US5734194A
公开(公告)日：1998-03-31
申请号：US792602
申请日：1997-01-31
申请人： Paul W. Sanders , Troy E. Mackie , Julio C. Costa , John L. Freeman, Jr. , Alan D. Wood
发明人： Paul W. Sanders , Troy E. Mackie , Julio C. Costa , John L. Freeman, Jr. , Alan D. Wood
IPC分类号： H01L29/73 , H01L21/265 , H01L21/331 , H01L29/08 , H01L29/732 , H01L27/082 , H01L27/102 , H01L29/70 , H01L31/11
CPC分类号： H01L29/66272 , H01L29/0804 , H01L29/0821 , H01L29/7322
摘要： A semiconductor device (10) is formed in a semiconductor substrate (11) that acts as a collector region. A base region (12) is formed in the semiconductor substrate (11) and an emitter region (52) is formed such that it contacts at least a portion of the base region (12). A conductive layer (28) is used to provide electrical connection to the emitter region (52). The portion of the conductive layer (28) above the emitter region (52) is counter-doped to address the problems of an interfacial oxide layer (27) that exists between the emitter region (52) and the conductive layer (28).
摘要翻译：半导体器件（10）形成在用作集电极区域的半导体衬底（11）中。在半导体衬底（11）中形成基极区（12），并且形成发射极区（52），使其与基极区（12）的至少一部分相接触。导电层（28）用于提供与发射极区域（52）的电连接。在发射极区域（52）上方的导电层（28）的部分被反掺杂以解决存在于发射极区域（52）和导电层（28）之间的界面氧化物层（27）的问题。

7. 发明申请

US20120037969A1 MONOLITHIC MICROWAVE INTEGRATED CIRCUIT 有权
标题翻译：单片微波集成电路
公开(公告)号：US20120037969A1
公开(公告)日：2012-02-16
申请号：US12855479
申请日：2010-08-12
申请人： Paul W. Sanders , Wayne R. Burger , Thuy B. Dao , Joel E. Keys , Michael F. Petras , Robert A. Pryor , Xiaowei Ren
发明人： Paul W. Sanders , Wayne R. Burger , Thuy B. Dao , Joel E. Keys , Michael F. Petras , Robert A. Pryor , Xiaowei Ren
IPC分类号： H01L27/06 , H01L21/82
CPC分类号： H01L23/66 , H01L21/76898 , H01L21/823475 , H01L23/481 , H01L23/5223 , H01L23/5226 , H01L23/5227 , H01L24/48 , H01L24/49 , H01L27/0617 , H01L27/0629 , H01L27/0727 , H01L28/10 , H01L28/40 , H01L29/7816 , H01L2223/6616 , H01L2223/6655 , H01L2223/6683 , H01L2224/48091 , H01L2224/49175 , H01L2225/06541 , H01L2924/00014 , H01L2924/12044 , H01L2924/13062 , H01L2924/14 , H01L2924/1423 , H01L2924/30107 , H03F3/195 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Low Q associated with passive components of monolithic integrated circuits (ICs) when operated at microwave frequencies can be avoided or mitigated using high resistivity (e.g., ≧100 Ohm-cm) semiconductor substrates (60) and lower resistance inductors (44′, 45′) for the IC (46). This eliminates significant in-substrate electromagnetic coupling losses from planar inductors (44, 45) and interconnections (50-1′, 52-1′, 94, 94′, 94″) overlying the substrate (60). The active transistor(s) (41′) are formed in the substrate (60) proximate the front face (63). Planar capacitors (42′, 43′) are also formed over the front face (63) of the substrate (60). Various terminals (42-1′, 42-2′, 43-1, 43-2′,50′, 51′, 52′, 42-1′, 42-2′, etc.) of the transistor(s) (41′), capacitor(s) (42′, 43′) and inductor(s) (44′, 45′) are coupled to a ground plane (69) on the rear face (62) of the substrate (60) using through-substrate-vias (98, 98′) to minimize parasitic resistance. Parasitic resistance associated with the planar inductors (44′, 45′) and heavy current carrying conductors (52-1′) is minimized by placing them on the outer surface of the IC where they can be made substantially thicker and of lower resistance. The result is a monolithic microwave IC (46, 58) previously unobtainable.
摘要翻译：使用高电阻率（例如≥100欧姆 - 厘米）的半导体衬底（60）和较低电阻电感（44'，45'）可以避免或减轻以微波频率操作时与单片集成电路（IC）的无源部件相关的低Q，）用于IC（46）。这消除了覆盖衬底（60）的平面电感器（44,45）和互连（50-1'，52-1'，94,94'，94“）的显着的衬底内电磁耦合损耗。有源晶体管（41'）在靠近前表面（63）的基底（60）中形成。平面电容器（42'，43'）也形成在衬底（60）的前表面（63）上方。晶体管的各个端子（42-1'，42-2'，43-1,43-2'，50'，51'，52'，42-1'，42-2'等）（41'），电容器（42'，43'）和电感器（44'，45'）耦合到衬底（60）的背面（62）上的接地平面（69）使用贯通衬底通孔（98,98'）来最小化寄生电阻。通过将平面电感器（44'，45'）和大电流承载导体（52-1'）相关联的寄生电阻放置在IC的外表面上，使其可以被制成基本上更厚且电阻更低。其结果是先前无法获得的单片微波IC（46,58）。

8. 发明申请

US20110156266A1 METHODS FOR FORMING THROUGH-SUBSTRATE CONDUCTOR FILLED VIAS, AND ELECTRONIC ASSEMBLIES FORMED USING SUCH METHODS 有权
标题翻译：形成通过基底导体填充VIAS的方法和使用这种方法形成的电子组件
公开(公告)号：US20110156266A1
公开(公告)日：2011-06-30
申请号：US13043094
申请日：2011-03-08
申请人： Chandrasekaram Ramiah , Douglas G. Mitchell , Michael F. Petras , Paul W. Sanders
发明人： Chandrasekaram Ramiah , Douglas G. Mitchell , Michael F. Petras , Paul W. Sanders
IPC分类号： H01L23/48 , H01L21/50
CPC分类号： H01L24/82 , H01L21/76898 , H01L23/3114 , H01L23/481 , H01L23/522 , H01L23/525 , H01L24/24 , H01L24/25 , H01L24/94 , H01L2224/12105 , H01L2224/16225 , H01L2224/24137 , H01L2224/82005 , H01L2224/94 , H01L2924/01018 , H01L2924/01021 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01073 , H01L2924/01074 , H01L2924/01078 , H01L2924/014 , H01L2924/09701 , H01L2924/12044 , H01L2924/14 , H01L2924/19041 , H01L2924/3011 , H01L2224/82
摘要： Through substrate vias for back-side electrical and thermal interconnections on very thin semiconductor wafers without loss of wafer mechanical strength during manufacturing are provided by: forming desired device regions with contacts on the front surface of an initially relatively thick wafer; etching via cavities partly through the wafer in the desired locations; filling the via cavities with a conductive material coupled to some device region contacts; mounting the wafer with its front side facing a support structure; thinning the wafer from the back side to expose internal ends of the conductive material filled vias; applying any desired back-side interconnect region coupled to the exposed ends of the filled vias; removing the support structure and separating the individual device or IC assemblies so as to be available for mounting on a further circuit board, tape or larger circuit.
摘要翻译：通过用于在非常薄的半导体晶片上进行背面电和热互连的衬底通孔，而不会在制造过程中丧失晶片的机械强度：通过在初始相对较厚的晶片的前表面上形成具有触点的所需器件区域来提供; 在期望的位置部分地通过晶片蚀刻孔; 用连接到一些设备区域接触件的导电材料填充通孔腔; 将晶片的正面安装在支撑结构上; 从背面使晶片变薄以暴露出导电材料填充的通孔的内端; 施加耦合到所述填充通孔的暴露端的任何期望的背面互连区域; 移除支撑结构并分离各个装置或IC组件，以便可用于安装在另外的电路板，带或更大的电路上。

9. 发明授权

US5670417A Method for fabricating self-aligned semiconductor component 失效
标题翻译：制造自对准半导体部件的方法
公开(公告)号：US5670417A
公开(公告)日：1997-09-23
申请号：US622535
申请日：1996-03-25
申请人： Charles T. Lambson , Paul W. Sanders
发明人： Charles T. Lambson , Paul W. Sanders
IPC分类号： H01L21/331 , H01L21/225
CPC分类号： H01L29/66272 , Y10S148/01 , Y10S148/011
摘要： A self-aligned semiconductor component (10) includes a layer (14) having two openings (36, 38) and overlying a doped region (13) in a substrate (11). One (36) of the two openings (36, 38) is used to self-align a different doped region (22) and a portion (27) of an electrode (27, 31). The electrode (27, 31) has another portion (31) overlying the self-aligned portion (27) to increase the current carrying capacity of the electrode (27, 31). A different electrode is formed in the other one (38) of the two openings (36, 38) and has a smaller current carrying capacity than the other electrode (27, 31).
摘要翻译：自对准半导体部件（10）包括具有两个开口（36,38）并且覆盖衬底（11）中的掺杂区域（13）的层（14）。两个开口（36,38）中的一个（36）用于自对准不同的掺杂区域（22）和电极（27,31）的部分（27）。电极（27,31）具有覆盖自对准部分（27）的另一部分（31），以增加电极（27,31）的载流能力。在两个开口（36,38）中的另一个（38）中形成不同的电极，并且具有比另一个电极（27,31）更小的载流能力。

10. 发明授权

US5139959A Method for forming bipolar transistor input protection 失效
标题翻译：形成双极晶体管输入保护的方法
公开(公告)号：US5139959A
公开(公告)日：1992-08-18
申请号：US822804
申请日：1992-01-21
申请人： Scott L. Craft , Stephen P. Robb , Paul W. Sanders
发明人： Scott L. Craft , Stephen P. Robb , Paul W. Sanders
IPC分类号： H01L27/02
CPC分类号： H01L29/7302 , H01L27/0248 , H01L29/0692 , Y10S148/011
摘要： A protective circuit for an input to a bipolar transistor (10) capable of operating in the microwave frequency range. In a first embodiment, a polysilicon diode (24) is connected across a base-emitter junction of the bipolar transistor (10). In a second embodiment, a polysilicon resistor (38) is connected in series with an emitter of the bipolar transistor (10), and the polysilicon diode (24) is connected across the series combination of the base-emitter junction and the polysilicon resistor (38). The layout of the transistor (10) and the islands of polysilicon (23, 25) housing the diode is critical since the bipolar transistor (10) is capable of operating in the microwave frequency range. In a first layout, an island of polysilicon (25) is centered between two transistor regions (47 and 48). In an exterior diode layout, a transistor region (51) is centered between two islands of polysilicon (23 and 25).
摘要翻译：一种用于能够在微波频率范围内工作的双极晶体管（10）的输入的保护电路。在第一实施例中，多晶硅二极管（24）跨越双极晶体管（10）的基极 - 发射极结连接。在第二实施例中，多晶硅电阻器（38）与双极晶体管（10）的发射极串联连接，并且多晶硅二极管（24）跨越基极 - 发射极结和多晶硅电阻器的串联组合 38）。晶体管（10）的布局和容纳二极管的多晶硅岛（23,25）的关键是至关重要的，因为双极晶体管（10）能够在微波频率范围内工作。在第一布局中，多晶硅岛（25）在两个晶体管区域（47和48）之间居中。在外部二极管布局中，晶体管区域（51）在两个多晶硅岛（23和25）之间居中。

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